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Searched refs:DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK (Results 1 – 7 of 7) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c498 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_S…
519 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_S…
540 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_S…
650 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_S…
671 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_S…
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28903 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro
H A Dgc_9_1_sh_mask.h30123 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h30458 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro
H A Dgc_9_4_2_sh_mask.h210 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h43261 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h48474 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK … macro