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Searched refs:DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h17281 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h18399 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_1_0_sh_mask.h30648 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h35810 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h29667 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h29266 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h34267 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h32185 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h38313 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h35085 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h34261 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h39762 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h39053 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h29263 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h37591 #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … macro