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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5793 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L macro
H A Ddce_8_0_sh_mask.h7951 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
H A Ddce_10_0_sh_mask.h6979 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
H A Ddce_11_0_sh_mask.h6881 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
H A Ddce_11_2_sh_mask.h7953 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
H A Ddce_12_0_sh_mask.h4909 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1531 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_1_0_sh_mask.h3871 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2377 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2518 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_2_sh_mask.h2002 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10632 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2569 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2448 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2645 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2515 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro