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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5801 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L macro
H A Ddce_8_0_sh_mask.h7959 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 macro
H A Ddce_10_0_sh_mask.h6987 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 macro
H A Ddce_11_0_sh_mask.h6889 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 macro
H A Ddce_11_2_sh_mask.h7961 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 macro
H A Ddce_12_0_sh_mask.h4913 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1535 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_1_0_sh_mask.h3875 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2381 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2522 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_2_sh_mask.h2006 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10636 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2573 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2452 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2649 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2519 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … macro