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Searched refs:DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_0_sh_mask.h27175 #define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK … macro
H A Ddpcs_4_2_2_sh_mask.h27329 #define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK … macro