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Searched refs:DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h16661 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_0_3_sh_mask.h17333 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_1_0_sh_mask.h28497 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_2_1_0_sh_mask.h34075 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_0_1_sh_mask.h27927 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_2_1_sh_mask.h37740 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_1_2_sh_mask.h42323 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_1_5_sh_mask.h40472 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_1_4_sh_mask.h36217 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_1_6_sh_mask.h43380 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_0_2_sh_mask.h32181 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_2_0_0_sh_mask.h37691 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_0_0_sh_mask.h36636 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
H A Ddcn_3_2_0_sh_mask.h37737 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h35731 #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT macro