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Searched refs:DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h6336 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 macro
H A Ddce_8_0_sh_mask.h9190 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h8666 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h8342 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h9604 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 macro