/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg, 87 const DebugLoc &DL, unsigned DReg, 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local 147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR() 431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument 438 .addReg(DReg, 0, Lane); in createExtractSubreg() 476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument 482 .addReg(DReg) in createInsertSubreg()
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H A D | ARMBaseInstrInfo.cpp | 5081 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane() 5082 return DReg; in getCorrespondingDRegAndLane() 5088 return DReg; in getCorrespondingDRegAndLane() 5111 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse() 5117 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse() 5135 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local 5186 .addReg(DReg, RegState::Undef) in setExecutionDomain() 5215 MIB.addReg(DReg, RegState::Define) in setExecutionDomain() 5216 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI))) in setExecutionDomain() 5391 if (!DReg || !MI.definesRegister(DReg, TRI)) in getPartialRegUpdateClearance() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 78 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local 80 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 935 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local 936 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs() 938 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs() 939 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs() 941 Defs &= ~(1 << DReg); in adjustLiveRegs() 967 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local 968 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs() 970 pushReg(DReg); in adjustLiveRegs() 971 Defs &= ~(1 << DReg); in adjustLiveRegs()
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/openbsd/gnu/llvm/llvm/lib/Target/M68k/MCTargetDesc/ |
H A D | M68kBaseInfo.h | 80 DReg = 0x8, enumerator
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 4902 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local 4905 unsigned TmpReg = DReg; in expandRotation() 4911 if (DReg == SReg) { in expandRotation() 4952 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation() 4965 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local 5015 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm() 5027 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local 5030 unsigned TmpReg = DReg; in expandDRotation() 5077 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation() 5090 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 469 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local 476 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/ |
H A D | CSKYISelLowering.cpp | 943 unsigned DReg = CSKY::F0_64 + RegNo; in getRegForInlineAsmConstraint() local 946 return std::make_pair(DReg, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint() 948 return std::make_pair(DReg, &CSKY::FPR64RegClass); in getRegForInlineAsmConstraint()
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/openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
H A D | M68kInstrInfo.td | 183 def MxDRegClass : MxOpClass<"DReg">;
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 3013 unsigned DReg = RegNo - LoongArch::F0 + LoongArch::F0_64; in getRegForInlineAsmConstraint() local 3014 return std::make_pair(DReg, &LoongArch::FPR64RegClass); in getRegForInlineAsmConstraint()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 13617 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local 13618 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
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