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Searched refs:DWB_OGAM_RAMB_REGION_0_1 (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb.h121 SR(DWB_OGAM_RAMB_REGION_0_1),\
339 SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
340 SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
341 SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
342 SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
826 uint32_t DWB_OGAM_RAMB_REGION_0_1; member
H A Ddcn30_dwb_cm.c140 gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1); in dwb3_program_ogam_lutb_settings()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h670 SR_ARR(DWB_OGAM_RAMB_REGION_0_1, id), \