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Searched refs:DestReg (Results 1 – 25 of 129) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
141 Register LdReg = DestReg; in emitThumbRegPlusImmInReg()
142 if (DestReg == ARM::SP) in emitThumbRegPlusImmInReg()
144 if (!isARMLowRegister(DestReg) && !DestReg.isVirtual()) in emitThumbRegPlusImmInReg()
174 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
218 if (DestReg == ARM::SP) { in emitThumbRegPlusImmediate()
230 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
254 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
320 BaseReg = DestReg; in emitThumbRegPlusImmediate()
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H A DThumb1InstrInfo.cpp41 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
109 Register DestReg, int FI, in loadRegFromStackSlot() argument
114 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
118 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
127 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
H A DThumb2InstrInfo.cpp136 if (!DestReg.isVirtual()) in optimizeSelect()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
235 if (DestReg.isVirtual()) { in loadRegFromStackSlot()
245 if (DestReg.isPhysical()) in loadRegFromStackSlot()
298 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
310 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
323 .addReg(DestReg) in emitT2RegPlusImmediate()
333 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
345 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
383 bool ToSP = DestReg == ARM::SP; in emitT2RegPlusImmediate()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp84 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
106 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
116 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
119 Src1Reg = DestReg; in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
126 Src2Reg = DestReg; in selectSELRMux()
132 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp472 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
508 .addReg(DestReg, RegState::Define) in copyPhysReg()
515 .addReg(DestReg) in copyPhysReg()
533 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
536 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
539 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp221 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
240 .addReg(DestReg) in doAtomicBinOpExpansion()
283 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
311 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
316 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
321 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
442 .addReg(DestReg) in expandAtomicMinMaxOp()
445 .addReg(DestReg) in expandAtomicMinMaxOp()
543 DestReg = MBBI->getOperand(0).getReg(); in tryToFoldBNEOnCmpXchgResult()
613 .addReg(DestReg) in expandAtomicCmpXchg()
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H A DRISCVMergeBaseOffset.cpp286 Register DestReg = Lo.getOperand(0).getReg(); in detectAndFoldOffset() local
291 if (!MRI->hasOneUse(DestReg)) in detectAndFoldOffset()
295 MachineInstr &Tail = *MRI->use_instr_begin(DestReg); in detectAndFoldOffset()
331 return foldLargeOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
338 return foldShiftedOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
346 Register DestReg = Lo.getOperand(0).getReg(); in foldIntoMemoryOps() local
361 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps()
386 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
388 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
418 llvm::make_early_inc_range(MRI->use_instructions(DestReg))) { in foldIntoMemoryOps()
H A DRISCVRegisterInfo.cpp189 Register ScratchReg = DestReg; in adjustReg()
190 if (DestReg == SrcReg) in adjustReg()
196 SrcReg = DestReg; in adjustReg()
201 if (DestReg == SrcReg && Val == 0) in adjustReg()
207 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
230 .addReg(DestReg, RegState::Kill) in adjustReg()
244 BuildMI(MBB, II, DL, TII->get(Opc), DestReg) in adjustReg()
365 Register DestReg = II->getOperand(0).getReg(); in lowerVRELOAD() local
371 TRI->getSubReg(DestReg, SubRegIdx + I)) in lowerVRELOAD()
441 Register DestReg; in eliminateFrameIndex() local
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp182 .addReg(DestReg) in doAtomicBinOpExpansion()
190 .addReg(DestReg) in doAtomicBinOpExpansion()
195 .addReg(DestReg) in doAtomicBinOpExpansion()
200 .addReg(DestReg) in doAtomicBinOpExpansion()
205 .addReg(DestReg) in doAtomicBinOpExpansion()
210 .addReg(DestReg) in doAtomicBinOpExpansion()
282 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
287 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
292 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
414 .addReg(DestReg) in expandAtomicMinMaxOp()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp423 if (Opnd.getReg() == DestReg) { in searchALUInst()
577 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
594 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
596 if (DestReg != BaseReg) in optTwoAddrLEA()
765 Register DestReg = Dest.getReg(); in processInstrForSlow3OpLEA() local
794 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) { in processInstrForSlow3OpLEA()
796 if (DestReg != BaseReg) in processInstrForSlow3OpLEA()
836 .addReg(DestReg); in processInstrForSlow3OpLEA()
841 .addReg(DestReg) in processInstrForSlow3OpLEA()
869 .addReg(DestReg) in processInstrForSlow3OpLEA()
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp780 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addImm(0), in emitLAInstSeq()
785 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
791 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
847 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressAbs()
866 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressPcrel()
912 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressGot()
957 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressTLSLE()
976 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressTLSIE()
1022 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressTLSLD()
1068 emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressTLSGD()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp393 return DestReg; in materializeFP()
401 return DestReg; in materializeFP()
417 emitInst(Mips::LW, DestReg) in materializeGV()
424 .addReg(DestReg) in materializeGV()
426 DestReg = TempReg; in materializeGV()
428 return DestReg; in materializeGV()
434 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
437 return DestReg; in materializeExternalCallSym()
1081 if (!DestReg) in selectFPTrunc()
1595 if (DestReg == 0) in fastLowerIntrinsicCall()
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H A DMipsSEInstrInfo.cpp124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
138 .addReg(DestReg) in copyPhysReg()
161 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
163 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
176 if (DestReg) in copyPhysReg()
177 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
329 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || in loadRegFromStack()
330 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); in loadRegFromStack()
384 if (DestReg == Mips::HI0) in loadRegFromStack()
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/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp423 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
431 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
432 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
436 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
447 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
461 } else if (SP::ASRRegsRegClass.contains(DestReg) && in copyPhysReg()
463 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
466 } else if (SP::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
468 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
480 Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]); in copyPhysReg()
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp266 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
267 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
268 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
270 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
276 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
353 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
360 MO.getReg() == DestReg) in AssignSlot()
366 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp43 unsigned DestReg;
67 void deleteDef(unsigned DestReg);
73 unsigned &DestReg);
112 return Info->DestReg; in phiInfoElementGetDest()
117 Info->DestReg = NewDef; in phiInfoElementSetDef()
200 NewElement->DestReg = DestReg; in addDest()
238 unsigned DestReg; in isSource() local
2035 unsigned DestReg; in rewriteLiveOutRegs() local
2053 unsigned DestReg = *DRI; in prunePHIInfo() local
2171 unsigned DestReg = *DRI; in createEntryPHIs() local
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/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp147 return BuildMI(MBB, II, DL, MCID, DestReg); in build()
150 return build(get(InstOpc), DestReg); in build()
264 Register DestReg = MI.getOperand(0).getReg(); in processLDQ() local
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
334 Register DestReg = MI.getOperand(0).getReg(); in processLDVM() local
354 build(VE::LVMir_m, DestReg) in processLDVM()
357 .addReg(DestReg); in processLDVM()
362 .addReg(DestReg); in processLDVM()
420 Register DestReg = MI.getOperand(0).getReg(); in processLDVM512() local
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H A DVEInstrInfo.cpp354 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysSubRegs()
364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { in copyPhysReg()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
406 << " to " << printReg(DestReg, TRI) << "\n"; in copyPhysReg()
539 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) in loadRegFromStackSlot()
545 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) in loadRegFromStackSlot()
551 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) in loadRegFromStackSlot()
557 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) in loadRegFromStackSlot()
563 BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg) in loadRegFromStackSlot()
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp77 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
80 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
84 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/openbsd/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
150 Register DestReg, int FI, in loadRegFromStackSlot() argument
159 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
161 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/openbsd/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp43 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
49 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
58 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
74 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
76 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
78 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
84 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
161 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp614 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
619 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
620 ActiveChains[DestReg] = G.get(); in scanInstruction()
627 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
632 if (DestReg != AccumReg) in scanInstruction()
647 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
649 if (DestReg != AccumReg) { in scanInstruction()
650 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
664 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h366 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
369 .addReg(DestReg, RegState::Define); in BuildMI()
378 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
384 .addReg(DestReg, RegState::Define); in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
402 .addReg(DestReg, RegState::Define); in BuildMI()
407 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
412 DestReg); in BuildMI()
413 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
419 return BuildMI(BB, *I, MIMD, MCID, DestReg); in BuildMI()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp59 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
65 Register::isVirtualRegister(DestReg) in copyPhysReg()
66 ? MRI.getRegClass(DestReg) in copyPhysReg()
67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
71 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp64 Register DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()

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