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Searched refs:EFLAGS (Results 1 – 25 of 37) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td148 let Defs = [EFLAGS] in {
193 } // Defs = [EFLAGS]
196 let Defs = [EFLAGS] in {
279 } // Defs = [EFLAGS]
390 } // Defs = [EFLAGS]
534 } // Defs = [EFLAGS]
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
927 // and use EFLAGS.
1038 let Uses = [EFLAGS], Defs = [EFLAGS] in {
1101 } // Uses = [EFLAGS], Defs = [EFLAGS]
[all …]
H A DX86InstrCMovSetCC.td17 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
44 timm:$cond, EFLAGS))]>, TB, OpSize16;
49 timm:$cond, EFLAGS))]>, TB, OpSize32;
54 timm:$cond, EFLAGS))]>, TB;
76 let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
79 [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
83 [(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
85 } // Uses = [EFLAGS]
[all …]
H A DX86InstrKL.td19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
26 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
32 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
39 Defs = [EFLAGS] in {
42 [(set VR128:$dst, EFLAGS,
48 [(set VR128:$dst, EFLAGS,
54 [(set VR128:$dst, EFLAGS,
60 [(set VR128:$dst, EFLAGS,
69 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86InstrCompiler.td38 // sub / add which can clobber EFLAGS.
56 // sub / add which can clobber EFLAGS.
84 let Defs = [EFLAGS] in {
263 Defs = [R10, R11, EFLAGS] in {
272 Defs = [R10, R11, EFLAGS] in {
376 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC],
533 let Defs = [EAX, ECX, EFLAGS, DF],
546 let Defs = [RAX, EFLAGS, DF],
697 let isCodeGenOnly = 1, Defs = [EFLAGS] in
946 let Defs = [AL, EFLAGS], Uses = [AL] in
[all …]
H A DX86FlagsCopyLowering.cpp388 MI.getOperand(0).getReg() == X86::EFLAGS) in runOnMachineFunction()
485 while (TestMBB->isLiveIn(X86::EFLAGS) && !TestMBB->pred_empty() && in runOnMachineFunction()
517 return MI.findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
581 if (MI.findRegisterDefOperand(X86::EFLAGS)) { in runOnMachineFunction()
631 assert(MI.findRegisterDefOperand(X86::EFLAGS) && in runOnMachineFunction()
659 if (SuccMBB->isLiveIn(X86::EFLAGS) && in runOnMachineFunction()
693 SuccMBB->removeLiveIn(X86::EFLAGS); in runOnMachineFunction()
720 (MI.getOperand(0).getReg() == X86::EFLAGS || in runOnMachineFunction()
721 MI.getOperand(1).getReg() == X86::EFLAGS)) { in runOnMachineFunction()
750 if (MI.findRegisterDefOperand(X86::EFLAGS)) in collectCondsInRegs()
[all …]
H A DX86InstrInfo.td38 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1502 let Defs = [EFLAGS] in {
1552 } // Defs = [EFLAGS]
2094 } // Defs = [EFLAGS]
2314 let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
2332 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2347 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2352 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2357 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2759 } // HasTBM, EFLAGS
[all …]
H A DX86CmovConversion.cpp354 if (I.definesRegister(X86::EFLAGS)) { in collectCmovCandidates()
581 if (MI->killsRegister(X86::EFLAGS)) in checkEFLAGSLive()
591 if (I->readsRegister(X86::EFLAGS)) in checkEFLAGSLive()
593 if (I->definesRegister(X86::EFLAGS)) in checkEFLAGSLive()
599 if (Succ->isLiveIn(X86::EFLAGS)) in checkEFLAGSLive()
692 FalseMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
693 SinkMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
H A DX86SpeculativeLoadHardening.cpp487 ZeroI->findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
737 bool LiveEFLAGS = Succ.isLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
739 CheckingMBB.addLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
1077 assert(!MBB.isLiveIn(X86::EFLAGS) && in tracePredStateThroughIndirectBranches()
1227 if (MI.killsRegister(X86::EFLAGS, &TRI)) in isEFLAGSLive()
1233 return MBB.isLiveIn(X86::EFLAGS); in isEFLAGSLive()
1541 ShiftI->addRegisterDead(X86::EFLAGS, TRI); in mergePredStateIntoSP()
1546 OrI->addRegisterDead(X86::EFLAGS, TRI); in mergePredStateIntoSP()
1566 ShiftI->addRegisterDead(X86::EFLAGS, TRI); in extractPredStateFromSP()
1744 OrI->addRegisterDead(X86::EFLAGS, TRI); in hardenLoadAddr()
[all …]
H A DX86FixupSetCC.cpp72 if (MI.definesRegister(X86::EFLAGS)) in runOnMachineFunction()
97 if (FlagsDefMI->readsRegister(X86::EFLAGS)) in runOnMachineFunction()
H A DX86InstrTSX.td42 let Defs = [EFLAGS] in
44 "xtest", [(set EFLAGS, (X86xtest))]>, PS, Requires<[HasRTM]>;
H A DX86InstrFPStack.td130 // Clobbers EFLAGS due to OR instruction used internally.
132 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in {
449 cc, EFLAGS))]>;
453 cc, EFLAGS))]>;
457 cc, EFLAGS))]>,
462 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
471 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
679 let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
681 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
684 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
[all …]
H A DX86FixupLEAs.cpp439 if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI)) in searchALUInst()
536 NewMI1->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
541 NewMI2->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
568 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) != in optTwoAddrLEA()
708 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstructionForSlowLEA()
760 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstrForSlow3OpLEA()
H A DX86InstrControl.td73 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
78 [(X86brcond bb:$dst, timm:$cond, EFLAGS)]>;
311 // rather than barriers, and they use EFLAGS.
314 let Uses = [ESP, EFLAGS, SSP] in {
435 // rather than barriers, and they use EFLAGS.
438 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86LoadValueInjectionRetHardening.cpp101 ->addRegisterDead(X86::EFLAGS, TRI); in runOnMachineFunction()
H A DX86InstrShiftRotate.td15 let Defs = [EFLAGS] in {
337 let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in {
346 } // Uses = [CL, EFLAGS], SchedRW
348 let Uses = [EFLAGS], SchedRW = [WriteRotate] in {
365 } // Uses = [EFLAGS], SchedRW
376 } // Uses = [CL, EFLAGS], SchedRW
378 let Uses = [EFLAGS], SchedRW = [WriteRotate] in {
395 } // Uses = [EFLAGS], SchedRW
436 } // Uses = [EFLAGS], SchedRW
458 } // Uses = [CL, EFLAGS], SchedRW
[all …]
H A DX86RegisterInfo.cpp691 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) && in adjustStackMapLiveOutMask()
695 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
H A DX86InstrSystem.td47 let Uses = [EFLAGS] in
682 let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
702 // IF (inside EFLAGS) management instructions.
703 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
767 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
H A DX86InstrInfo.cpp944 MO.getReg() == X86::EFLAGS && !MO.isDead()) { in hasLiveCondCodeDef()
1036 if (Instr.modifiesRegister(X86::EFLAGS, TRI)) in findRedundantFlagInstr()
3229 if (MI.modifiesRegister(X86::EFLAGS, TRI)) { in analyzeBranchPredicate()
3234 if (MI.readsRegister(X86::EFLAGS, TRI)) in analyzeBranchPredicate()
3243 if (Succ->isLiveIn(X86::EFLAGS)) in analyzeBranchPredicate()
3563 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) { in copyPhysReg()
4425 if (Inst.modifiesRegister(X86::EFLAGS, TRI)) { in optimizeCompareInstr()
4621 if (Successor->isLiveIn(X86::EFLAGS)) in optimizeCompareInstr()
4640 if (!Instr->readsRegister(X86::EFLAGS, TRI) && in optimizeCompareInstr()
4668 if (!MBB->isLiveIn(X86::EFLAGS)) in optimizeCompareInstr()
[all …]
H A DX86ExpandPseudo.cpp122 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
123 MBB->addLiveIn(X86::EFLAGS); in INITIALIZE_PASS()
H A DX86FrameLowering.cpp192 if (Reg != X86::EFLAGS) in flagsNeedToBePreservedBeforeTheTerminators()
213 if (Succ->isLiveIn(X86::EFLAGS)) in flagsNeedToBePreservedBeforeTheTerminators()
343 UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS); in BuildStackAdjustment()
739 assert(MBB.computeRegisterLiveness(TRI, X86::EFLAGS, MBBI) != in emitStackProbeInlineGenericLoop()
880 assert(MBB.computeRegisterLiveness(TRI, X86::EFLAGS, MBBI) != in emitStackProbeInlineWindowsCoreCLR64()
1120 assert(MBB.computeRegisterLiveness(TRI, X86::EFLAGS, MBBI) != in emitStackProbeCall()
1154 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); in emitStackProbeCall()
3595 if (!MBB.isLiveIn(X86::EFLAGS)) in canUseAsPrologue()
H A DX86ISelLowering.cpp25283 return EFLAGS; in emitFlagsForSetcc()
25360 SDValue EFLAGS; in LowerSETCC() local
25363 EFLAGS = in LowerSETCC()
46651 return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, in combinePTESTCC()
46660 return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, in combinePTESTCC()
46672 return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, in combinePTESTCC()
46680 return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, in combinePTESTCC()
54195 SDValue EFLAGS; in combineAddOrSubToADCOrSBB() local
54204 if (!EFLAGS) in combineAddOrSubToADCOrSBB()
54231 EFLAGS.getOperand(1), EFLAGS.getOperand(0)); in combineAddOrSubToADCOrSBB()
[all …]
H A DX86RegisterInfo.td314 def EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>;
315 def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>;
575 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
/openbsd/gnu/usr.bin/binutils/gdb/
H A Damd64-linux-nat.c67 RIP * 8, EFLAGS * 8, /* %rip, %eflags */
89 RIP * 8, EFLAGS * 8, /* %eip, %eflags */
/openbsd/gnu/usr.bin/binutils/gdb/gdbserver/
H A Dlinux-x86-64-low.c64 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
/openbsd/gnu/llvm/llvm/docs/TableGen/
H A Dindex.rst68 ECX, EDI, EDX, EFLAGS, EIP, ESI, ESP, FP0, FP1, FP2, FP3, FP4, FP5, FP6, IP,
110 list<Register> Defs = [EFLAGS];
167 let Defs = [EFLAGS],

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