1 /* $OpenBSD: ehcireg.h,v 1.21 2016/10/02 06:36:39 kettenis Exp $ */ 2 /* $NetBSD: ehcireg.h,v 1.17 2004/06/23 06:45:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_EHCIREG_H_ 34 #define _DEV_PCI_EHCIREG_H_ 35 36 /*** PCI config registers ***/ 37 38 #define PCI_CBMEM 0x10 /* configuration base MEM */ 39 40 #define PCI_INTERFACE_EHCI 0x20 41 42 #define PCI_USBREV 0x60 /* RO USB protocol revision */ 43 #define PCI_USBREV_MASK 0xff 44 #define PCI_USBREV_PRE_1_0 0x00 45 #define PCI_USBREV_1_0 0x10 46 #define PCI_USBREV_1_1 0x11 47 #define PCI_USBREV_2_0 0x20 48 49 #define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */ 50 51 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 52 53 /* EHCI Extended Capabilities */ 54 #define EHCI_EC_LEGSUP 0x01 55 56 #define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff) 57 #define EHCI_EECP_ID(x) ((x) & 0xff) 58 59 #define EHCI_LEGSUP_LEGSUP 0x00 60 #define EHCI_LEGSUP_OSOWNED 0x01000000 /* OS owned semaphore */ 61 #define EHCI_LEGSUP_BIOSOWNED 0x00010000 /* BIOS owned semaphore */ 62 #define PCI_LEGSUP_USBLEGCTLSTS 0x04 63 64 /*** EHCI capability registers ***/ 65 66 #define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */ 67 /* reserved 0x01 */ 68 #define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 69 70 #define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 71 #define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 72 #define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 73 #define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 74 #define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 75 #define EHCI_HCS_PRR(x) ((x) & 0x80) /* port routing rules */ 76 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 77 #define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 78 79 #define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 80 #define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 81 #define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 82 #define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 83 #define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 84 #define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 85 86 #define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */ 87 88 /* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 89 #define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 90 #define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 91 #define EHCI_CMD_ITC_1 0x00010000 92 #define EHCI_CMD_ITC_2 0x00020000 93 #define EHCI_CMD_ITC_4 0x00040000 94 #define EHCI_CMD_ITC_8 0x00080000 95 #define EHCI_CMD_ITC_16 0x00100000 96 #define EHCI_CMD_ITC_32 0x00200000 97 #define EHCI_CMD_ITC_64 0x00400000 98 #define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 99 #define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 100 #define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 101 #define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */ 102 #define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 103 #define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 104 #define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 105 #define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 106 #define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 107 #define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 108 109 #define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 110 #define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 111 #define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 112 #define EHCI_STS_REC 0x00002000 /* RO reclamation */ 113 #define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 114 #define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 115 #define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 116 #define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 117 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 118 #define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 119 #define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 120 #define EHCI_STS_INTRS(x) ((x) & 0x3f) 121 122 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 123 124 #define EHCI_USBINTR 0x08 /* RW Interrupt register */ 125 #define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */ 126 #define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 127 #define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 128 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 129 #define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 130 #define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 131 132 #define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 133 134 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 135 136 #define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 137 #define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 138 139 #define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 140 #define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 141 142 #define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */ 143 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 144 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 145 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 146 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 147 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 148 #define EHCI_PS_PO 0x00002000 /* RW port owner */ 149 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 150 #define EHCI_PS_LS 0x00000c00 /* RO line status */ 151 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 152 #define EHCI_PS_PR 0x00000100 /* RW port reset */ 153 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 154 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 155 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 156 #define EHCI_PS_OCA 0x00000010 /* RO over current active */ 157 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 158 #define EHCI_PS_PE 0x00000004 /* RW port enable */ 159 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 160 #define EHCI_PS_CS 0x00000001 /* RO connect status */ 161 #define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) 162 163 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 164 165 /* Nonstandard register to set controller mode. */ 166 #define EHCI_USBMODE 0x68 167 #define EHCI_USBMODE_CM_M 0x00000003 168 #define EHCI_USBMODE_CM_IDLE 0x00000000 169 #define EHCI_USBMODE_CM_DEVICE 0x00000002 170 #define EHCI_USBMODE_CM_HOST 0x00000003 171 172 #define EHCI_FLALIGN_ALIGN 0x1000 173 174 /* No data structure may cross a page boundary. */ 175 #define EHCI_PAGE_SIZE 0x1000 176 #define EHCI_PAGE(x) ((x) &~ 0xfff) 177 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff) 178 179 typedef u_int32_t ehci_link_t; 180 #define EHCI_LINK_TERMINATE 0x00000001 181 #define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 182 #define EHCI_LINK_ITD 0x0 183 #define EHCI_LINK_QH 0x2 184 #define EHCI_LINK_SITD 0x4 185 #define EHCI_LINK_FSTN 0x6 186 #define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 187 188 typedef u_int32_t ehci_physaddr_t; 189 typedef u_int32_t ehci_isoc_trans_t; 190 typedef u_int32_t ehci_isoc_bufr_ptr_t; 191 #define EHCI_BUFPTR_MASK 0xfffff000 192 193 /* Isochronous Transfer Descriptor */ 194 #define EHCI_ITD_NTRANS 8 195 #define EHCI_ITD_NBUFFERS 7 196 struct ehci_itd { 197 volatile ehci_link_t itd_next; 198 volatile ehci_isoc_trans_t itd_ctl[8]; 199 #define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf) 200 #define EHCI_ITD_SET_STATUS(x) (((x) & 0xf) << 28) 201 #define EHCI_ITD_ACTIVE 0x80000000 202 #define EHCI_ITD_BUF_ERR 0x40000000 203 #define EHCI_ITD_BABBLE 0x20000000 204 #define EHCI_ITD_ERROR 0x10000000 205 #define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xfff) 206 #define EHCI_ITD_SET_LEN(x) (((x) & 0xfff) << 16) 207 #define EHCI_ITD_IOC 0x8000 208 #define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 1) 209 #define EHCI_ITD_SET_IOC(x) (((x) << 15) & EHCI_ITD_IOC) 210 #define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) 211 #define EHCI_ITD_SET_PG(x) (((x) & 0x7) << 12) 212 #define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xfff) 213 #define EHCI_ITD_SET_OFFS(x) (((x) & 0xfff) << 0) 214 volatile ehci_isoc_bufr_ptr_t itd_bufr[7]; 215 #define EHCI_ITD_GET_ENDPT(x) (((x) >> 8) & 0xf) 216 #define EHCI_ITD_SET_ENDPT(x) (((x) & 0xf) << 8) 217 #define EHCI_ITD_GET_DADDR(x) ((x) & 0x7f) 218 #define EHCI_ITD_SET_DADDR(x) ((x) & 0x7f) 219 #define EHCI_ITD_GET_DIR(x) (((x) >> 11) & 1) 220 #define EHCI_ITD_SET_DIR(x) (((x) & 1) << 11) 221 #define EHCI_ITD_GET_MAXPKT(x) ((x) & 0x7ff) 222 #define EHCI_ITD_SET_MAXPKT(x) ((x) & 0x7ff) 223 #define EHCI_ITD_GET_MULTI(x) ((x) & 0x3) 224 #define EHCI_ITD_SET_MULTI(x) ((x) & 0x3) 225 volatile ehci_isoc_bufr_ptr_t itd_bufr_hi[7]; 226 }; 227 #define EHCI_ITD_ALIGN 32 228 229 /* Split Transaction Isochronous Transfer Descriptor */ 230 struct ehci_sitd { 231 volatile ehci_link_t sitd_next; 232 volatile u_int32_t sitd_endp; 233 #define EHCI_SITD_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 234 #define EHCI_SITD_SET_ADDR(x) (x) 235 #define EHCI_SITD_GET_ENDPT(x) (((x) >> 8) & 0xf) /* endpoint no */ 236 #define EHCI_SITD_SET_ENDPT(x) ((x) << 8) 237 #define EHCI_SITD_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 238 #define EHCI_SITD_SET_HUBA(x) ((x) << 16) 239 #define EHCI_SITD_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 240 #define EHCI_SITD_SET_PORT(x) ((x) << 23) 241 #define EHCI_SITD_GET_DIR(x) (((x) >> 31) & 0x1) /* direction */ 242 #define EHCI_SITD_SET_DIR(x) ((x) << 31) 243 volatile u_int32_t sitd_sched; 244 #define EHCI_SITD_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 245 #define EHCI_SITD_SET_SMASK(x) ((x) << 0) 246 #define EHCI_SITD_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 247 #define EHCI_SITD_SET_CMASK(x) ((x) << 8) 248 volatile u_int32_t sitd_trans; 249 #define EHCI_SITD_IOC 0x80000000 250 #define EHCI_SITD_ACTIVE 0x80 251 #define EHCI_SITD_ERR 0x40 252 #define EHCI_SITD_BUFERR 0x20 253 #define EHCI_SITD_BABBLE 0x10 254 #define EHCI_SITD_XACTERR 0x08 255 #define EHCI_SITD_MISSEDMICRO 0x04 256 #define EHCI_SITD_SPLITXSTATE 0x02 257 #define EHCI_SITD_GET_LEN(x) (((x) >> 16) & 0x3ff) /* bytes to transfer */ 258 #define EHCI_SITD_SET_LEN(x) (((x) & 0x3ff) << 16) 259 #define EHCI_SITD_GET_PG(x) (((x) >> 30) & 0x1) /* buffer page */ 260 #define EHCI_SITD_SET_PG(x) ((x) << 30) 261 volatile ehci_physaddr_t sitd_bufr[2]; 262 #define EHCI_SITD_GET_TCOUNT(x) (((x) >> 0) & 0x7) /* transaction count */ 263 #define EHCI_SITD_SET_TCOUNT(x) ((x) << 0) 264 #define EHCI_SITD_GET_TP(x) (((x) >> 3) & 0x3) /* transaction position */ 265 #define EHCI_SITD_SET_TP(x) ((x) << 3) 266 #define EHCI_SITD_TP_ALL 0x0 267 #define EHCI_SITD_TP_BEGIN 0x1 268 #define EHCI_SITD_TP_MIDDLE 0x2 269 #define EHCI_SITD_TP_END 0x3 270 volatile ehci_link_t sitd_back; 271 volatile ehci_physaddr_t sitd_bufr_hi[2]; /* 64bit */ 272 }; 273 #define EHCI_SITD_ALIGN 32 274 275 /* Queue Element Transfer Descriptor */ 276 #define EHCI_QTD_NBUFFERS 5 277 struct ehci_qtd { 278 ehci_link_t qtd_next; 279 ehci_link_t qtd_altnext; 280 u_int32_t qtd_status; 281 #define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) 282 #define EHCI_QTD_SET_STATUS(x) ((x) << 0) 283 #define EHCI_QTD_ACTIVE 0x80 284 #define EHCI_QTD_HALTED 0x40 285 #define EHCI_QTD_BUFERR 0x20 286 #define EHCI_QTD_BABBLE 0x10 287 #define EHCI_QTD_XACTERR 0x08 288 #define EHCI_QTD_MISSEDMICRO 0x04 289 #define EHCI_QTD_SPLITXSTATE 0x02 290 #define EHCI_QTD_PINGSTATE 0x01 291 #define EHCI_QTD_STATERRS 0x7c 292 #define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3) 293 #define EHCI_QTD_SET_PID(x) ((x) << 8) 294 #define EHCI_QTD_PID_OUT 0x0 295 #define EHCI_QTD_PID_IN 0x1 296 #define EHCI_QTD_PID_SETUP 0x2 297 #define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3) 298 #define EHCI_QTD_SET_CERR(x) ((x) << 10) 299 #define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7) 300 #define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) 301 #define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1) 302 #define EHCI_QTD_IOC 0x00008000 303 #define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff) 304 #define EHCI_QTD_SET_BYTES(x) ((x) << 16) 305 #define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1) 306 #define EHCI_QTD_SET_TOGGLE(x) ((x) << 31) 307 #define EHCI_QTD_TOGGLE_MASK 0x80000000 308 ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 309 ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 310 }; 311 #define EHCI_QTD_ALIGN 32 312 313 /* Queue Head */ 314 struct ehci_qh { 315 ehci_link_t qh_link; 316 u_int32_t qh_endp; 317 #define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 318 #define EHCI_QH_SET_ADDR(x) (x) 319 #define EHCI_QH_ADDRMASK 0x0000007f 320 #define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */ 321 #define EHCI_QH_INACT 0x00000080 322 #define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */ 323 #define EHCI_QH_SET_ENDPT(x) ((x) << 8) 324 #define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */ 325 #define EHCI_QH_SET_EPS(x) ((x) << 12) 326 #define EHCI_QH_SPEED_FULL 0x0 327 #define EHCI_QH_SPEED_LOW 0x1 328 #define EHCI_QH_SPEED_HIGH 0x2 329 #define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */ 330 #define EHCI_QH_DTC 0x00004000 331 #define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */ 332 #define EHCI_QH_HRECL 0x00008000 333 #define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */ 334 #define EHCI_QH_SET_MPL(x) ((x) << 16) 335 #define EHCI_QH_MPLMASK 0x07ff0000 336 #define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */ 337 #define EHCI_QH_CTL 0x08000000 338 #define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */ 339 #define EHCI_QH_SET_NRL(x) ((x) << 28) 340 u_int32_t qh_endphub; 341 #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 342 #define EHCI_QH_SET_SMASK(x) ((x) << 0) 343 #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 344 #define EHCI_QH_SET_CMASK(x) ((x) << 8) 345 #define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 346 #define EHCI_QH_SET_HUBA(x) ((x) << 16) 347 #define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 348 #define EHCI_QH_SET_PORT(x) ((x) << 23) 349 #define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */ 350 #define EHCI_QH_SET_MULT(x) ((x) << 30) 351 ehci_link_t qh_curqtd; 352 struct ehci_qtd qh_qtd; 353 }; 354 #define EHCI_QH_ALIGN 32 355 356 /* Periodic Frame Span Traversal Node */ 357 struct ehci_fstn { 358 ehci_link_t fstn_link; 359 ehci_link_t fstn_back; 360 }; 361 #define EHCI_FSTN_ALIGN 32 362 363 #endif /* _DEV_PCI_EHCIREG_H_ */ 364