1 /* $OpenBSD: esmreg.h,v 1.10 2005/12/13 02:31:45 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Jordan Hargrave <jordan@openbsd.org> 5 * Copyright (c) 2005 David Gwynne <dlg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define ESM2_BASE_PORT 0xe0 21 22 #define ESM2_CTRL_REG 4 23 #define ESM2_DATA_REG 5 24 #define ESM2_INTMASK_REG 6 25 26 #define ESM2_TC_CLR_WPTR (1L << 0) 27 #define ESM2_TC_CLR_RPTR (1L << 1) 28 #define ESM2_TC_H2ECDB (1L << 2) 29 #define ESM2_TC_EC2HDB (1L << 3) 30 #define ESM2_TC_EVENTDB (1L << 4) 31 #define ESM2_TC_HBDB (1L << 5) 32 #define ESM2_TC_HOSTBUSY (1L << 6) 33 #define ESM2_TC_ECBUSY (1L << 7) 34 #define ESM2_TC_READY (ESM2_TC_EC2HDB | ESM2_TC_H2ECDB | \ 35 ESM2_TC_ECBUSY) 36 #define ESM2_TC_POWER_UP_BITS (ESM2_TC_CLR_WPTR | ESM2_TC_CLR_RPTR | \ 37 ESM2_TC_EC2HDB | ESM2_TC_EVENTDB) 38 39 #define ESM2_TIM_HIRQ_PEND (1L << 1) 40 #define ESM2_TIM_SCI_EN (1L << 2) 41 #define ESM2_TIM_SMI_EN (1L << 3) 42 #define ESM2_TIM_NMI2SMI (1L << 4) 43 #define ESM2_TIM_POWER_UP_BITS (ESM2_TIM_HIRQ_PEND) 44 45 #define ESM2_CMD_NOOP 0x00 46 #define ESM2_CMD_ECHO 0x01 47 #define ESM2_CMD_DEVICEMAP 0x03 48 #define ESM2_DEVICEMAP_READ 0x00 49 50 #define ESM2_CMD_HWDC 0x05 /* Host Watch Dog Control */ 51 #define ESM2_HWDC_WRITE_STATE 0x01 52 #define ESM2_HWDC_READ_PROPERTY 0x02 53 #define ESM2_HWDC_WRITE_PROPERTY 0x03 54 55 #define ESM2_CMD_SMB_BUF 0x20 56 #define ESM2_CMD_SMB_BUF_XMIT_RECV 0x21 57 #define ESM2_CMD_SMB_XMIT_RECV 0x22 58 #define ESM2_SMB_SENSOR_VALUE 0x04 59 #define ESM2_SMB_SENSOR_THRESHOLDS 0x19 60 61 #define ESM2_MAX_CMD_LEN 0x20 62 #define ESM2_UUID_LEN 0x08 63 64 #define DELL_SYSSTR_ADDR 0xFE076L 65 #define DELL_SYSID_ADDR 0xFE840L 66 67 #define DELL_SYSID_2300 0x81 68 #define DELL_SYSID_4300 0x7C 69 #define DELL_SYSID_4350 0x84 70 #define DELL_SYSID_6300 0x7F 71 #define DELL_SYSID_6350 0x83 72 #define DELL_SYSID_2400 0x9B 73 #define DELL_SYSID_2450 0xA6 74 #define DELL_SYSID_4400 0x9A 75 #define DELL_SYSID_6400 0x9C 76 #define DELL_SYSID_6450 0xA2 77 #define DELL_SYSID_2500 0xD9 78 #define DELL_SYSID_2550 0xD1 79 #define DELL_SYSID_PV530F 0xCD 80 #define DELL_SYSID_PV735N 0xE2 81 #define DELL_SYSID_PV750N 0xEE 82 #define DELL_SYSID_PV755N 0xEF 83 #define DELL_SYSID_PA200 0xCB 84 #define DELL_SYSID_EXT 0xFE 85 86 struct dell_sysid { 87 u_int16_t ext_id; 88 u_int8_t bios_ver[3]; 89 u_int8_t sys_id; 90 } __packed; 91 92 struct esm_wdog_prop { 93 u_int8_t cmd; 94 u_int8_t reserved; 95 u_int8_t subcmd; 96 u_int8_t action; 97 u_int32_t time; 98 } __packed; 99 100 #define ESM_WDOG_DISABLE 0x00 101 #define ESM_WDOG_PWROFF (1L << 1) 102 #define ESM_WDOG_PWRCYCLE (1L << 2) 103 #define ESM_WDOG_RESET (1L << 3) 104 #define ESM_WDOG_NOTIFY (1L << 4) 105 106 struct esm_wdog_state { 107 u_int8_t cmd; 108 u_int8_t reserved; 109 u_int8_t subcmd; 110 u_int8_t state; 111 } __packed; 112 113 struct esm_devmap { 114 u_int8_t index; 115 u_int8_t dev_major; 116 u_int8_t dev_minor; 117 u_int8_t rev_major; 118 u_int8_t rev_minor; 119 u_int8_t rev_rom; 120 u_int8_t smb_addr; 121 u_int8_t status; 122 u_int8_t monitor_type; 123 u_int8_t pollcycle; 124 u_int8_t uniqueid[ESM2_UUID_LEN]; 125 } __packed; 126 127 struct esm_devmap_req { 128 u_int8_t cmd; 129 u_int8_t initiator; 130 u_int8_t action; 131 u_int8_t index; 132 u_int8_t ndev; 133 } __packed; 134 135 struct esm_devmap_resp { 136 u_int8_t status; 137 u_int8_t ndev; 138 struct esm_devmap devmap[1]; /* request one map at a time */ 139 } __packed; 140 141 /* ESM SMB requests */ 142 143 struct esm_smb_req_val { 144 u_int8_t v_cmd; 145 u_int8_t v_initiator; 146 u_int8_t v_sensor; 147 } __packed; 148 149 struct esm_smb_req_thr { 150 u_int8_t t_cmd; 151 u_int8_t t_sensor; 152 } __packed; 153 154 struct esm_smb_req { 155 struct { 156 u_int8_t _cmd; 157 u_int8_t _dev; 158 u_int8_t _txlen; 159 u_int8_t _rxlen; 160 } __packed hdr; 161 #define h_cmd hdr._cmd 162 #define h_dev hdr._dev 163 #define h_txlen hdr._txlen 164 #define h_rxlen hdr._rxlen 165 166 union { 167 struct esm_smb_req_val _val; 168 struct esm_smb_req_thr _thr; 169 } __packed _; 170 #define req_val _._val 171 #define req_thr _._thr 172 173 } __packed; 174 175 /* ESM SMB responses */ 176 177 struct esm_smb_resp_val { 178 u_int16_t v_reading; 179 u_int8_t v_status; 180 u_int8_t v_checksum; 181 } __packed; 182 183 struct esm_smb_resp_thr { 184 u_int8_t t_sensor; 185 u_int16_t t_lo_fail; 186 u_int16_t t_hi_fail; 187 u_int16_t t_lo_warn; 188 u_int16_t t_hi_warn; 189 u_int16_t t_hysterisis; 190 u_int8_t t_checksum; 191 } __packed; 192 193 struct esm_smb_resp { 194 struct { 195 u_int8_t _status; 196 u_int8_t _i2csts; 197 u_int8_t _procsts; 198 u_int8_t _tx; 199 u_int8_t _rx; 200 } __packed hdr; 201 #define h_status hdr._status 202 #define h_i2csts hdr._i2csts 203 #define h_procsts hdr._procsts 204 #define h_tx hdr._tx 205 #define h_rx hdr._rx 206 207 union { 208 struct esm_smb_resp_val _val; 209 struct esm_smb_resp_thr _thr; 210 } __packed _; 211 #define resp_val _._val 212 #define resp_thr _._thr 213 } __packed; 214 215 /* esm_smb_resp_val drive values */ 216 #define ESM2_V_DRV_EMPTY 1 217 #define ESM2_V_DRV_READY 2 218 #define ESM2_V_DRV_POWERUP 3 219 #define ESM2_V_DRV_ONLINE 4 220 #define ESM2_V_DRV_IDLE 5 221 #define ESM2_V_DRV_ACTIVE 6 222 #define ESM2_V_DRV_REBUILD 7 223 #define ESM2_V_DRV_POWERDOWN 8 224 #define ESM2_V_DRV_FAIL 9 225 #define ESM2_V_DRV_PFAIL 10 226 227 /* esm_smb_resp_val powersupply values */ 228 #define ESM2_V_PSU_ID(x) ((x)>>8 & 0xff) 229 #define ESM2_V_PSU_AC (1<<0) 230 #define ESM2_V_PSU_SW (1<<1) 231 #define ESM2_V_PSU_OK (1<<2) 232 #define ESM2_V_PSU_ON (1<<3) 233 #define ESM2_V_PSU_FFAN (1<<4) 234 #define ESM2_V_PSU_OTMP (1<<5) 235 236 /* esm_smb_resp_val status */ 237 #define ESM2_VS_VALID (1<<2) 238 /* the powersupplies have a special status field */ 239 #define ESM2_VS_PSU_INST (1<<0) 240 #define ESM2_VS_PSU_PSON (1<<1) 241 #define ESM2_VS_PSU_FAIL (1<<2) 242 #define ESM2_VS_PSU_PSDB (1<<3) 243 244 enum esm_dev_type { 245 ESM2_DEV_ESM2 = 1, 246 ESM2_DEV_DRACII, 247 ESM2_DEV_FRONT_PANEL, 248 ESM2_DEV_BACKPLANE2, 249 ESM2_DEV_POWERUNIT2, 250 ESM2_DEV_ENCL2_BACKPLANE, 251 ESM2_DEV_ENCL2_POWERUNIT, 252 ESM2_DEV_ENCL1_BACKPLANE, 253 ESM2_DEV_ENCL1_POWERUNIT, 254 ESM2_DEV_HPPCI, 255 ESM2_DEV_BACKPLANE3 256 }; 257 258 enum esm_dev_esm2_type { 259 ESM2_DEV_ESM2_2300 = 0, 260 ESM2_DEV_ESM2_4300, 261 ESM2_DEV_ESM2_6300, 262 ESM2_DEV_ESM2_6400, 263 ESM2_DEV_ESM2_2550, 264 ESM2_DEV_ESM2_4350, 265 ESM2_DEV_ESM2_6350, 266 ESM2_DEV_ESM2_6450, 267 ESM2_DEV_ESM2_2400, 268 ESM2_DEV_ESM2_4400, 269 ESM2_DEV_ESM2_R0, /* reserved */ 270 ESM2_DEV_ESM2_2500, 271 ESM2_DEV_ESM2_2450, 272 ESM2_DEV_ESM2_R1, /* reserved */ 273 ESM2_DEV_ESM2_R2, /* reserved */ 274 ESM2_DEV_ESM2_2400EX, 275 ESM2_DEV_ESM2_2450EX 276 }; 277 278