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Searched refs:EltSize (Results 1 – 25 of 63) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/DirectX/
H A DCBufferDataLayout.cpp81 TypeSize EltSize = getTypeAllocSize(AT->getElementType()); in getTypeAllocSize() local
82 TypeSize AlignedEltSize = alignTo4Dwords(EltSize); in getTypeAllocSize()
84 return TypeSize::getFixed(AlignedEltSize * (NumElts - 1) + EltSize); in getTypeAllocSize()
102 TypeSize EltSize = getTypeAllocSize(EltTy); in getStructLayout() local
107 Offset = Offset.getWithIncrement(EltSize); in getStructLayout()
/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp399 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeEXTRQIMask() argument
409 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeEXTRQIMask()
423 Len /= EltSize; in DecodeEXTRQIMask()
424 Idx /= EltSize; in DecodeEXTRQIMask()
436 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeINSERTQIMask() argument
446 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeINSERTQIMask()
460 Len /= EltSize; in DecodeINSERTQIMask()
461 Idx /= EltSize; in DecodeINSERTQIMask()
H A DX86ShuffleDecode.h140 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
144 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
/openbsd/gnu/llvm/clang/lib/CodeGen/
H A DCGBuilder.h217 CharUnits EltSize = variable
224 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
236 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy)); variable
241 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
252 CharUnits EltSize = variable
258 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
267 CharUnits EltSize = variable
273 Addr.getAlignment().alignmentOfArrayElement(EltSize));
H A DCGNonTrivialStruct.cpp196 CharUnits EltSize = Ctx.getTypeSizeInChars(EltTy); in visitArray() local
198 llvm::to_string(EltSize.getQuantity()) + "n" + in visitArray()
398 CharUnits EltSize = Ctx.getTypeSizeInChars(EltQT); in visitArray() local
404 StartAddrs[I].getAlignment().alignmentAtOffset(EltSize)); in visitArray()
415 NewAddrs[I] = getAddrWithOffset(NewAddrs[I], EltSize); in visitArray()
H A DCGDecl.cpp1756 CharUnits EltSize = getContext().getTypeSizeInChars(VlaSize.Type); in emitZeroOrPatternForAutoVarInit() local
1764 if (!EltSize.isOne()) in emitZeroOrPatternForAutoVarInit()
1765 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); in emitZeroOrPatternForAutoVarInit()
1787 if (!EltSize.isOne()) in emitZeroOrPatternForAutoVarInit()
1788 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); in emitZeroOrPatternForAutoVarInit()
1790 llvm::ConstantInt::get(IntPtrTy, EltSize.getQuantity()); in emitZeroOrPatternForAutoVarInit()
1798 CharUnits CurAlign = Loc.getAlignment().alignmentOfArrayElement(EltSize); in emitZeroOrPatternForAutoVarInit()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp110 unsigned EltSize; member
226 unsigned read2Opcode(unsigned EltSize) const;
232 unsigned write2Opcode(unsigned EltSize) const;
718 EltSize = in setMI()
723 EltSize = in setMI()
733 EltSize = 4; in setMI()
944 if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0)) in offsetsCanBeCombined()
1018 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
1032 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
1167 CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize); in mergeRead2Pair()
[all …]
H A DR600TargetTransformInfo.cpp117 unsigned EltSize = in getVectorInstrCost() local
119 if (EltSize < 32) { in getVectorInstrCost()
H A DSIRegisterInfo.cpp99 unsigned EltSize = 4; member
1277 switch (EltSize) { in getFlatScratchSpillOpcode()
1335 unsigned Size = NumSubRegs * EltSize; in buildSpillLoadStore()
1344 if (IsFlat && EltSize > 4) { in buildSpillLoadStore()
1495 ++i, RegOffset += EltSize) { in buildSpillLoadStore()
1497 EltSize = RemSize; in buildSpillLoadStore()
1518 unsigned NumRegs = EltSize / 4; in buildSpillLoadStore()
1541 unsigned RemEltSize = EltSize; in buildSpillLoadStore()
1579 assert(IsFlat && EltSize > 4); in buildSpillLoadStore()
1591 assert(EltSize == 4); in buildSpillLoadStore()
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H A DAMDGPULegalizerInfo.cpp75 EltSize > 1 && EltSize < 32 && in isSmallOddVector()
127 assert(EltSize < 32); in moreEltsToNext32Bit()
129 const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize; in moreEltsToNext32Bit()
189 const int EltSize = EltTy.getSizeInBits(); in isRegisterVectorElementType() local
190 return EltSize == 16 || EltSize % 32 == 0; in isRegisterVectorElementType()
195 return EltSize == 32 || EltSize == 64 || in isRegisterVectorType()
197 EltSize == 128 || EltSize == 256; in isRegisterVectorType()
350 unsigned EltSize = EltTy.getSizeInBits(); in loadStoreBitcastWorkaround() local
351 return EltSize != 32 && EltSize != 64; in loadStoreBitcastWorkaround()
1453 return (EltSize == 32 || EltSize == 64) && in AMDGPULegalizerInfo()
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H A DAMDGPUTargetTransformInfo.cpp799 unsigned EltSize in getVectorInstrCost() local
801 if (EltSize < 32) { in getVectorInstrCost()
802 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp70 static bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts, in isREVMask() argument
74 assert(EltSize != 64 && "EltSize cannot be 64 for REV mask."); in isREVMask()
80 BlockElts = BlockSize / EltSize; in isREVMask()
82 if (BlockSize <= EltSize || BlockSize != BlockElts * EltSize) in isREVMask()
229 unsigned EltSize = Ty.getScalarSizeInBits(); in matchREV() local
232 if (EltSize == 64) in matchREV()
238 if (isREVMask(ShuffleMask, EltSize, NumElts, 64)) { in matchREV()
965 unsigned EltSize = MRI.getType(LHS).getScalarSizeInBits(); in lowerVectorFCMP() local
966 if (EltSize != 32 && EltSize != 64) in lowerVectorFCMP()
H A DAArch64InstructionSelector.cpp2538 if (EltSize == 32) in select()
2541 else if (EltSize == 64) in select()
3996 switch (EltSize) { in emitScalarToVector()
4081 switch (EltSize) { in getLaneCopyOpcode()
4437 if (EltSize == 16) { in getInsertVecEltOpInfo()
4440 } else if (EltSize == 32) { in getInsertVecEltOpInfo()
4443 } else if (EltSize == 64) { in getInsertVecEltOpInfo()
4450 if (EltSize == 8) { in getInsertVecEltOpInfo()
4453 } else if (EltSize == 16) { in getInsertVecEltOpInfo()
5361 if (EltSize < 16 || EltSize > 64) in selectInsertElt()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h311 unsigned EltSize = DataTypeTy->getElementType()->getScalarSizeInBits(); in isLegalNTStoreLoad() local
312 return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 && in isLegalNTStoreLoad()
313 EltSize <= 128 && isPowerOf2_64(EltSize); in isLegalNTStoreLoad()
H A DAArch64RegisterInfo.td941 let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
958 let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
1601 class MatrixTileAsmOperand<string RC, int EltSize> : AsmOperandClass {
1602 let Name = "MatrixTile" # EltSize;
1626 class MatrixTileVectorAsmOperand<string RC, int EltSize, int IsVertical>
1628 let Name = "MatrixTileVector" # !if(IsVertical, "V", "H") # EltSize;
1638 class MatrixTileVectorOperand<int EltSize, int NumBitsForTile,
1663 class MatrixAsmOperand<string RC, int EltSize> : AsmOperandClass {
1664 let Name = "Matrix" # !if(EltSize, !cast<string>(EltSize), "");
1674 let ParserMatchClass = MatrixAsmOperand<!cast<string>(RC), EltSize>;
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H A DAArch64StackTagging.cpp280 uint32_t EltSize = DL->getTypeSizeInBits(EltTy); in flatten() local
282 IntegerType::get(Ctx, EltSize), in flatten()
/openbsd/gnu/llvm/llvm/lib/Analysis/
H A DLoads.cpp269 APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()), in isDereferenceableAndAlignedInLoop() local
278 return isDereferenceableAndAlignedPointer(Ptr, Alignment, EltSize, DL, in isDereferenceableAndAlignedInLoop()
290 if (Step->getAPInt() != EltSize) in isDereferenceableAndAlignedInLoop()
297 const APInt AccessSize = TC * EltSize; in isDereferenceableAndAlignedInLoop()
308 if (EltSize.urem(Alignment.value()) != 0) in isDereferenceableAndAlignedInLoop()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h831 unsigned NumElts, unsigned EltSize) { in isSequenceFromUnmerge() argument
836 MI.getSourceReg(i), EltSize, EltUnmergeIdx); in isSequenceFromUnmerge()
853 unsigned EltSize = EltTy.getSizeInBits(); in tryCombineMergeLike() local
857 auto *Unmerge = findUnmergeThatDefinesReg(Elt0, EltSize, Elt0UnmergeIdx); in tryCombineMergeLike()
875 if (!isSequenceFromUnmerge(MI, 0, Unmerge, 0, NumMIElts, EltSize)) in tryCombineMergeLike()
896 EltSize)) in tryCombineMergeLike()
900 unsigned DstIdx = (Elt0UnmergeIdx * EltSize) / DstTy.getSizeInBits(); in tryCombineMergeLike()
924 EltSize, EltUnmergeIdx); in tryCombineMergeLike()
929 if (!isSequenceFromUnmerge(MI, i, UnmergeI, 0, NumElts, EltSize)) in tryCombineMergeLike()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4288 unsigned EltSize = MemIntr->getMemoryVT().getSizeInBits(); in matchVPTERNLOG() local
4289 assert((EltSize == 32 || EltSize == 64) && "Unexpected broadcast size!"); in matchVPTERNLOG()
4291 bool UseD = EltSize == 32; in matchVPTERNLOG()
5958 unsigned EltSize = ValueSVT.getSizeInBits(); in Select() local
5963 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
5990 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
6054 unsigned EltSize = ValueSVT.getSizeInBits(); in Select() local
6057 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
6059 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 32) in Select()
6063 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) in Select()
[all …]
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DAnalysis.cpp104 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue(); in ComputeValueVTs() local
107 StartingOffset + i * EltSize); in ComputeValueVTs()
149 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue(); in computeValueLLTs() local
152 StartingOffset + i * EltSize); in computeValueLLTs()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h191 template <int EltSize>
218 template <int EltSize>
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1577 unsigned EltSize = VTy->getScalarSizeInBits(); in getGatherScatterOpCost() local
1596 if (EltSize < 8 || Alignment < EltSize / 8) in getGatherScatterOpCost()
1599 unsigned ExtSize = EltSize; in getGatherScatterOpCost()
1613 if (((TypeSize == 32 && (EltSize == 8 || EltSize == 16)) || in getGatherScatterOpCost()
1614 (TypeSize == 16 && EltSize == 8)) && in getGatherScatterOpCost()
1627 if (((EltSize == 16 && TypeSize == 32) || in getGatherScatterOpCost()
1628 (EltSize == 8 && (TypeSize == 32 || TypeSize == 16))) && in getGatherScatterOpCost()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp710 unsigned EltSize = Val->getScalarSizeInBits(); in getVectorInstrCost() local
711 if (EltSize == 64) { in getVectorInstrCost()
715 } else if (EltSize == 32) { in getVectorInstrCost()
/openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineLoadStoreAlloca.cpp788 auto EltSize = DL.getTypeAllocSize(ET); in unpackLoadToAggregate() local
809 Offset += EltSize; in unpackLoadToAggregate()
1310 auto EltSize = DL.getTypeAllocSize(AT->getElementType()); in unpackStoreToAggregate() local
1334 Offset += EltSize; in unpackStoreToAggregate()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h582 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, in computeVLMAX() argument
589 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock; in computeVLMAX()

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