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Searched refs:FABS (Results 1 – 25 of 40) sorted by relevance

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/openbsd/gnu/usr.bin/gcc/contrib/
H A Dparanoia.cc724 FABS (const FLOAT &f) in FABS() function
793 diff2 = FABS (z * z - f); in SQRT()
798 diff = FABS (t * t - f); in SQRT()
1118 while (MinusOne + FABS (Y) < Zero); in main()
1160 X = FABS (X - Third); in main()
1179 X = FABS (X + F6); in main()
1235 if (FABS (X - Y) * Four < One) in main()
1378 Y = FABS ((X + Z) - X * X) - U2; in main()
1380 Z = FABS ((X - U2) - X * X) - U1; in main()
1903 E1 = FABS (Y1 - Y2); in main()
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h911 FABS, enumerator
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp447 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering()
539 ISD::FABS, ISD::AssertZext, in AMDGPUTargetLowering()
1765 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1768 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2247 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2289 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2668 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
3684 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) || in foldFreeOpFromSelect()
3691 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3712 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL) in foldFreeOpFromSelect()
[all …]
H A DR600Instructions.td681 class FABS <RegisterClass rc> : AMDGPUShaderInst <
684 "FABS $dst, $src0",
1207 def FABS_R600 : FABS<R600_Reg32>;
H A DAMDGPUISelDAGToDAG.cpp149 case ISD::FABS: in fp16SrcZerosHighBits()
2603 if (AllowAbs && Src.getOpcode() == ISD::FABS) { in SelectVOP3ModsImpl()
2634 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
H A DSIISelLowering.cpp640 setOperationAction(ISD::FABS, MVT::v2f16, Legal); in SITargetLowering()
705 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom); in SITargetLowering()
716 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v2f16, Custom); in SITargetLowering()
4752 case ISD::FABS: in LowerOperation()
5131 case ISD::FABS: { in ReplaceNodeResults()
9024 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in lowerFDIV_FAST()
9720 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X || in performAndCombine()
10136 case ISD::FABS: in isCanonicalized()
10801 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) { in performExtractVectorEltCombine()
11493 if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) { in performSetCCCombine()
/openbsd/gnu/gcc/gcc/
H A Dlibgcc2.c1778 #define FABS CONCAT2(__builtin_fabs, CEXT) macro
1869 if (FABS (c) < FABS (d))
H A Dconvert.c159 CASE_MATHFN (FABS) in convert_to_real()
/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1761 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1868 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1871 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1890 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2876 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3020 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3238 case ISD::FABS: in LowerOperation()
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp71 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
1216 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1337 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
2257 case ISD::FABS: in PromoteFloatResult()
2622 case ISD::FABS: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp187 case ISD::FABS: return "fabs"; in getOperationName()
H A DDAGCombiner.cpp1786 case ISD::FABS: return visitFABS(N); in visit()
14138 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
14146 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
14272 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
14290 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15607 TLI.isOperationLegal(ISD::FABS, VT)) { in visitFMUL()
15642 return DAG.getNode(ISD::FABS, DL, VT, X); in visitFMUL()
16103 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
16104 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); in visitFCOPYSIGN()
16635 if (N0.getOpcode() == ISD::FABS) in visitFABS()
[all …]
H A DLegalizeDAG.cpp1613 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) && in ExpandFCOPYSIGN()
1615 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag); in ExpandFCOPYSIGN()
3191 case ISD::FABS: in ExpandNode()
4884 case ISD::FABS: in PromoteNode()
H A DLegalizeVectorOps.cpp360 case ISD::FABS: in LegalizeOp()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
H A DAArch64SchedCyclone.td436 // FABS,FNEG are WriteF
H A DAArch64SchedExynosM3.td537 def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>;
H A DAArch64SchedExynosM4.td635 def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>;
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td123 defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
H A DMipsISelLowering.cpp345 setOperationAction(ISD::FABS, MVT::f32, Custom); in MipsTargetLowering()
346 setOperationAction(ISD::FABS, MVT::f64, Custom); in MipsTargetLowering()
1229 case ISD::FABS: return lowerFABS(Op, DAG); in LowerOperation()
H A DMipsInstrFPU.td531 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
H A DMipsSEISelLowering.cpp136 setOperationAction(ISD::FABS, MVT::f16, Promote); in MipsSETargetLowering()
380 setOperationAction(ISD::FABS, Ty, Legal); in addMSAFloatType()
/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td119 defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;
/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp617 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FABS}) { in NVPTXTargetLowering()
2222 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND32()
2263 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND64()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp345 ISD::FDIV, ISD::FSQRT, ISD::FABS, in RISCVTargetLowering()
953 ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT, in RISCVTargetLowering()
4213 case ISD::FABS: in LowerOperation()
10133 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
10147 assert(Op0.getOpcode() == ISD::FABS); in PerformDAGCombine()
10192 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
10202 assert(Op0.getOpcode() == ISD::FABS); in PerformDAGCombine()

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