1 /* $OpenBSD: pyro.c,v 1.38 2024/03/29 21:29:33 miod Exp $ */
2
3 /*
4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2003 Henric Jungheim
6 * Copyright (c) 2007 Mark Kettenis
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <sys/param.h>
32 #include <sys/device.h>
33 #include <sys/errno.h>
34 #include <sys/malloc.h>
35 #include <sys/systm.h>
36
37 #define _SPARC_BUS_DMA_PRIVATE
38 #include <machine/bus.h>
39 #include <machine/autoconf.h>
40 #include <machine/openfirm.h>
41
42 #ifdef DDB
43 #include <machine/db_machdep.h>
44 #endif
45
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48
49 #include <sparc64/dev/iommureg.h>
50 #include <sparc64/dev/iommuvar.h>
51 #include <sparc64/dev/msivar.h>
52 #include <sparc64/dev/pyrovar.h>
53
54 #ifdef DEBUG
55 #define PDB_PROM 0x01
56 #define PDB_BUSMAP 0x02
57 #define PDB_INTR 0x04
58 #define PDB_CONF 0x08
59 int pyro_debug = ~0;
60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0)
61 #else
62 #define DPRINTF(l, s)
63 #endif
64
65 #define FIRE_INTR_MAP(_n) 0x01000 + ((_n) * 8)
66 #define FIRE_INTR_CLR(_n) 0x01400 + ((_n) * 8)
67
68 #define FIRE_EQ_BASE_ADDR 0x10000
69 #define FIRE_EQ_CNTRL_SET(_n) 0x11000 + ((_n) * 8)
70 #define FIRE_EQ_CTRL_SET_EN 0x0000100000000000UL
71 #define FIRE_EQ_CNTRL_CLEAR(_n) 0x11200 + ((_n) * 8)
72 #define FIRE_EQ_STATE(_n) 0x11400 + ((_n) * 8)
73 #define FIRE_EQ_TAIL(_n) 0x11600 + ((_n) * 8)
74 #define FIRE_EQ_HEAD(_n) 0x11800 + ((_n) * 8)
75 #define FIRE_MSI_MAP(_n) 0x20000 + ((_n) * 8)
76 #define FIRE_MSI_MAP_V 0x8000000000000000UL
77 #define FIRE_MSI_MAP_EQWR_N 0x4000000000000000UL
78 #define FIRE_MSI_MAP_EQNUM 0x000000000000003fUL
79 #define FIRE_MSI_CLEAR(_n) 0x28000 + ((_n) * 8)
80 #define FIRE_MSI_CLEAR_EQWR_N 0x4000000000000000UL
81 #define FIRE_INTRMONDO_DATA0 0x2c000
82 #define FIRE_INTRMONDO_DATA1 0x2c008
83 #define FIRE_MSI32_ADDR 0x34000
84 #define FIRE_MSI64_ADDR 0x34008
85
86 #define FIRE_RESET_GEN 0x7010
87
88 #define FIRE_RESET_GEN_XIR 0x0000000000000002UL
89
90 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0
91 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040
92 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080
93 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100
94 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200
95 #define FIRE_INTRMAP_T_JPID_SHIFT 26
96 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000
97
98 #define OBERON_INTRMAP_T_DESTID_SHIFT 21
99 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000
100
101 extern struct sparc_pci_chipset _sparc_pci_chipset;
102
103 int pyro_match(struct device *, void *, void *);
104 void pyro_attach(struct device *, struct device *, void *);
105 void pyro_init(struct pyro_softc *, int);
106 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *);
107 void pyro_init_msi(struct pyro_softc *, struct pyro_pbm *);
108 int pyro_print(void *, const char *);
109
110 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int,
111 pci_chipset_tag_t);
112 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *);
113 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *);
114 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *);
115 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *,
116 int, int, int);
117 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *);
118
119 int pyro_conf_size(pci_chipset_tag_t, pcitag_t);
120 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int);
121 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
122
123 int pyro_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
124 int pyro_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t,
125 bus_size_t, int, bus_space_handle_t *);
126 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t,
127 int, int);
128 void *pyro_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int,
129 int (*)(void *), void *, const char *);
130 void *pyro_intr_establish_cpu(bus_space_tag_t, bus_space_tag_t, int, int, int,
131 struct cpu_info *, int (*)(void *), void *, const char *);
132 void pyro_msi_ack(struct intrhand *);
133
134 int pyro_msi_eq_intr(void *);
135
136 int pyro_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int,
137 bus_size_t, bus_size_t, int, bus_dmamap_t *);
138
139 void pyro_iommu_enable(struct iommu_state *);
140
141 const struct iommu_hw iommu_hw_fire = {
142 .ihw_enable = pyro_iommu_enable,
143
144 .ihw_dvma_pa = 0x000007ffffffffffUL,
145
146 .ihw_bypass = 0xfffc000000000000UL,
147 .ihw_bypass_nc = 0x0000080000000000UL,
148 .ihw_bypass_ro = 0,
149 };
150
151 const struct iommu_hw iommu_hw_oberon = {
152 .ihw_enable = pyro_iommu_enable,
153
154 .ihw_dvma_pa = 0x00007fffffffffffUL,
155
156 .ihw_bypass = 0x7ffc000000000000UL,
157 .ihw_bypass_nc = 0x0000800000000000UL,
158 .ihw_bypass_ro = 0x8000000000000000UL,
159
160 .ihw_flags = IOMMU_HW_FLUSH_CACHE,
161 };
162
163 #ifdef DDB
164 void pyro_xir(void *, int);
165 #endif
166
167 int
pyro_match(struct device * parent,void * match,void * aux)168 pyro_match(struct device *parent, void *match, void *aux)
169 {
170 struct mainbus_attach_args *ma = aux;
171 char *str;
172
173 if (strcmp(ma->ma_name, "pci") != 0)
174 return (0);
175
176 str = getpropstring(ma->ma_node, "compatible");
177 if (strcmp(str, "pciex108e,80f0") == 0 ||
178 strcmp(str, "pciex108e,80f8") == 0)
179 return (1);
180
181 return (0);
182 }
183
184 void
pyro_attach(struct device * parent,struct device * self,void * aux)185 pyro_attach(struct device *parent, struct device *self, void *aux)
186 {
187 struct pyro_softc *sc = (struct pyro_softc *)self;
188 struct mainbus_attach_args *ma = aux;
189 char *str;
190 int busa;
191
192 sc->sc_node = ma->ma_node;
193 sc->sc_dmat = ma->ma_dmatag;
194 sc->sc_bust = ma->ma_bustag;
195 sc->sc_csr = ma->ma_reg[0].ur_paddr;
196 sc->sc_xbc = ma->ma_reg[1].ur_paddr;
197 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
198
199 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
200 busa = 1;
201 else
202 busa = 0;
203
204 if (bus_space_map(sc->sc_bust, sc->sc_csr,
205 ma->ma_reg[0].ur_len, 0, &sc->sc_csrh)) {
206 printf(": failed to map csr registers\n");
207 return;
208 }
209
210 if (bus_space_map(sc->sc_bust, sc->sc_xbc,
211 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) {
212 printf(": failed to map xbc registers\n");
213 return;
214 }
215
216 str = getpropstring(ma->ma_node, "compatible");
217 if (strcmp(str, "pciex108e,80f8") == 0)
218 sc->sc_oberon = 1;
219
220 pyro_init(sc, busa);
221 }
222
223 void
pyro_init(struct pyro_softc * sc,int busa)224 pyro_init(struct pyro_softc *sc, int busa)
225 {
226 struct pyro_pbm *pbm;
227 struct pcibus_attach_args pba;
228 int *busranges = NULL, nranges;
229
230 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO);
231 if (pbm == NULL)
232 panic("pyro: can't alloc pyro pbm");
233
234 pbm->pp_sc = sc;
235 pbm->pp_bus_a = busa;
236
237 if (getprop(sc->sc_node, "ranges", sizeof(struct pyro_range),
238 &pbm->pp_nrange, (void **)&pbm->pp_range))
239 panic("pyro: can't get ranges");
240
241 if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
242 (void **)&busranges))
243 panic("pyro: can't get bus-range");
244
245 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n",
246 sc->sc_oberon ? "Oberon" : "Fire",
247 getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign,
248 busa ? 'A' : 'B', busranges[0], busranges[1]);
249
250 printf("%s: ", sc->sc_dv.dv_xname);
251 pyro_init_iommu(sc, pbm);
252
253 pbm->pp_memt = pyro_alloc_mem_tag(pbm);
254 pbm->pp_iot = pyro_alloc_io_tag(pbm);
255 pbm->pp_cfgt = pyro_alloc_config_tag(pbm);
256 pbm->pp_dmat = pyro_alloc_dma_tag(pbm);
257
258 pyro_init_msi(sc, pbm);
259
260 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh))
261 panic("pyro: can't map config space");
262
263 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset);
264
265 pbm->pp_pc->bustag = pbm->pp_cfgt;
266 pbm->pp_pc->bushandle = pbm->pp_cfgh;
267
268 bzero(&pba, sizeof(pba));
269 pba.pba_busname = "pci";
270 pba.pba_domain = pci_ndomains++;
271 pba.pba_bus = busranges[0];
272 pba.pba_pc = pbm->pp_pc;
273 pba.pba_flags = pbm->pp_flags;
274 pba.pba_dmat = pbm->pp_dmat;
275 pba.pba_memt = pbm->pp_memt;
276 pba.pba_iot = pbm->pp_iot;
277 pba.pba_pc->conf_size = pyro_conf_size;
278 pba.pba_pc->conf_read = pyro_conf_read;
279 pba.pba_pc->conf_write = pyro_conf_write;
280 pba.pba_pc->intr_map = pyro_intr_map;
281
282 free(busranges, M_DEVBUF, 0);
283
284 #ifdef DDB
285 db_register_xir(pyro_xir, sc);
286 #endif
287
288 config_found(&sc->sc_dv, &pba, pyro_print);
289 }
290
291 void
pyro_init_iommu(struct pyro_softc * sc,struct pyro_pbm * pbm)292 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm)
293 {
294 struct iommu_state *is = &pbm->pp_is;
295 int tsbsize = 7;
296 u_int32_t iobase = -1;
297 char *name;
298 const struct iommu_hw *ihw = &iommu_hw_fire;
299
300 is->is_bustag = sc->sc_bust;
301
302 if (bus_space_subregion(is->is_bustag, sc->sc_csrh,
303 0x40000, 0x100, &is->is_iommu)) {
304 panic("pyro: unable to create iommu handle");
305 }
306
307 is->is_sb[0] = &pbm->pp_sb;
308 is->is_sb[0]->sb_bustag = is->is_bustag;
309
310 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
311 if (name == NULL)
312 panic("couldn't malloc iommu name");
313 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname);
314
315 if (sc->sc_oberon)
316 ihw = &iommu_hw_oberon;
317
318 iommu_init(name, ihw, is, tsbsize, iobase);
319 }
320
321 void
pyro_iommu_enable(struct iommu_state * is)322 pyro_iommu_enable(struct iommu_state *is)
323 {
324 unsigned long cr;
325
326 cr = IOMMUREG_READ(is, iommu_cr);
327 cr |= IOMMUCR_FIRE_BE | IOMMUCR_FIRE_SE | IOMMUCR_FIRE_CM_EN |
328 IOMMUCR_FIRE_TE;
329
330 IOMMUREG_WRITE(is, iommu_tsb, is->is_ptsb | is->is_tsbsize);
331 IOMMUREG_WRITE(is, iommu_cr, cr);
332 }
333
334 void
pyro_init_msi(struct pyro_softc * sc,struct pyro_pbm * pbm)335 pyro_init_msi(struct pyro_softc *sc, struct pyro_pbm *pbm)
336 {
337 u_int32_t msi_addr_range[3];
338 u_int32_t msi_eq_devino[3] = { 0, 36, 24 };
339 int ihandle;
340 int msis, msi_eq_size, num_eq;
341 struct pyro_eq *eq;
342 struct msi_eq *meq;
343 struct pyro_msi_msg *msgs;
344 struct cpu_info *ci;
345 CPU_INFO_ITERATOR cii;
346
347 /* One queue per cpu. */
348 num_eq = ncpus;
349
350 if (OF_getprop(sc->sc_node, "msi-address-ranges",
351 msi_addr_range, sizeof(msi_addr_range)) <= 0)
352 return;
353 pbm->pp_msiaddr = msi_addr_range[1];
354 pbm->pp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32;
355
356 msis = getpropint(sc->sc_node, "#msi", 256);
357 pbm->pp_msi = mallocarray(msis, sizeof(*pbm->pp_msi), M_DEVBUF,
358 M_NOWAIT | M_ZERO);
359 if (pbm->pp_msi == NULL)
360 return;
361
362 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256);
363 pbm->pp_meq = msi_eq_alloc(pbm->pp_dmat, msi_eq_size, num_eq);
364 if (pbm->pp_meq == NULL)
365 goto free_table;
366
367 bzero(pbm->pp_meq->meq_va,
368 pbm->pp_meq->meq_nentries * sizeof(struct pyro_msi_msg) *
369 num_eq);
370
371 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_BASE_ADDR,
372 pbm->pp_meq->meq_map->dm_segs[0].ds_addr);
373
374 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
375 FIRE_INTRMONDO_DATA0, sc->sc_ign);
376 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
377 FIRE_INTRMONDO_DATA1, 0);
378
379 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_MSI32_ADDR,
380 pbm->pp_msiaddr);
381
382 if (OF_getprop(sc->sc_node, "msi-eq-to-devino",
383 msi_eq_devino, sizeof(msi_eq_devino)) == -1) {
384 OF_getprop(sc->sc_node, "msi-eq-devino",
385 msi_eq_devino, sizeof(msi_eq_devino));
386 }
387
388 pbm->pp_eq = mallocarray(num_eq, sizeof(*eq), M_DEVBUF, M_WAITOK);
389 pbm->pp_neq = num_eq;
390
391 meq = pbm->pp_meq;
392 msgs = (struct pyro_msi_msg *)meq->meq_va;
393
394 CPU_INFO_FOREACH(cii, ci) {
395 int unit = CPU_INFO_UNIT(ci);
396 eq = &pbm->pp_eq[unit];
397
398 eq->eq_id = unit;
399 eq->eq_intr = msi_eq_devino[2] + unit;
400 eq->eq_pbm = pbm;
401 snprintf(eq->eq_name, sizeof(eq->eq_name), "%s:%d",
402 sc->sc_dv.dv_xname, unit);
403 eq->eq_head = FIRE_EQ_HEAD(unit);
404 eq->eq_tail = FIRE_EQ_TAIL(unit);
405 eq->eq_ring = msgs + (unit * meq->meq_nentries);
406 eq->eq_mask = (meq->meq_nentries - 1);
407
408 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
409 FIRE_EQ_HEAD(unit), 0);
410 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
411 FIRE_EQ_TAIL(unit), 0);
412
413 ihandle = eq->eq_intr | sc->sc_ign;
414 eq->eq_ih = pyro_intr_establish_cpu(pbm->pp_memt, sc->sc_bust,
415 ihandle, IPL_HIGH, BUS_INTR_ESTABLISH_MPSAFE, ci,
416 pyro_msi_eq_intr, eq, eq->eq_name);
417 if (eq->eq_ih == NULL) {
418 /* XXX */
419 goto free_table;
420 }
421
422 /* Enable EQ. */
423 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
424 FIRE_EQ_CNTRL_SET(unit), FIRE_EQ_CTRL_SET_EN);
425 }
426
427 pbm->pp_flags |= PCI_FLAGS_MSI_ENABLED;
428
429 return;
430
431 free_table:
432 free(pbm->pp_msi, M_DEVBUF, 0);
433 }
434
435 int
pyro_print(void * aux,const char * p)436 pyro_print(void *aux, const char *p)
437 {
438 if (p == NULL)
439 return (UNCONF);
440 return (QUIET);
441 }
442
443 int
pyro_conf_size(pci_chipset_tag_t pc,pcitag_t tag)444 pyro_conf_size(pci_chipset_tag_t pc, pcitag_t tag)
445 {
446 return PCIE_CONFIG_SPACE_SIZE;
447 }
448
449 pcireg_t
pyro_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)450 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
451 {
452 struct cpu_info *ci = curcpu();
453 pcireg_t val;
454 int s;
455
456 s = splhigh();
457 __membar("#Sync");
458 ci->ci_pci_probe = 1;
459 val = bus_space_read_4(pc->bustag, pc->bushandle,
460 (PCITAG_OFFSET(tag) << 4) + reg);
461 __membar("#Sync");
462 if (ci->ci_pci_fault)
463 val = 0xffffffff;
464 ci->ci_pci_probe = ci->ci_pci_fault = 0;
465 splx(s);
466
467 return (val);
468 }
469
470 void
pyro_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)471 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
472 {
473 bus_space_write_4(pc->bustag, pc->bushandle,
474 (PCITAG_OFFSET(tag) << 4) + reg, data);
475 }
476
477 /*
478 * Bus-specific interrupt mapping
479 */
480 int
pyro_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)481 pyro_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
482 {
483 struct pyro_pbm *pp = pa->pa_pc->cookie;
484 struct pyro_softc *sc = pp->pp_sc;
485 u_int dev;
486
487 if (*ihp != (pci_intr_handle_t)-1) {
488 *ihp |= sc->sc_ign;
489 return (0);
490 }
491
492 /*
493 * We didn't find a PROM mapping for this interrupt. Try to
494 * construct one ourselves based on the swizzled interrupt pin
495 * and the interrupt mapping for PCI slots documented in the
496 * UltraSPARC-IIi User's Manual.
497 */
498
499 if (pa->pa_intrpin == 0)
500 return (-1);
501
502 /*
503 * This deserves some documentation. Should anyone
504 * have anything official looking, please speak up.
505 */
506 dev = pa->pa_device - 1;
507
508 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT;
509 *ihp |= (dev << 2) & INTMAP_PCISLOT;
510 *ihp |= sc->sc_ign;
511
512 return (0);
513 }
514
515 bus_space_tag_t
pyro_alloc_mem_tag(struct pyro_pbm * pp)516 pyro_alloc_mem_tag(struct pyro_pbm *pp)
517 {
518 return (pyro_alloc_bus_tag(pp, "mem",
519 0x02, /* 32-bit mem space (where's the #define???) */
520 ASI_PRIMARY, ASI_PRIMARY_LITTLE));
521 }
522
523 bus_space_tag_t
pyro_alloc_io_tag(struct pyro_pbm * pp)524 pyro_alloc_io_tag(struct pyro_pbm *pp)
525 {
526 return (pyro_alloc_bus_tag(pp, "io",
527 0x01, /* IO space (where's the #define???) */
528 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED));
529 }
530
531 bus_space_tag_t
pyro_alloc_config_tag(struct pyro_pbm * pp)532 pyro_alloc_config_tag(struct pyro_pbm *pp)
533 {
534 return (pyro_alloc_bus_tag(pp, "cfg",
535 0x00, /* Config space (where's the #define???) */
536 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED));
537 }
538
539 bus_space_tag_t
pyro_alloc_bus_tag(struct pyro_pbm * pbm,const char * name,int ss,int asi,int sasi)540 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int ss,
541 int asi, int sasi)
542 {
543 struct pyro_softc *sc = pbm->pp_sc;
544 struct sparc_bus_space_tag *bt;
545
546 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO);
547 if (bt == NULL)
548 panic("pyro: could not allocate bus tag");
549
550 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)",
551 sc->sc_dv.dv_xname, name, ss, asi);
552
553 bt->cookie = pbm;
554 bt->parent = sc->sc_bust;
555 bt->default_type = ss;
556 bt->asi = asi;
557 bt->sasi = sasi;
558 bt->sparc_bus_map = pyro_bus_map;
559 bt->sparc_bus_mmap = pyro_bus_mmap;
560 bt->sparc_intr_establish = pyro_intr_establish;
561 bt->sparc_intr_establish_cpu = pyro_intr_establish_cpu;
562 return (bt);
563 }
564
565 bus_dma_tag_t
pyro_alloc_dma_tag(struct pyro_pbm * pbm)566 pyro_alloc_dma_tag(struct pyro_pbm *pbm)
567 {
568 struct pyro_softc *sc = pbm->pp_sc;
569 bus_dma_tag_t dt, pdt = sc->sc_dmat;
570
571 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO);
572 if (dt == NULL)
573 panic("pyro: could not alloc dma tag");
574
575 dt->_cookie = pbm;
576 dt->_parent = pdt;
577 dt->_dmamap_create = pyro_dmamap_create;
578 dt->_dmamap_destroy = iommu_dvmamap_destroy;
579 dt->_dmamap_load = iommu_dvmamap_load;
580 dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
581 dt->_dmamap_unload = iommu_dvmamap_unload;
582 dt->_dmamap_sync = iommu_dvmamap_sync;
583 dt->_dmamem_alloc = iommu_dvmamem_alloc;
584 dt->_dmamem_free = iommu_dvmamem_free;
585 return (dt);
586 }
587
588 pci_chipset_tag_t
pyro_alloc_chipset(struct pyro_pbm * pbm,int node,pci_chipset_tag_t pc)589 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc)
590 {
591 pci_chipset_tag_t npc;
592
593 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT);
594 if (npc == NULL)
595 panic("pyro: could not allocate pci_chipset_tag_t");
596 memcpy(npc, pc, sizeof *pc);
597 npc->cookie = pbm;
598 npc->rootnode = node;
599 return (npc);
600 }
601
602 int
pyro_dmamap_create(bus_dma_tag_t t,bus_dma_tag_t t0,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)603 pyro_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size,
604 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
605 bus_dmamap_t *dmamp)
606 {
607 struct pyro_pbm *pp = t->_cookie;
608
609 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments,
610 maxsegsz, boundary, flags, dmamp));
611 }
612
613 int
pyro_bus_map(bus_space_tag_t t,bus_space_tag_t t0,bus_addr_t offset,bus_size_t size,int flags,bus_space_handle_t * hp)614 pyro_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset,
615 bus_size_t size, int flags, bus_space_handle_t *hp)
616 {
617 struct pyro_pbm *pbm = t->cookie;
618 int i, ss;
619
620 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %llx sz %llx flags %d",
621 t->default_type,
622 (unsigned long long)offset,
623 (unsigned long long)size,
624 flags));
625
626 ss = t->default_type;
627 DPRINTF(PDB_BUSMAP, (" cspace %d", ss));
628
629 if (t->parent == 0 || t->parent->sparc_bus_map == 0) {
630 printf("\npyro_bus_map: invalid parent");
631 return (EINVAL);
632 }
633
634 if (flags & BUS_SPACE_MAP_PROMADDRESS) {
635 return ((*t->parent->sparc_bus_map)
636 (t, t0, offset, size, flags, hp));
637 }
638
639 for (i = 0; i < pbm->pp_nrange; i++) {
640 bus_addr_t paddr;
641
642 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss)
643 continue;
644
645 paddr = pbm->pp_range[i].phys_lo + offset;
646 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32;
647 return ((*t->parent->sparc_bus_map)
648 (t, t0, paddr, size, flags, hp));
649 }
650
651 return (EINVAL);
652 }
653
654 paddr_t
pyro_bus_mmap(bus_space_tag_t t,bus_space_tag_t t0,bus_addr_t paddr,off_t off,int prot,int flags)655 pyro_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr,
656 off_t off, int prot, int flags)
657 {
658 bus_addr_t offset = paddr;
659 struct pyro_pbm *pbm = t->cookie;
660 int i, ss;
661
662 ss = t->default_type;
663
664 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %llx\n",
665 prot, flags, (unsigned long long)paddr));
666
667 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) {
668 printf("\npyro_bus_mmap: invalid parent");
669 return (-1);
670 }
671
672 for (i = 0; i < pbm->pp_nrange; i++) {
673 bus_addr_t paddr;
674
675 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss)
676 continue;
677
678 paddr = pbm->pp_range[i].phys_lo + offset;
679 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32;
680 return ((*t->parent->sparc_bus_mmap)
681 (t, t0, paddr, off, prot, flags));
682 }
683
684 return (-1);
685 }
686
687 void *
pyro_intr_establish(bus_space_tag_t t,bus_space_tag_t t0,int ihandle,int level,int flags,int (* handler)(void *),void * arg,const char * what)688 pyro_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle,
689 int level, int flags, int (*handler)(void *), void *arg, const char *what)
690 {
691 return (pyro_intr_establish_cpu(t, t0, ihandle, level, flags, NULL,
692 handler, arg, what));
693 }
694
695 void *
pyro_intr_establish_cpu(bus_space_tag_t t,bus_space_tag_t t0,int ihandle,int level,int flags,struct cpu_info * ci,int (* handler)(void *),void * arg,const char * what)696 pyro_intr_establish_cpu(bus_space_tag_t t, bus_space_tag_t t0, int ihandle,
697 int level, int flags, struct cpu_info *ci,
698 int (*handler)(void *), void *arg, const char *what)
699 {
700 struct pyro_pbm *pbm = t->cookie;
701 struct pyro_softc *sc = pbm->pp_sc;
702 struct intrhand *ih = NULL;
703 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL;
704 int ino;
705
706 if (PCI_INTR_TYPE(ihandle) != PCI_INTR_INTX) {
707 pci_chipset_tag_t pc = pbm->pp_pc;
708 pcitag_t tag = PCI_INTR_TAG(ihandle);
709 int msinum = pbm->pp_msinum++;
710 u_int64_t reg;
711
712 ih = bus_intr_allocate(t0, handler, arg, ihandle, level,
713 NULL, NULL, what);
714 if (ih == NULL)
715 return (NULL);
716
717 evcount_attach(&ih->ih_count, ih->ih_name, NULL);
718
719 if (ci == NULL)
720 ci = cpus; /* Default to the boot cpu. */
721
722 ih->ih_cpu = ci;
723 ih->ih_ack = pyro_msi_ack;
724
725 pbm->pp_msi[msinum] = ih;
726 ih->ih_number = msinum;
727
728 if (flags & BUS_INTR_ESTABLISH_MPSAFE)
729 ih->ih_mpsafe = 1;
730
731 switch (PCI_INTR_TYPE(ihandle)) {
732 case PCI_INTR_MSI:
733 pci_msi_enable(pc, tag, pbm->pp_msiaddr, msinum);
734 break;
735 case PCI_INTR_MSIX:
736 pci_msix_enable(pc, tag, pbm->pp_memt,
737 PCI_INTR_VEC(ihandle), pbm->pp_msiaddr, msinum);
738 break;
739 }
740
741 /* Map MSI to the right EQ and mark it as valid. */
742 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh,
743 FIRE_MSI_MAP(msinum));
744 CLR(reg, FIRE_MSI_MAP_EQNUM);
745 SET(reg, CPU_INFO_UNIT(ci)); /* There's an eq per cpu. */
746 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
747 FIRE_MSI_MAP(msinum), reg);
748
749 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
750 FIRE_MSI_CLEAR(msinum), FIRE_MSI_CLEAR_EQWR_N);
751
752 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh,
753 FIRE_MSI_MAP(msinum));
754 SET(reg, FIRE_MSI_MAP_V);
755 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
756 FIRE_MSI_MAP(msinum), reg);
757
758 return (ih);
759 }
760
761 ino = INTINO(ihandle);
762
763 if (level == IPL_NONE)
764 level = INTLEV(ihandle);
765 if (level == IPL_NONE) {
766 printf(": no IPL, setting IPL 2.\n");
767 level = 2;
768 }
769
770 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) {
771 u_int64_t *imap, *iclr;
772
773 imap = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1000;
774 iclr = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1400;
775 intrmapptr = &imap[ino];
776 intrclrptr = &iclr[ino];
777 ino |= INTVEC(ihandle);
778 }
779
780 ih = bus_intr_allocate(t0, handler, arg, ino, level, NULL,
781 intrclrptr, what);
782 if (ih == NULL)
783 return (NULL);
784
785 ih->ih_cpu = ci;
786 if (flags & BUS_INTR_ESTABLISH_MPSAFE)
787 ih->ih_mpsafe = 1;
788
789 intr_establish(ih);
790
791 if (intrmapptr != NULL) {
792 u_int64_t intrmap;
793
794 ci = ih->ih_cpu;
795
796 intrmap = *intrmapptr;
797 intrmap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK;
798 intrmap |= FIRE_INTRMAP_INT_CNTRL_NUM0;
799 if (sc->sc_oberon) {
800 intrmap &= ~OBERON_INTRMAP_T_DESTID_MASK;
801 intrmap |= ci->ci_upaid <<
802 OBERON_INTRMAP_T_DESTID_SHIFT;
803 } else {
804 intrmap &= ~FIRE_INTRMAP_T_JPID_MASK;
805 intrmap |= ci->ci_upaid <<
806 FIRE_INTRMAP_T_JPID_SHIFT;
807 }
808 intrmap |= INTMAP_V;
809 membar_producer();
810 *intrmapptr = intrmap;
811 intrmap = *intrmapptr;
812 ih->ih_number |= intrmap & INTMAP_INR;
813 }
814
815 return (ih);
816 }
817
818 void
pyro_msi_ack(struct intrhand * ih)819 pyro_msi_ack(struct intrhand *ih)
820 {
821 }
822
823 int
pyro_msi_eq_intr(void * arg)824 pyro_msi_eq_intr(void *arg)
825 {
826 struct pyro_eq *eq = arg;
827 struct pyro_pbm *pbm = eq->eq_pbm;
828 struct pyro_softc *sc = pbm->pp_sc;
829 struct pyro_msi_msg *msg;
830 uint64_t head, tail;
831 struct intrhand *ih;
832 int msinum;
833
834 head = bus_space_read_8(sc->sc_bust, sc->sc_csrh, eq->eq_head);
835 tail = bus_space_read_8(sc->sc_bust, sc->sc_csrh, eq->eq_tail);
836
837 if (head == tail)
838 return (0);
839
840 do {
841 msg = &eq->eq_ring[head];
842 if (msg->mm_type == 0)
843 break;
844
845 msg->mm_type = 0;
846
847 msinum = msg->mm_data;
848 ih = pbm->pp_msi[msinum];
849 bus_space_write_8(sc->sc_bust, sc->sc_csrh,
850 FIRE_MSI_CLEAR(msinum), FIRE_MSI_CLEAR_EQWR_N);
851
852 send_softint(ih->ih_pil, ih);
853
854 head += 1;
855 head &= eq->eq_mask;
856 } while (head != tail);
857
858 bus_space_write_8(sc->sc_bust, sc->sc_csrh, eq->eq_head, head);
859
860 return (1);
861 }
862
863 #ifdef DDB
864 void
pyro_xir(void * arg,int cpu)865 pyro_xir(void *arg, int cpu)
866 {
867 struct pyro_softc *sc = arg;
868
869 bus_space_write_8(sc->sc_bust, sc->sc_xbch, FIRE_RESET_GEN,
870 FIRE_RESET_GEN_XIR);
871 }
872 #endif
873
874 const struct cfattach pyro_ca = {
875 sizeof(struct pyro_softc), pyro_match, pyro_attach
876 };
877
878 struct cfdriver pyro_cd = {
879 NULL, "pyro", DV_DULL
880 };
881