1 /* $OpenBSD: bcmgenetreg.h,v 1.1 2020/04/14 21:02:39 kettenis Exp $ */ 2 /* $NetBSD: bcmgenetreg.h,v 1.2 2020/02/22 13:41:41 jmcneill Exp $ */ 3 4 /*- 5 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom GENETv5 32 */ 33 34 #ifndef _BCMGENETREG_H 35 #define _BCMGENETREG_H 36 37 #define __BIT(__n) (1U << (__n)) 38 #define __BITS(__n, __m) ((__BIT((__n) - (__m) + 1) - 1) << (__m)) 39 40 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 41 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 42 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 43 44 #define GENET_SYS_REV_CTRL 0x000 45 #define GENET_SYS_REV_MAJOR __BITS(27,24) 46 #define GENET_SYS_REV_MINOR __BITS(19,16) 47 #define GENET_SYS_PORT_CTRL 0x004 48 #define GENET_SYS_PORT_MODE_EXT_GPHY 3 49 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008 50 #define GENET_SYS_RBUF_FLUSH_RESET __BIT(1) 51 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c 52 #define GENET_EXT_RGMII_OOB_CTRL 0x08c 53 #define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16) 54 #define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6) 55 #define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5) 56 #define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4) 57 #define GENET_INTRL2_CPU_STAT 0x200 58 #define GENET_INTRL2_CPU_CLEAR 0x208 59 #define GENET_INTRL2_CPU_STAT_MASK 0x20c 60 #define GENET_INTRL2_CPU_SET_MASK 0x210 61 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214 62 #define GENET_IRQ_MDIO_ERROR __BIT(24) 63 #define GENET_IRQ_MDIO_DONE __BIT(23) 64 #define GENET_IRQ_TXDMA_DONE __BIT(16) 65 #define GENET_IRQ_RXDMA_DONE __BIT(13) 66 #define GENET_RBUF_CTRL 0x300 67 #define GENET_RBUF_BAD_DIS __BIT(2) 68 #define GENET_RBUF_ALIGN_2B __BIT(1) 69 #define GENET_RBUF_64B_EN __BIT(0) 70 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4 71 #define GENET_UMAC_CMD 0x808 72 #define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15) 73 #define GENET_UMAC_CMD_SW_RESET __BIT(13) 74 #define GENET_UMAC_CMD_PROMISC __BIT(4) 75 #define GENET_UMAC_CMD_SPEED __BITS(3,2) 76 #define GENET_UMAC_CMD_SPEED_10 0 77 #define GENET_UMAC_CMD_SPEED_100 1 78 #define GENET_UMAC_CMD_SPEED_1000 2 79 #define GENET_UMAC_CMD_RXEN __BIT(1) 80 #define GENET_UMAC_CMD_TXEN __BIT(0) 81 #define GENET_UMAC_MAC0 0x80c 82 #define GENET_UMAC_MAC1 0x810 83 #define GENET_UMAC_MAX_FRAME_LEN 0x814 84 #define GENET_UMAC_TX_FLUSH 0xb34 85 #define GENET_UMAC_MIB_CTRL 0xd80 86 #define GENET_UMAC_MIB_RESET_TX __BIT(2) 87 #define GENET_UMAC_MIB_RESET_RUNT __BIT(1) 88 #define GENET_UMAC_MIB_RESET_RX __BIT(0) 89 #define GENET_MDIO_CMD 0xe14 90 #define GENET_MDIO_START_BUSY __BIT(29) 91 #define GENET_MDIO_READ __BIT(27) 92 #define GENET_MDIO_WRITE __BIT(26) 93 #define GENET_MDIO_PMD __BITS(25,21) 94 #define GENET_MDIO_REG __BITS(20,16) 95 #define GENET_UMAC_MDF_CTRL 0xe50 96 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8) 97 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8) 98 99 #define GENET_DMA_DESC_COUNT 256 100 #define GENET_DMA_DESC_SIZE 12 101 #define GENET_DMA_DEFAULT_QUEUE 16 102 103 #define GENET_DMA_RING_SIZE 0x40 104 #define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1)) 105 106 #define GENET_RX_BASE 0x2000 107 #define GENET_TX_BASE 0x4000 108 109 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 110 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00) 111 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04) 112 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08) 113 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c) 114 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10) 115 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 116 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 117 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14) 118 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18) 119 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c) 120 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20) 121 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28) 122 #define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16) 123 #define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0) 124 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c) 125 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30) 126 127 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 128 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00) 129 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04) 130 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08) 131 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c) 132 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10) 133 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 134 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 135 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14) 136 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18) 137 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c) 138 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20) 139 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24) 140 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28) 141 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c) 142 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30) 143 144 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 145 #define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16) 146 #define GENET_RX_DESC_STATUS_OWN __BIT(15) 147 #define GENET_RX_DESC_STATUS_EOP __BIT(14) 148 #define GENET_RX_DESC_STATUS_SOP __BIT(13) 149 #define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2) 150 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 151 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 152 153 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 154 #define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16) 155 #define GENET_TX_DESC_STATUS_OWN __BIT(15) 156 #define GENET_TX_DESC_STATUS_EOP __BIT(14) 157 #define GENET_TX_DESC_STATUS_SOP __BIT(13) 158 #define GENET_TX_DESC_STATUS_QTAG __BITS(12,7) 159 #define GENET_TX_DESC_STATUS_CRC __BIT(6) 160 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 161 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 162 163 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00) 164 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04) 165 #define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 166 #define GENET_RX_DMA_CTRL_EN __BIT(0) 167 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c) 168 169 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00) 170 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04) 171 #define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 172 #define GENET_TX_DMA_CTRL_EN __BIT(0) 173 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c) 174 175 #endif /* !_BCMGENETREG_H */ 176