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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h377 return getGeneration() >= AMDGPUSubtarget::GFX9; in hasMed3_16()
381 return getGeneration() >= AMDGPUSubtarget::GFX9; in hasMin3Max3_16()
414 return getGeneration() >= GFX9; in supportsGetDoorbellID()
474 return getGeneration() >= AMDGPUSubtarget::GFX9; in supportsMinMaxDenormModes()
505 return getGeneration() < AMDGPUSubtarget::GFX9; in privateMemoryResourceIsRangeChecked()
615 return getGeneration() >= GFX9; in hasMultiDwordFlatScratchAddressing()
623 return getGeneration() > GFX9; in hasFlatLgkmVMemCountInOrder()
627 return getGeneration() >= GFX9; in hasD16LoadStore()
641 return getGeneration() < GFX9; in ldsRequiresM0Init()
650 return getGeneration() >= GFX9; in hasGWSAutoReplay()
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H A DAMDGPU.td319 "Additional instructions for GFX9+"
355 "Instructions shared in GFX7, GFX8, GFX9"
909 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
1476 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1483 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1498 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1505 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1522 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1526 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1567 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
[all …]
H A DAMDGPUSubtarget.h40 GFX9 = 8, enumerator
H A DSMInstructions.td504 // VI and GFX9.
518 // Note that for GFX9 instructions with immediate offsets, soffset_en
520 // meaning GFX9 is not perfectly backward-compatible with GFX8, despite
537 // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
557 // The alternative GFX9 SGPR encoding using soffset to encode the
558 // offset register. Not available in assembler and goes to the GFX9
564 int Subtarget = SIEncodingFamily.GFX9;
652 // GFX9
H A DVOP1Instructions.td1036 // GFX8, GFX9 (VI).
1236 // GFX9
1240 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1251 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1257 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1270 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1276 let AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX9" in
H A DGCNProcessors.td160 // GCN GFX9.
H A DVOP2Instructions.td1079 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
1973 // GFX8, GFX9 (VI).
1986 let DecoderNamespace = "GFX9";
2068 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
2072 let DecoderNamespace = "GFX9";
2075 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
2079 let DecoderNamespace = "GFX9";
2100 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
2102 let DecoderNamespace = "GFX9";
2105 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
[all …]
H A DVOP3Instructions.td660 // exclude pre-GFX9 where it was slow
1174 // GFX8, GFX9 (VI).
1226 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1229 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1237 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1245 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
1253 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1260 } // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
H A DAMDGPUSubtarget.cpp155 HasSMulHi = getGeneration() >= AMDGPUSubtarget::GFX9; in initializeSubtargetDependencies()
293 return getGeneration() <= AMDGPUSubtarget::GFX9; in zeroesHigh16BitsOfDest()
H A DSIInstrFormats.td95 // in GFX9. Required for correct mapping from pseudo to MC.
H A DSOPInstructions.td1998 // SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
2149 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
2201 // GFX8 (VI), GFX9.
2341 // SOP1 - GFX9.
2351 // SOP2 - GFX9.
H A DAMDGPUSearchableTables.td77 // Buffer formats with equal component sizes (GFX9 and earlier)
H A DSIMachineFunctionInfo.cpp180 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 && in SIMachineFunctionInfo()
H A DFLATInstructions.td129 // Only valid on GFX9+
143 let Inst{55} = acc; // nv on GFX9+, TFE before. AccVGPR for data on GFX90A.
1674 let DecoderNamespace = "GFX9";
1685 let DecoderNamespace = "GFX9";
H A DSIInstrInfo.cpp7518 ST.getGeneration() <= AMDGPUSubtarget::GFX9) in getScratchRsrcWords23()
7998 GFX9 = 5, enumerator
8014 case AMDGPUSubtarget::GFX9: in subtargetEncodingFamily()
8048 ST.getGeneration() == AMDGPUSubtarget::GFX9) in pseudoToMCOpcode()
8049 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
8062 case AMDGPUSubtarget::GFX9: in pseudoToMCOpcode()
8090 NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX9); in pseudoToMCOpcode()
H A DVOPInstructions.td497 // GFX9 adds two features to SDWA:
508 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
/openbsd/gnu/llvm/llvm/docs/
H A DAMDGPUInstructionSyntax.rst120 d16_xy b16x2 2 for GFX8.0, 1 for GFX8.1 and GFX9+
121 d16_xyz b16x3 3 for GFX8.0, 2 for GFX8.1 and GFX9+
122 d16_xyzw b16x4 4 for GFX8.0, 2 for GFX8.1 and GFX9+
H A DAMDGPUOperandSyntax.rst221 GFX9 102
309 GFX9 16
687 …red_base src_shared_base Base address of shared memory region. GFX9+
688 …red_limit src_shared_limit Address of the end of shared memory region. GFX9+
689 …vate_base src_private_base Base address of private memory region. GFX9+
690 …vate_limit src_private_limit Address of the end of private memory region. GFX9+
691 …ing_wave_id src_pops_exiting_wave_id A dedicated counter for POPS. GFX9, GFX10
1056 // GFX9
1081 // GFX9
1126 // GFX9
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H A DAMDGPUUsage.rst772 GFX9-GFX11.
2549 For GFX9-GFX11 this is 4.
2552 For GFX9-GFX11 this is 1.
3975 383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-GFX9
4038 458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9
4115 GFX9
4822 instructions (GFX9-GFX11).
4868 GFX9-GFX11
5160 Memory Model GFX6-GFX9
5163 For GFX6-GFX9:
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H A DAMDGPUModifierSyntax.rst521 GFX8.1 and GFX9+ support data packing.
873 BUF_NUM_FORMAT_RESERVED_6 GFX8 and GFX9 only.
/openbsd/gnu/llvm/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX904.rst20 For a description of other gfx904 instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsm…
H A DAMDGPUAsmGFX900.rst20 …r gfx900, gfx902, gfx909 and gfx90c instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPU…
H A DAMDGPUAsmGFX906.rst20 For a description of other gfx906 instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsm…
H A DAMDGPUAsmGFX908.rst20 For a description of other gfx908 instructions, see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAs…
/openbsd/gnu/llvm/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def211 // GFX9+ only builtins.

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