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Searched refs:HasVSX (Results 1 – 10 of 10) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td1341 } // HasVSX, HasP8Vector
2446 // [HasVSX]
2447 // [HasVSX, IsBigEndian]
2449 // [HasVSX, NoP9Vector]
2454 // [HasVSX, HasP8Vector]
2468 // [HasVSX, HasP9Vector]
2921 } // HasVSX
3034 } // HasVSX, IsBigEndian
3189 } // HasVSX, NoP9Vector
3340 } // HasVSX, HasP8Vector
[all …]
H A DPPCSubtarget.cpp116 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) in initSubtargetFeatures()
H A DPPCInstrFuture.td54 let Predicates = [HasVSX, IsISAFuture] in {
H A DPPCInstrP10.td1854 let Predicates = [IsISA3_1, HasVSX] in {
2013 let Predicates = [IsISA3_1, HasVSX] in {
2043 let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2313 let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2347 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2360 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2384 let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
H A DPPC.td150 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
H A DPPCISelDAGToDAG.cpp4206 bool HasVSX, bool &Swap, bool &Negate) { in getVCmpInst() argument
4234 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP; in getVCmpInst()
4241 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP; in getVCmpInst()
4248 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP; in getVCmpInst()
H A DPPCInstrAltivec.td1316 // !HasVSX predicate. This essentially favours VSX over Altivec, in
H A DPPCISelLowering.cpp6823 bool HasVSX) { in getRegClassForSVT() argument
6837 return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass; in getRegClassForSVT()
/openbsd/gnu/llvm/clang/lib/Basic/Targets/
H A DPPC.cpp38 HasVSX = true; in handleTargetFeatures()
389 if (HasVSX) in getTargetDefines()
660 .Case("vsx", HasVSX) in hasFeature()
H A DPPC.h63 bool HasVSX = false; variable