1 /* $OpenBSD: if_icereg.h,v 1.2 2024/11/25 12:50:47 stsp Exp $ */
2
3 /* Copyright (c) 2024, Intel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 *
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * 3. Neither the name of the Intel Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /* Machine generated file. Do not edit. */
34
35 #ifndef _ICE_HW_AUTOGEN_H_
36 #define _ICE_HW_AUTOGEN_H_
37
38 /* portability goo */
39 #define BIT(x) (1UL << (x))
40 #define BIT_ULL(x) (1ULL << (x))
41 #define MAKEMASK(_m, _s) ((_m) << (_s))
42
43 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
44 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
45 #define GL_HICR 0x00082040
46 #define GL_HICR_EN 0x00082044
47 #define GLGEN_CSR_DEBUG_C 0x00075750
48 #define GLNVM_GENS 0x000B6100
49 #define GLNVM_FLA 0x000B6108
50 #define GL_HIDA_MAX_INDEX 15
51 #define GL_HIBA_MAX_INDEX 1023
52 #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
53 #define GL_RDPU_CNTRL_RX_PAD_EN_S 0
54 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
55 #define GL_RDPU_CNTRL_UDP_ZERO_EN_S 1
56 #define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
57 #define GL_RDPU_CNTRL_BLNC_EN_S 2
58 #define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
59 #define GL_RDPU_CNTRL_RECIPE_BYPASS_S 3
60 #define GL_RDPU_CNTRL_RECIPE_BYPASS_M BIT(3)
61 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_S 4
62 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 4)
63 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_S 10
64 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 10)
65 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_S 16
66 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16)
67 #define GL_RDPU_CNTRL_ECO_S 21
68 #define GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21)
69 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
70 #define MSIX_PBA_MAX_INDEX 2
71 #define MSIX_PBA_PENBIT_S 0
72 #define MSIX_PBA_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
73 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
74 #define MSIX_TADD_MAX_INDEX 64
75 #define MSIX_TADD_MSIXTADD10_S 0
76 #define MSIX_TADD_MSIXTADD10_M MAKEMASK(0x3, 0)
77 #define MSIX_TADD_MSIXTADD_S 2
78 #define MSIX_TADD_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
79 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
80 #define MSIX_TUADD_MAX_INDEX 64
81 #define MSIX_TUADD_MSIXTUADD_S 0
82 #define MSIX_TUADD_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
83 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
84 #define MSIX_TVCTRL_MAX_INDEX 64
85 #define MSIX_TVCTRL_MASK_S 0
86 #define MSIX_TVCTRL_MASK_M BIT(0)
87 #define PF0_FW_HLP_ARQBAH_PAGE 0x02D00180 /* Reset Source: EMPR */
88 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_S 0
89 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
90 #define PF0_FW_HLP_ARQBAL_PAGE 0x02D00080 /* Reset Source: EMPR */
91 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
92 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
93 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_S 6
94 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
95 #define PF0_FW_HLP_ARQH_PAGE 0x02D00380 /* Reset Source: EMPR */
96 #define PF0_FW_HLP_ARQH_PAGE_ARQH_S 0
97 #define PF0_FW_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
98 #define PF0_FW_HLP_ARQLEN_PAGE 0x02D00280 /* Reset Source: EMPR */
99 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_S 0
100 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
101 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_S 28
102 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
103 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_S 29
104 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
105 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_S 30
106 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
107 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_S 31
108 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
109 #define PF0_FW_HLP_ARQT_PAGE 0x02D00480 /* Reset Source: EMPR */
110 #define PF0_FW_HLP_ARQT_PAGE_ARQT_S 0
111 #define PF0_FW_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
112 #define PF0_FW_HLP_ATQBAH_PAGE 0x02D00100 /* Reset Source: EMPR */
113 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_S 0
114 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
115 #define PF0_FW_HLP_ATQBAL_PAGE 0x02D00000 /* Reset Source: EMPR */
116 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_S 0
117 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
118 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_S 6
119 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
120 #define PF0_FW_HLP_ATQH_PAGE 0x02D00300 /* Reset Source: EMPR */
121 #define PF0_FW_HLP_ATQH_PAGE_ATQH_S 0
122 #define PF0_FW_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
123 #define PF0_FW_HLP_ATQLEN_PAGE 0x02D00200 /* Reset Source: EMPR */
124 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_S 0
125 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
126 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_S 28
127 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
128 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_S 29
129 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
130 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_S 30
131 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
132 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_S 31
133 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
134 #define PF0_FW_HLP_ATQT_PAGE 0x02D00400 /* Reset Source: EMPR */
135 #define PF0_FW_HLP_ATQT_PAGE_ATQT_S 0
136 #define PF0_FW_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
137 #define PF0_FW_PSM_ARQBAH_PAGE 0x02D40180 /* Reset Source: EMPR */
138 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_S 0
139 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
140 #define PF0_FW_PSM_ARQBAL_PAGE 0x02D40080 /* Reset Source: EMPR */
141 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
142 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
143 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_S 6
144 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
145 #define PF0_FW_PSM_ARQH_PAGE 0x02D40380 /* Reset Source: EMPR */
146 #define PF0_FW_PSM_ARQH_PAGE_ARQH_S 0
147 #define PF0_FW_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
148 #define PF0_FW_PSM_ARQLEN_PAGE 0x02D40280 /* Reset Source: EMPR */
149 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_S 0
150 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
151 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_S 28
152 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
153 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_S 29
154 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
155 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_S 30
156 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
157 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_S 31
158 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
159 #define PF0_FW_PSM_ARQT_PAGE 0x02D40480 /* Reset Source: EMPR */
160 #define PF0_FW_PSM_ARQT_PAGE_ARQT_S 0
161 #define PF0_FW_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
162 #define PF0_FW_PSM_ATQBAH_PAGE 0x02D40100 /* Reset Source: EMPR */
163 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_S 0
164 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
165 #define PF0_FW_PSM_ATQBAL_PAGE 0x02D40000 /* Reset Source: EMPR */
166 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_S 0
167 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
168 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_S 6
169 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
170 #define PF0_FW_PSM_ATQH_PAGE 0x02D40300 /* Reset Source: EMPR */
171 #define PF0_FW_PSM_ATQH_PAGE_ATQH_S 0
172 #define PF0_FW_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
173 #define PF0_FW_PSM_ATQLEN_PAGE 0x02D40200 /* Reset Source: EMPR */
174 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_S 0
175 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
176 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_S 28
177 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
178 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_S 29
179 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
180 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_S 30
181 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
182 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_S 31
183 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
184 #define PF0_FW_PSM_ATQT_PAGE 0x02D40400 /* Reset Source: EMPR */
185 #define PF0_FW_PSM_ATQT_PAGE_ATQT_S 0
186 #define PF0_FW_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
187 #define PF0_MBX_CPM_ARQBAH_PAGE 0x02D80190 /* Reset Source: CORER */
188 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_S 0
189 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
190 #define PF0_MBX_CPM_ARQBAL_PAGE 0x02D80090 /* Reset Source: CORER */
191 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
192 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
193 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_S 6
194 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
195 #define PF0_MBX_CPM_ARQH_PAGE 0x02D80390 /* Reset Source: CORER */
196 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_S 0
197 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
198 #define PF0_MBX_CPM_ARQLEN_PAGE 0x02D80290 /* Reset Source: PFR */
199 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S 0
200 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
201 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_S 28
202 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
203 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_S 29
204 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
205 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_S 30
206 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
207 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_S 31
208 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
209 #define PF0_MBX_CPM_ARQT_PAGE 0x02D80490 /* Reset Source: CORER */
210 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_S 0
211 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
212 #define PF0_MBX_CPM_ATQBAH_PAGE 0x02D80110 /* Reset Source: CORER */
213 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_S 0
214 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
215 #define PF0_MBX_CPM_ATQBAL_PAGE 0x02D80010 /* Reset Source: CORER */
216 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_S 6
217 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
218 #define PF0_MBX_CPM_ATQH_PAGE 0x02D80310 /* Reset Source: CORER */
219 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_S 0
220 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
221 #define PF0_MBX_CPM_ATQLEN_PAGE 0x02D80210 /* Reset Source: PFR */
222 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S 0
223 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
224 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_S 28
225 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
226 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_S 29
227 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
228 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_S 30
229 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
230 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_S 31
231 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
232 #define PF0_MBX_CPM_ATQT_PAGE 0x02D80410 /* Reset Source: CORER */
233 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_S 0
234 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
235 #define PF0_MBX_HLP_ARQBAH_PAGE 0x02D00190 /* Reset Source: CORER */
236 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_S 0
237 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
238 #define PF0_MBX_HLP_ARQBAL_PAGE 0x02D00090 /* Reset Source: CORER */
239 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
240 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
241 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_S 6
242 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
243 #define PF0_MBX_HLP_ARQH_PAGE 0x02D00390 /* Reset Source: CORER */
244 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_S 0
245 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
246 #define PF0_MBX_HLP_ARQLEN_PAGE 0x02D00290 /* Reset Source: PFR */
247 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S 0
248 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
249 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_S 28
250 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
251 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_S 29
252 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
253 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_S 30
254 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
255 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_S 31
256 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
257 #define PF0_MBX_HLP_ARQT_PAGE 0x02D00490 /* Reset Source: CORER */
258 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_S 0
259 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
260 #define PF0_MBX_HLP_ATQBAH_PAGE 0x02D00110 /* Reset Source: CORER */
261 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_S 0
262 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
263 #define PF0_MBX_HLP_ATQBAL_PAGE 0x02D00010 /* Reset Source: CORER */
264 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_S 6
265 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
266 #define PF0_MBX_HLP_ATQH_PAGE 0x02D00310 /* Reset Source: CORER */
267 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_S 0
268 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
269 #define PF0_MBX_HLP_ATQLEN_PAGE 0x02D00210 /* Reset Source: PFR */
270 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S 0
271 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
272 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_S 28
273 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
274 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_S 29
275 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
276 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_S 30
277 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
278 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_S 31
279 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
280 #define PF0_MBX_HLP_ATQT_PAGE 0x02D00410 /* Reset Source: CORER */
281 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_S 0
282 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
283 #define PF0_MBX_PSM_ARQBAH_PAGE 0x02D40190 /* Reset Source: CORER */
284 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_S 0
285 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
286 #define PF0_MBX_PSM_ARQBAL_PAGE 0x02D40090 /* Reset Source: CORER */
287 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
288 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
289 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_S 6
290 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
291 #define PF0_MBX_PSM_ARQH_PAGE 0x02D40390 /* Reset Source: CORER */
292 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_S 0
293 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
294 #define PF0_MBX_PSM_ARQLEN_PAGE 0x02D40290 /* Reset Source: PFR */
295 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S 0
296 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
297 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_S 28
298 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
299 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_S 29
300 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
301 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_S 30
302 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
303 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_S 31
304 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
305 #define PF0_MBX_PSM_ARQT_PAGE 0x02D40490 /* Reset Source: CORER */
306 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_S 0
307 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
308 #define PF0_MBX_PSM_ATQBAH_PAGE 0x02D40110 /* Reset Source: CORER */
309 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_S 0
310 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
311 #define PF0_MBX_PSM_ATQBAL_PAGE 0x02D40010 /* Reset Source: CORER */
312 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_S 6
313 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
314 #define PF0_MBX_PSM_ATQH_PAGE 0x02D40310 /* Reset Source: CORER */
315 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_S 0
316 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
317 #define PF0_MBX_PSM_ATQLEN_PAGE 0x02D40210 /* Reset Source: PFR */
318 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S 0
319 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
320 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_S 28
321 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
322 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_S 29
323 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
324 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_S 30
325 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
326 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_S 31
327 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
328 #define PF0_MBX_PSM_ATQT_PAGE 0x02D40410 /* Reset Source: CORER */
329 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_S 0
330 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
331 #define PF0_SB_CPM_ARQBAH_PAGE 0x02D801A0 /* Reset Source: CORER */
332 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_S 0
333 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
334 #define PF0_SB_CPM_ARQBAL_PAGE 0x02D800A0 /* Reset Source: CORER */
335 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
336 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
337 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_S 6
338 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
339 #define PF0_SB_CPM_ARQH_PAGE 0x02D803A0 /* Reset Source: CORER */
340 #define PF0_SB_CPM_ARQH_PAGE_ARQH_S 0
341 #define PF0_SB_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
342 #define PF0_SB_CPM_ARQLEN_PAGE 0x02D802A0 /* Reset Source: PFR */
343 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S 0
344 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
345 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_S 28
346 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
347 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_S 29
348 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
349 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_S 30
350 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
351 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_S 31
352 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
353 #define PF0_SB_CPM_ARQT_PAGE 0x02D804A0 /* Reset Source: CORER */
354 #define PF0_SB_CPM_ARQT_PAGE_ARQT_S 0
355 #define PF0_SB_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
356 #define PF0_SB_CPM_ATQBAH_PAGE 0x02D80120 /* Reset Source: CORER */
357 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_S 0
358 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
359 #define PF0_SB_CPM_ATQBAL_PAGE 0x02D80020 /* Reset Source: CORER */
360 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_S 6
361 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
362 #define PF0_SB_CPM_ATQH_PAGE 0x02D80320 /* Reset Source: CORER */
363 #define PF0_SB_CPM_ATQH_PAGE_ATQH_S 0
364 #define PF0_SB_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
365 #define PF0_SB_CPM_ATQLEN_PAGE 0x02D80220 /* Reset Source: PFR */
366 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S 0
367 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
368 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_S 28
369 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
370 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_S 29
371 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
372 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_S 30
373 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
374 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_S 31
375 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
376 #define PF0_SB_CPM_ATQT_PAGE 0x02D80420 /* Reset Source: CORER */
377 #define PF0_SB_CPM_ATQT_PAGE_ATQT_S 0
378 #define PF0_SB_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
379 #define PF0_SB_HLP_ARQBAH_PAGE 0x02D001A0 /* Reset Source: CORER */
380 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_S 0
381 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
382 #define PF0_SB_HLP_ARQBAL_PAGE 0x02D000A0 /* Reset Source: CORER */
383 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
384 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
385 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_S 6
386 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
387 #define PF0_SB_HLP_ARQH_PAGE 0x02D003A0 /* Reset Source: CORER */
388 #define PF0_SB_HLP_ARQH_PAGE_ARQH_S 0
389 #define PF0_SB_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
390 #define PF0_SB_HLP_ARQLEN_PAGE 0x02D002A0 /* Reset Source: PFR */
391 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S 0
392 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
393 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_S 28
394 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
395 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_S 29
396 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
397 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_S 30
398 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
399 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_S 31
400 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
401 #define PF0_SB_HLP_ARQT_PAGE 0x02D004A0 /* Reset Source: CORER */
402 #define PF0_SB_HLP_ARQT_PAGE_ARQT_S 0
403 #define PF0_SB_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
404 #define PF0_SB_HLP_ATQBAH_PAGE 0x02D00120 /* Reset Source: CORER */
405 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_S 0
406 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
407 #define PF0_SB_HLP_ATQBAL_PAGE 0x02D00020 /* Reset Source: CORER */
408 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_S 6
409 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
410 #define PF0_SB_HLP_ATQH_PAGE 0x02D00320 /* Reset Source: CORER */
411 #define PF0_SB_HLP_ATQH_PAGE_ATQH_S 0
412 #define PF0_SB_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
413 #define PF0_SB_HLP_ATQLEN_PAGE 0x02D00220 /* Reset Source: PFR */
414 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S 0
415 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
416 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_S 28
417 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
418 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_S 29
419 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
420 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_S 30
421 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
422 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_S 31
423 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
424 #define PF0_SB_HLP_ATQT_PAGE 0x02D00420 /* Reset Source: CORER */
425 #define PF0_SB_HLP_ATQT_PAGE_ATQT_S 0
426 #define PF0_SB_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
427 #define PF0INT_DYN_CTL(_i) (0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
428 #define PF0INT_DYN_CTL_MAX_INDEX 2047
429 #define PF0INT_DYN_CTL_INTENA_S 0
430 #define PF0INT_DYN_CTL_INTENA_M BIT(0)
431 #define PF0INT_DYN_CTL_CLEARPBA_S 1
432 #define PF0INT_DYN_CTL_CLEARPBA_M BIT(1)
433 #define PF0INT_DYN_CTL_SWINT_TRIG_S 2
434 #define PF0INT_DYN_CTL_SWINT_TRIG_M BIT(2)
435 #define PF0INT_DYN_CTL_ITR_INDX_S 3
436 #define PF0INT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
437 #define PF0INT_DYN_CTL_INTERVAL_S 5
438 #define PF0INT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
439 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_S 24
440 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
441 #define PF0INT_DYN_CTL_SW_ITR_INDX_S 25
442 #define PF0INT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
443 #define PF0INT_DYN_CTL_WB_ON_ITR_S 30
444 #define PF0INT_DYN_CTL_WB_ON_ITR_M BIT(30)
445 #define PF0INT_DYN_CTL_INTENA_MSK_S 31
446 #define PF0INT_DYN_CTL_INTENA_MSK_M BIT(31)
447 #define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
448 #define PF0INT_ITR_0_MAX_INDEX 2047
449 #define PF0INT_ITR_0_INTERVAL_S 0
450 #define PF0INT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
451 #define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
452 #define PF0INT_ITR_1_MAX_INDEX 2047
453 #define PF0INT_ITR_1_INTERVAL_S 0
454 #define PF0INT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
455 #define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
456 #define PF0INT_ITR_2_MAX_INDEX 2047
457 #define PF0INT_ITR_2_INTERVAL_S 0
458 #define PF0INT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
459 #define PF0INT_OICR_CPM_PAGE 0x02D03000 /* Reset Source: CORER */
460 #define PF0INT_OICR_CPM_PAGE_INTEVENT_S 0
461 #define PF0INT_OICR_CPM_PAGE_INTEVENT_M BIT(0)
462 #define PF0INT_OICR_CPM_PAGE_QUEUE_S 1
463 #define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1)
464 #define PF0INT_OICR_CPM_PAGE_RSV1_S 2
465 #define PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
466 #define PF0INT_OICR_CPM_PAGE_HH_COMP_S 10
467 #define PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10)
468 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_S 11
469 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11)
470 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S 12
471 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_M BIT(12)
472 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_S 13
473 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_M BIT(13)
474 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_S 14
475 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_M BIT(14)
476 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_S 15
477 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_M BIT(15)
478 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_S 16
479 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_M BIT(16)
480 #define PF0INT_OICR_CPM_PAGE_RSV2_S 17
481 #define PF0INT_OICR_CPM_PAGE_RSV2_M MAKEMASK(0x3, 17)
482 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_S 19
483 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_M BIT(19)
484 #define PF0INT_OICR_CPM_PAGE_GRST_S 20
485 #define PF0INT_OICR_CPM_PAGE_GRST_M BIT(20)
486 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S 21
487 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21)
488 #define PF0INT_OICR_CPM_PAGE_GPIO_S 22
489 #define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22)
490 #define PF0INT_OICR_CPM_PAGE_RSV3_S 23
491 #define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)
492 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24
493 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)
494 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
495 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
496 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26
497 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)
498 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27
499 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27)
500 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S 28
501 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28)
502 #define PF0INT_OICR_CPM_PAGE_VFLR_S 29
503 #define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29)
504 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_S 30
505 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_M BIT(30)
506 #define PF0INT_OICR_CPM_PAGE_SWINT_S 31
507 #define PF0INT_OICR_CPM_PAGE_SWINT_M BIT(31)
508 #define PF0INT_OICR_ENA_CPM_PAGE 0x02D03100 /* Reset Source: CORER */
509 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_S 0
510 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M BIT(0)
511 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_S 1
512 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
513 #define PF0INT_OICR_ENA_HLP_PAGE 0x02D01100 /* Reset Source: CORER */
514 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_S 0
515 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M BIT(0)
516 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_S 1
517 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
518 #define PF0INT_OICR_ENA_PSM_PAGE 0x02D02100 /* Reset Source: CORER */
519 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_S 0
520 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M BIT(0)
521 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_S 1
522 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
523 #define PF0INT_OICR_HLP_PAGE 0x02D01000 /* Reset Source: CORER */
524 #define PF0INT_OICR_HLP_PAGE_INTEVENT_S 0
525 #define PF0INT_OICR_HLP_PAGE_INTEVENT_M BIT(0)
526 #define PF0INT_OICR_HLP_PAGE_QUEUE_S 1
527 #define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1)
528 #define PF0INT_OICR_HLP_PAGE_RSV1_S 2
529 #define PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2)
530 #define PF0INT_OICR_HLP_PAGE_HH_COMP_S 10
531 #define PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10)
532 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_S 11
533 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11)
534 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S 12
535 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_M BIT(12)
536 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_S 13
537 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_M BIT(13)
538 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_S 14
539 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_M BIT(14)
540 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_S 15
541 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_M BIT(15)
542 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_S 16
543 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_M BIT(16)
544 #define PF0INT_OICR_HLP_PAGE_RSV2_S 17
545 #define PF0INT_OICR_HLP_PAGE_RSV2_M MAKEMASK(0x3, 17)
546 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_S 19
547 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_M BIT(19)
548 #define PF0INT_OICR_HLP_PAGE_GRST_S 20
549 #define PF0INT_OICR_HLP_PAGE_GRST_M BIT(20)
550 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S 21
551 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21)
552 #define PF0INT_OICR_HLP_PAGE_GPIO_S 22
553 #define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22)
554 #define PF0INT_OICR_HLP_PAGE_RSV3_S 23
555 #define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)
556 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24
557 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)
558 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
559 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
560 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26
561 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)
562 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27
563 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27)
564 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S 28
565 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28)
566 #define PF0INT_OICR_HLP_PAGE_VFLR_S 29
567 #define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29)
568 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_S 30
569 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_M BIT(30)
570 #define PF0INT_OICR_HLP_PAGE_SWINT_S 31
571 #define PF0INT_OICR_HLP_PAGE_SWINT_M BIT(31)
572 #define PF0INT_OICR_PSM_PAGE 0x02D02000 /* Reset Source: CORER */
573 #define PF0INT_OICR_PSM_PAGE_INTEVENT_S 0
574 #define PF0INT_OICR_PSM_PAGE_INTEVENT_M BIT(0)
575 #define PF0INT_OICR_PSM_PAGE_QUEUE_S 1
576 #define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1)
577 #define PF0INT_OICR_PSM_PAGE_RSV1_S 2
578 #define PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
579 #define PF0INT_OICR_PSM_PAGE_HH_COMP_S 10
580 #define PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10)
581 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_S 11
582 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11)
583 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S 12
584 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_M BIT(12)
585 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_S 13
586 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_M BIT(13)
587 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_S 14
588 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_M BIT(14)
589 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_S 15
590 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_M BIT(15)
591 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_S 16
592 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_M BIT(16)
593 #define PF0INT_OICR_PSM_PAGE_RSV2_S 17
594 #define PF0INT_OICR_PSM_PAGE_RSV2_M MAKEMASK(0x3, 17)
595 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_S 19
596 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_M BIT(19)
597 #define PF0INT_OICR_PSM_PAGE_GRST_S 20
598 #define PF0INT_OICR_PSM_PAGE_GRST_M BIT(20)
599 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S 21
600 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21)
601 #define PF0INT_OICR_PSM_PAGE_GPIO_S 22
602 #define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22)
603 #define PF0INT_OICR_PSM_PAGE_RSV3_S 23
604 #define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)
605 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24
606 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)
607 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
608 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
609 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26
610 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)
611 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27
612 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27)
613 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S 28
614 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28)
615 #define PF0INT_OICR_PSM_PAGE_VFLR_S 29
616 #define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29)
617 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_S 30
618 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_M BIT(30)
619 #define PF0INT_OICR_PSM_PAGE_SWINT_S 31
620 #define PF0INT_OICR_PSM_PAGE_SWINT_M BIT(31)
621 #define QRX_TAIL_PAGE(_QRX) (0x03800000 + ((_QRX) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
622 #define QRX_TAIL_PAGE_MAX_INDEX 2047
623 #define QRX_TAIL_PAGE_TAIL_S 0
624 #define QRX_TAIL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
625 #define QTX_COMM_DBELL_PAGE(_DBQM) (0x04000000 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
626 #define QTX_COMM_DBELL_PAGE_MAX_INDEX 16383
627 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S 0
628 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
629 #define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
630 #define QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX 255
631 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0
632 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
633 #define VSI_MBX_ARQBAH(_VSI) (0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
634 #define VSI_MBX_ARQBAH_MAX_INDEX 767
635 #define VSI_MBX_ARQBAH_ARQBAH_S 0
636 #define VSI_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
637 #define VSI_MBX_ARQBAL(_VSI) (0x02000014 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
638 #define VSI_MBX_ARQBAL_MAX_INDEX 767
639 #define VSI_MBX_ARQBAL_ARQBAL_LSB_S 0
640 #define VSI_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
641 #define VSI_MBX_ARQBAL_ARQBAL_S 6
642 #define VSI_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
643 #define VSI_MBX_ARQH(_VSI) (0x02000020 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
644 #define VSI_MBX_ARQH_MAX_INDEX 767
645 #define VSI_MBX_ARQH_ARQH_S 0
646 #define VSI_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
647 #define VSI_MBX_ARQLEN(_VSI) (0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
648 #define VSI_MBX_ARQLEN_MAX_INDEX 767
649 #define VSI_MBX_ARQLEN_ARQLEN_S 0
650 #define VSI_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
651 #define VSI_MBX_ARQLEN_ARQVFE_S 28
652 #define VSI_MBX_ARQLEN_ARQVFE_M BIT(28)
653 #define VSI_MBX_ARQLEN_ARQOVFL_S 29
654 #define VSI_MBX_ARQLEN_ARQOVFL_M BIT(29)
655 #define VSI_MBX_ARQLEN_ARQCRIT_S 30
656 #define VSI_MBX_ARQLEN_ARQCRIT_M BIT(30)
657 #define VSI_MBX_ARQLEN_ARQENABLE_S 31
658 #define VSI_MBX_ARQLEN_ARQENABLE_M BIT(31)
659 #define VSI_MBX_ARQT(_VSI) (0x02000024 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
660 #define VSI_MBX_ARQT_MAX_INDEX 767
661 #define VSI_MBX_ARQT_ARQT_S 0
662 #define VSI_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
663 #define VSI_MBX_ATQBAH(_VSI) (0x02000004 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
664 #define VSI_MBX_ATQBAH_MAX_INDEX 767
665 #define VSI_MBX_ATQBAH_ATQBAH_S 0
666 #define VSI_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
667 #define VSI_MBX_ATQBAL(_VSI) (0x02000000 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
668 #define VSI_MBX_ATQBAL_MAX_INDEX 767
669 #define VSI_MBX_ATQBAL_ATQBAL_S 6
670 #define VSI_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
671 #define VSI_MBX_ATQH(_VSI) (0x0200000C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
672 #define VSI_MBX_ATQH_MAX_INDEX 767
673 #define VSI_MBX_ATQH_ATQH_S 0
674 #define VSI_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
675 #define VSI_MBX_ATQLEN(_VSI) (0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
676 #define VSI_MBX_ATQLEN_MAX_INDEX 767
677 #define VSI_MBX_ATQLEN_ATQLEN_S 0
678 #define VSI_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
679 #define VSI_MBX_ATQLEN_ATQVFE_S 28
680 #define VSI_MBX_ATQLEN_ATQVFE_M BIT(28)
681 #define VSI_MBX_ATQLEN_ATQOVFL_S 29
682 #define VSI_MBX_ATQLEN_ATQOVFL_M BIT(29)
683 #define VSI_MBX_ATQLEN_ATQCRIT_S 30
684 #define VSI_MBX_ATQLEN_ATQCRIT_M BIT(30)
685 #define VSI_MBX_ATQLEN_ATQENABLE_S 31
686 #define VSI_MBX_ATQLEN_ATQENABLE_M BIT(31)
687 #define VSI_MBX_ATQT(_VSI) (0x02000010 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
688 #define VSI_MBX_ATQT_MAX_INDEX 767
689 #define VSI_MBX_ATQT_ATQT_S 0
690 #define VSI_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
691 #define GL_ACL_ACCESS_CMD 0x00391000 /* Reset Source: CORER */
692 #define GL_ACL_ACCESS_CMD_TABLE_ID_S 0
693 #define GL_ACL_ACCESS_CMD_TABLE_ID_M MAKEMASK(0xFF, 0)
694 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_S 8
695 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_M MAKEMASK(0xFFF, 8)
696 #define GL_ACL_ACCESS_CMD_OPERATION_S 20
697 #define GL_ACL_ACCESS_CMD_OPERATION_M BIT(20)
698 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_S 24
699 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_M MAKEMASK(0xF, 24)
700 #define GL_ACL_ACCESS_CMD_EXECUTE_S 31
701 #define GL_ACL_ACCESS_CMD_EXECUTE_M BIT(31)
702 #define GL_ACL_ACCESS_STATUS 0x00391004 /* Reset Source: CORER */
703 #define GL_ACL_ACCESS_STATUS_BUSY_S 0
704 #define GL_ACL_ACCESS_STATUS_BUSY_M BIT(0)
705 #define GL_ACL_ACCESS_STATUS_DONE_S 1
706 #define GL_ACL_ACCESS_STATUS_DONE_M BIT(1)
707 #define GL_ACL_ACCESS_STATUS_ERROR_S 2
708 #define GL_ACL_ACCESS_STATUS_ERROR_M BIT(2)
709 #define GL_ACL_ACCESS_STATUS_OPERATION_S 3
710 #define GL_ACL_ACCESS_STATUS_OPERATION_M BIT(3)
711 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_S 4
712 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_M MAKEMASK(0xF, 4)
713 #define GL_ACL_ACCESS_STATUS_TABLE_ID_S 8
714 #define GL_ACL_ACCESS_STATUS_TABLE_ID_M MAKEMASK(0xFF, 8)
715 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_S 16
716 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_M MAKEMASK(0xFFF, 16)
717 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_S 28
718 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_M MAKEMASK(0xF, 28)
719 #define GL_ACL_ACTMEM_ACT(_i) (0x00393824 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
720 #define GL_ACL_ACTMEM_ACT_MAX_INDEX 1
721 #define GL_ACL_ACTMEM_ACT_VALUE_S 0
722 #define GL_ACL_ACTMEM_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
723 #define GL_ACL_ACTMEM_ACT_MDID_S 20
724 #define GL_ACL_ACTMEM_ACT_MDID_M MAKEMASK(0x3F, 20)
725 #define GL_ACL_ACTMEM_ACT_PRIORITY_S 28
726 #define GL_ACL_ACTMEM_ACT_PRIORITY_M MAKEMASK(0x7, 28)
727 #define GL_ACL_CHICKEN_REGISTER 0x00393810 /* Reset Source: CORER */
728 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_S 0
729 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0)
730 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_S 1
731 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_M BIT(1)
732 #define GL_ACL_DEFAULT_ACT(_i) (0x00391168 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
733 #define GL_ACL_DEFAULT_ACT_MAX_INDEX 15
734 #define GL_ACL_DEFAULT_ACT_VALUE_S 0
735 #define GL_ACL_DEFAULT_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
736 #define GL_ACL_DEFAULT_ACT_MDID_S 20
737 #define GL_ACL_DEFAULT_ACT_MDID_M MAKEMASK(0x3F, 20)
738 #define GL_ACL_DEFAULT_ACT_PRIORITY_S 28
739 #define GL_ACL_DEFAULT_ACT_PRIORITY_M MAKEMASK(0x7, 28)
740 #define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
741 #define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX 31
742 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0
743 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0)
744 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S 8
745 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)
746 #define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
747 #define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15
748 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
749 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
750 #define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
751 #define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7
752 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0
753 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0)
754 #define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
755 #define GL_ACL_PROFILE_RC_CFG_MAX_INDEX 7
756 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0
757 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0)
758 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_S 16
759 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_M MAKEMASK(0xFFFF, 16)
760 #define GL_ACL_PROFILE_RCF_MASK(_i) (0x00391108 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
761 #define GL_ACL_PROFILE_RCF_MASK_MAX_INDEX 7
762 #define GL_ACL_PROFILE_RCF_MASK_MASK_S 0
763 #define GL_ACL_PROFILE_RCF_MASK_MASK_M MAKEMASK(0xFFFF, 0)
764 #define GL_ACL_SCENARIO_ACT_CFG(_i) (0x003938AC + ((_i) * 4)) /* _i=0...19 */ /* Reset Source: CORER */
765 #define GL_ACL_SCENARIO_ACT_CFG_MAX_INDEX 19
766 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_S 0
767 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_M MAKEMASK(0xF, 0)
768 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_S 8
769 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_M BIT(8)
770 #define GL_ACL_SCENARIO_CFG_H(_i) (0x0039386C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
771 #define GL_ACL_SCENARIO_CFG_H_MAX_INDEX 15
772 #define GL_ACL_SCENARIO_CFG_H_SELECT4_S 0
773 #define GL_ACL_SCENARIO_CFG_H_SELECT4_M MAKEMASK(0x1F, 0)
774 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_S 8
775 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_M MAKEMASK(0xFF, 8)
776 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_S 24
777 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_M BIT(24)
778 #define GL_ACL_SCENARIO_CFG_H_START_SET_S 28
779 #define GL_ACL_SCENARIO_CFG_H_START_SET_M BIT(28)
780 #define GL_ACL_SCENARIO_CFG_L(_i) (0x0039382C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
781 #define GL_ACL_SCENARIO_CFG_L_MAX_INDEX 15
782 #define GL_ACL_SCENARIO_CFG_L_SELECT0_S 0
783 #define GL_ACL_SCENARIO_CFG_L_SELECT0_M MAKEMASK(0x7F, 0)
784 #define GL_ACL_SCENARIO_CFG_L_SELECT1_S 8
785 #define GL_ACL_SCENARIO_CFG_L_SELECT1_M MAKEMASK(0x7F, 8)
786 #define GL_ACL_SCENARIO_CFG_L_SELECT2_S 16
787 #define GL_ACL_SCENARIO_CFG_L_SELECT2_M MAKEMASK(0x7F, 16)
788 #define GL_ACL_SCENARIO_CFG_L_SELECT3_S 24
789 #define GL_ACL_SCENARIO_CFG_L_SELECT3_M MAKEMASK(0x7F, 24)
790 #define GL_ACL_TCAM_KEY_H 0x00393818 /* Reset Source: CORER */
791 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_S 0
792 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_M MAKEMASK(0xFF, 0)
793 #define GL_ACL_TCAM_KEY_INV_H 0x00393820 /* Reset Source: CORER */
794 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_S 0
795 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_M MAKEMASK(0xFF, 0)
796 #define GL_ACL_TCAM_KEY_INV_L 0x0039381C /* Reset Source: CORER */
797 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_S 0
798 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_M MAKEMASK(0xFFFFFFFF, 0)
799 #define GL_ACL_TCAM_KEY_L 0x00393814 /* Reset Source: CORER */
800 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_S 0
801 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_M MAKEMASK(0xFFFFFFFF, 0)
802 #define VSI_ACL_DEF_SEL(_VSI) (0x00391800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
803 #define VSI_ACL_DEF_SEL_MAX_INDEX 767
804 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_S 0
805 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 0)
806 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_S 4
807 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_M MAKEMASK(0x3, 4)
808 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_S 8
809 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 8)
810 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_S 12
811 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_M MAKEMASK(0x3, 12)
812 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
813 #define GL_SWT_L2TAG0_MAX_INDEX 7
814 #define GL_SWT_L2TAG0_DATA_S 0
815 #define GL_SWT_L2TAG0_DATA_M MAKEMASK(0xFFFFFFFF, 0)
816 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
817 #define GL_SWT_L2TAG1_MAX_INDEX 7
818 #define GL_SWT_L2TAG1_DATA_S 0
819 #define GL_SWT_L2TAG1_DATA_M MAKEMASK(0xFFFFFFFF, 0)
820 #define GL_SWT_L2TAGCTRL(_i) (0x001D2660 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
821 #define GL_SWT_L2TAGCTRL_MAX_INDEX 7
822 #define GL_SWT_L2TAGCTRL_LENGTH_S 0
823 #define GL_SWT_L2TAGCTRL_LENGTH_M MAKEMASK(0x7F, 0)
824 #define GL_SWT_L2TAGCTRL_HAS_UP_S 7
825 #define GL_SWT_L2TAGCTRL_HAS_UP_M BIT(7)
826 #define GL_SWT_L2TAGCTRL_ISVLAN_S 9
827 #define GL_SWT_L2TAGCTRL_ISVLAN_M BIT(9)
828 #define GL_SWT_L2TAGCTRL_INNERUP_S 10
829 #define GL_SWT_L2TAGCTRL_INNERUP_M BIT(10)
830 #define GL_SWT_L2TAGCTRL_OUTERUP_S 11
831 #define GL_SWT_L2TAGCTRL_OUTERUP_M BIT(11)
832 #define GL_SWT_L2TAGCTRL_LONG_S 12
833 #define GL_SWT_L2TAGCTRL_LONG_M BIT(12)
834 #define GL_SWT_L2TAGCTRL_ISMPLS_S 13
835 #define GL_SWT_L2TAGCTRL_ISMPLS_M BIT(13)
836 #define GL_SWT_L2TAGCTRL_ISNSH_S 14
837 #define GL_SWT_L2TAGCTRL_ISNSH_M BIT(14)
838 #define GL_SWT_L2TAGCTRL_ETHERTYPE_S 16
839 #define GL_SWT_L2TAGCTRL_ETHERTYPE_M MAKEMASK(0xFFFF, 16)
840 #define GL_SWT_L2TAGRXEB(_i) (0x00052000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
841 #define GL_SWT_L2TAGRXEB_MAX_INDEX 7
842 #define GL_SWT_L2TAGRXEB_OFFSET_S 0
843 #define GL_SWT_L2TAGRXEB_OFFSET_M MAKEMASK(0xFF, 0)
844 #define GL_SWT_L2TAGRXEB_LENGTH_S 8
845 #define GL_SWT_L2TAGRXEB_LENGTH_M MAKEMASK(0x3, 8)
846 #define GL_SWT_L2TAGTXIB(_i) (0x000492E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
847 #define GL_SWT_L2TAGTXIB_MAX_INDEX 7
848 #define GL_SWT_L2TAGTXIB_OFFSET_S 0
849 #define GL_SWT_L2TAGTXIB_OFFSET_M MAKEMASK(0xFF, 0)
850 #define GL_SWT_L2TAGTXIB_LENGTH_S 8
851 #define GL_SWT_L2TAGTXIB_LENGTH_M MAKEMASK(0x3, 8)
852 #define GLCM_PE_CACHESIZE 0x005046B4 /* Reset Source: CORER */
853 #define GLCM_PE_CACHESIZE_WORD_SIZE_S 0
854 #define GLCM_PE_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFFF, 0)
855 #define GLCM_PE_CACHESIZE_SETS_S 12
856 #define GLCM_PE_CACHESIZE_SETS_M MAKEMASK(0xF, 12)
857 #define GLCM_PE_CACHESIZE_WAYS_S 16
858 #define GLCM_PE_CACHESIZE_WAYS_M MAKEMASK(0x1FF, 16)
859 #define GLCOMM_CQ_CTL(_CQ) (0x000F0000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
860 #define GLCOMM_CQ_CTL_MAX_INDEX 511
861 #define GLCOMM_CQ_CTL_COMP_TYPE_S 0
862 #define GLCOMM_CQ_CTL_COMP_TYPE_M MAKEMASK(0x7, 0)
863 #define GLCOMM_CQ_CTL_CMD_S 4
864 #define GLCOMM_CQ_CTL_CMD_M MAKEMASK(0x7, 4)
865 #define GLCOMM_CQ_CTL_ID_S 16
866 #define GLCOMM_CQ_CTL_ID_M MAKEMASK(0x3FFF, 16)
867 #define GLCOMM_MIN_MAX_PKT 0x000FC064 /* Reset Source: CORER */
868 #define GLCOMM_MIN_MAX_PKT_MAHDL_S 0
869 #define GLCOMM_MIN_MAX_PKT_MAHDL_M MAKEMASK(0x3FFF, 0)
870 #define GLCOMM_MIN_MAX_PKT_MIHDL_S 16
871 #define GLCOMM_MIN_MAX_PKT_MIHDL_M MAKEMASK(0x3F, 16)
872 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_S 22
873 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_M MAKEMASK(0x3FF, 22)
874 #define GLCOMM_PKT_SHAPER_PROF(_i) (0x002D2DA8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
875 #define GLCOMM_PKT_SHAPER_PROF_MAX_INDEX 7
876 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_S 0
877 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_M MAKEMASK(0x3F, 0)
878 #define GLCOMM_QTX_CNTX_CTL 0x002D2DC8 /* Reset Source: CORER */
879 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_S 0
880 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x3FFF, 0)
881 #define GLCOMM_QTX_CNTX_CTL_CMD_S 16
882 #define GLCOMM_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16)
883 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_S 19
884 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M BIT(19)
885 #define GLCOMM_QTX_CNTX_DATA(_i) (0x002D2D40 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: CORER */
886 #define GLCOMM_QTX_CNTX_DATA_MAX_INDEX 9
887 #define GLCOMM_QTX_CNTX_DATA_DATA_S 0
888 #define GLCOMM_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
889 #define GLCOMM_QTX_CNTX_STAT 0x002D2DCC /* Reset Source: CORER */
890 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_S 0
891 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
892 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
893 #define GLCOMM_QUANTA_PROF_MAX_INDEX 15
894 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S 0
895 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M MAKEMASK(0x3FFF, 0)
896 #define GLCOMM_QUANTA_PROF_MAX_CMD_S 16
897 #define GLCOMM_QUANTA_PROF_MAX_CMD_M MAKEMASK(0xFF, 16)
898 #define GLCOMM_QUANTA_PROF_MAX_DESC_S 24
899 #define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24)
900 #define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */
901 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0
902 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)
903 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S 6
904 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)
905 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7
906 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
907 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
908 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
909 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22
910 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)
911 #define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
912 #define GLTCLAN_CQ_CNTX0_MAX_INDEX 511
913 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0
914 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0)
915 #define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
916 #define GLTCLAN_CQ_CNTX1_MAX_INDEX 511
917 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_S 0
918 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_M MAKEMASK(0x1FFFFFF, 0)
919 #define GLTCLAN_CQ_CNTX10(_CQ) (0x000F5800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
920 #define GLTCLAN_CQ_CNTX10_MAX_INDEX 511
921 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_S 0
922 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
923 #define GLTCLAN_CQ_CNTX11(_CQ) (0x000F6000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
924 #define GLTCLAN_CQ_CNTX11_MAX_INDEX 511
925 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_S 0
926 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
927 #define GLTCLAN_CQ_CNTX12(_CQ) (0x000F6800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
928 #define GLTCLAN_CQ_CNTX12_MAX_INDEX 511
929 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_S 0
930 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
931 #define GLTCLAN_CQ_CNTX13(_CQ) (0x000F7000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
932 #define GLTCLAN_CQ_CNTX13_MAX_INDEX 511
933 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_S 0
934 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
935 #define GLTCLAN_CQ_CNTX14(_CQ) (0x000F7800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
936 #define GLTCLAN_CQ_CNTX14_MAX_INDEX 511
937 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_S 0
938 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
939 #define GLTCLAN_CQ_CNTX15(_CQ) (0x000F8000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
940 #define GLTCLAN_CQ_CNTX15_MAX_INDEX 511
941 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_S 0
942 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
943 #define GLTCLAN_CQ_CNTX16(_CQ) (0x000F8800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
944 #define GLTCLAN_CQ_CNTX16_MAX_INDEX 511
945 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_S 0
946 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
947 #define GLTCLAN_CQ_CNTX17(_CQ) (0x000F9000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
948 #define GLTCLAN_CQ_CNTX17_MAX_INDEX 511
949 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_S 0
950 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
951 #define GLTCLAN_CQ_CNTX18(_CQ) (0x000F9800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
952 #define GLTCLAN_CQ_CNTX18_MAX_INDEX 511
953 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_S 0
954 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
955 #define GLTCLAN_CQ_CNTX19(_CQ) (0x000FA000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
956 #define GLTCLAN_CQ_CNTX19_MAX_INDEX 511
957 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_S 0
958 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
959 #define GLTCLAN_CQ_CNTX2(_CQ) (0x000F1800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
960 #define GLTCLAN_CQ_CNTX2_MAX_INDEX 511
961 #define GLTCLAN_CQ_CNTX2_RING_LEN_S 0
962 #define GLTCLAN_CQ_CNTX2_RING_LEN_M MAKEMASK(0x3FFFF, 0)
963 #define GLTCLAN_CQ_CNTX20(_CQ) (0x000FA800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
964 #define GLTCLAN_CQ_CNTX20_MAX_INDEX 511
965 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_S 0
966 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
967 #define GLTCLAN_CQ_CNTX21(_CQ) (0x000FB000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
968 #define GLTCLAN_CQ_CNTX21_MAX_INDEX 511
969 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_S 0
970 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
971 #define GLTCLAN_CQ_CNTX3(_CQ) (0x000F2000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
972 #define GLTCLAN_CQ_CNTX3_MAX_INDEX 511
973 #define GLTCLAN_CQ_CNTX3_GENERATION_S 0
974 #define GLTCLAN_CQ_CNTX3_GENERATION_M BIT(0)
975 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_S 1
976 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_M MAKEMASK(0x3FFFFF, 1)
977 #define GLTCLAN_CQ_CNTX4(_CQ) (0x000F2800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
978 #define GLTCLAN_CQ_CNTX4_MAX_INDEX 511
979 #define GLTCLAN_CQ_CNTX4_PF_NUM_S 0
980 #define GLTCLAN_CQ_CNTX4_PF_NUM_M MAKEMASK(0x7, 0)
981 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_S 3
982 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_M MAKEMASK(0x3FF, 3)
983 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_S 13
984 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_M MAKEMASK(0x3, 13)
985 #define GLTCLAN_CQ_CNTX5(_CQ) (0x000F3000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
986 #define GLTCLAN_CQ_CNTX5_MAX_INDEX 511
987 #define GLTCLAN_CQ_CNTX5_TPH_EN_S 0
988 #define GLTCLAN_CQ_CNTX5_TPH_EN_M BIT(0)
989 #define GLTCLAN_CQ_CNTX5_CPU_ID_S 1
990 #define GLTCLAN_CQ_CNTX5_CPU_ID_M MAKEMASK(0xFF, 1)
991 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_S 9
992 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_M BIT(9)
993 #define GLTCLAN_CQ_CNTX6(_CQ) (0x000F3800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
994 #define GLTCLAN_CQ_CNTX6_MAX_INDEX 511
995 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_S 0
996 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
997 #define GLTCLAN_CQ_CNTX7(_CQ) (0x000F4000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
998 #define GLTCLAN_CQ_CNTX7_MAX_INDEX 511
999 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_S 0
1000 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1001 #define GLTCLAN_CQ_CNTX8(_CQ) (0x000F4800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1002 #define GLTCLAN_CQ_CNTX8_MAX_INDEX 511
1003 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_S 0
1004 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1005 #define GLTCLAN_CQ_CNTX9(_CQ) (0x000F5000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1006 #define GLTCLAN_CQ_CNTX9_MAX_INDEX 511
1007 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_S 0
1008 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1009 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
1010 #define QTX_COMM_DBELL_MAX_INDEX 16383
1011 #define QTX_COMM_DBELL_QTX_COMM_DBELL_S 0
1012 #define QTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
1013 #define QTX_COMM_DBLQ_CNTX(_i, _DBLQ) (0x002D0000 + ((_i) * 1024 + (_DBLQ) * 4)) /* _i=0...4, _DBLQ=0...255 */ /* Reset Source: CORER */
1014 #define QTX_COMM_DBLQ_CNTX_MAX_INDEX 4
1015 #define QTX_COMM_DBLQ_CNTX_DATA_S 0
1016 #define QTX_COMM_DBLQ_CNTX_DATA_M MAKEMASK(0xFFFFFFFF, 0)
1017 #define QTX_COMM_DBLQ_DBELL(_DBLQ) (0x002D1400 + ((_DBLQ) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1018 #define QTX_COMM_DBLQ_DBELL_MAX_INDEX 255
1019 #define QTX_COMM_DBLQ_DBELL_TAIL_S 0
1020 #define QTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
1021 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
1022 #define QTX_COMM_HEAD_MAX_INDEX 16383
1023 #define QTX_COMM_HEAD_HEAD_S 0
1024 #define QTX_COMM_HEAD_HEAD_M MAKEMASK(0x1FFF, 0)
1025 #define QTX_COMM_HEAD_RS_PENDING_S 16
1026 #define QTX_COMM_HEAD_RS_PENDING_M BIT(16)
1027 #define GL_FW_TOOL_ARQBAH 0x000801C0 /* Reset Source: EMPR */
1028 #define GL_FW_TOOL_ARQBAH_ARQBAH_S 0
1029 #define GL_FW_TOOL_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1030 #define GL_FW_TOOL_ARQBAL 0x000800C0 /* Reset Source: EMPR */
1031 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_S 0
1032 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1033 #define GL_FW_TOOL_ARQBAL_ARQBAL_S 6
1034 #define GL_FW_TOOL_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1035 #define GL_FW_TOOL_ARQH 0x000803C0 /* Reset Source: EMPR */
1036 #define GL_FW_TOOL_ARQH_ARQH_S 0
1037 #define GL_FW_TOOL_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1038 #define GL_FW_TOOL_ARQLEN 0x000802C0 /* Reset Source: EMPR */
1039 #define GL_FW_TOOL_ARQLEN_ARQLEN_S 0
1040 #define GL_FW_TOOL_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1041 #define GL_FW_TOOL_ARQLEN_ARQVFE_S 28
1042 #define GL_FW_TOOL_ARQLEN_ARQVFE_M BIT(28)
1043 #define GL_FW_TOOL_ARQLEN_ARQOVFL_S 29
1044 #define GL_FW_TOOL_ARQLEN_ARQOVFL_M BIT(29)
1045 #define GL_FW_TOOL_ARQLEN_ARQCRIT_S 30
1046 #define GL_FW_TOOL_ARQLEN_ARQCRIT_M BIT(30)
1047 #define GL_FW_TOOL_ARQLEN_ARQENABLE_S 31
1048 #define GL_FW_TOOL_ARQLEN_ARQENABLE_M BIT(31)
1049 #define GL_FW_TOOL_ARQT 0x000804C0 /* Reset Source: EMPR */
1050 #define GL_FW_TOOL_ARQT_ARQT_S 0
1051 #define GL_FW_TOOL_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1052 #define GL_FW_TOOL_ATQBAH 0x00080140 /* Reset Source: EMPR */
1053 #define GL_FW_TOOL_ATQBAH_ATQBAH_S 0
1054 #define GL_FW_TOOL_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1055 #define GL_FW_TOOL_ATQBAL 0x00080040 /* Reset Source: EMPR */
1056 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_S 0
1057 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1058 #define GL_FW_TOOL_ATQBAL_ATQBAL_S 6
1059 #define GL_FW_TOOL_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1060 #define GL_FW_TOOL_ATQH 0x00080340 /* Reset Source: EMPR */
1061 #define GL_FW_TOOL_ATQH_ATQH_S 0
1062 #define GL_FW_TOOL_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1063 #define GL_FW_TOOL_ATQLEN 0x00080240 /* Reset Source: EMPR */
1064 #define GL_FW_TOOL_ATQLEN_ATQLEN_S 0
1065 #define GL_FW_TOOL_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1066 #define GL_FW_TOOL_ATQLEN_ATQVFE_S 28
1067 #define GL_FW_TOOL_ATQLEN_ATQVFE_M BIT(28)
1068 #define GL_FW_TOOL_ATQLEN_ATQOVFL_S 29
1069 #define GL_FW_TOOL_ATQLEN_ATQOVFL_M BIT(29)
1070 #define GL_FW_TOOL_ATQLEN_ATQCRIT_S 30
1071 #define GL_FW_TOOL_ATQLEN_ATQCRIT_M BIT(30)
1072 #define GL_FW_TOOL_ATQLEN_ATQENABLE_S 31
1073 #define GL_FW_TOOL_ATQLEN_ATQENABLE_M BIT(31)
1074 #define GL_FW_TOOL_ATQT 0x00080440 /* Reset Source: EMPR */
1075 #define GL_FW_TOOL_ATQT_ATQT_S 0
1076 #define GL_FW_TOOL_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1077 #define GL_MBX_PASID 0x00231EC0 /* Reset Source: CORER */
1078 #define GL_MBX_PASID_PASID_MODE_S 0
1079 #define GL_MBX_PASID_PASID_MODE_M BIT(0)
1080 #define GL_MBX_PASID_PASID_MODE_VALID_S 1
1081 #define GL_MBX_PASID_PASID_MODE_VALID_M BIT(1)
1082 #define PF_FW_ARQBAH 0x00080180 /* Reset Source: EMPR */
1083 #define PF_FW_ARQBAH_ARQBAH_S 0
1084 #define PF_FW_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1085 #define PF_FW_ARQBAL 0x00080080 /* Reset Source: EMPR */
1086 #define PF_FW_ARQBAL_ARQBAL_LSB_S 0
1087 #define PF_FW_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1088 #define PF_FW_ARQBAL_ARQBAL_S 6
1089 #define PF_FW_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1090 #define PF_FW_ARQH 0x00080380 /* Reset Source: EMPR */
1091 #define PF_FW_ARQH_ARQH_S 0
1092 #define PF_FW_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1093 #define PF_FW_ARQLEN 0x00080280 /* Reset Source: EMPR */
1094 #define PF_FW_ARQLEN_ARQLEN_S 0
1095 #define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1096 #define PF_FW_ARQLEN_ARQVFE_S 28
1097 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
1098 #define PF_FW_ARQLEN_ARQOVFL_S 29
1099 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
1100 #define PF_FW_ARQLEN_ARQCRIT_S 30
1101 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
1102 #define PF_FW_ARQLEN_ARQENABLE_S 31
1103 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
1104 #define PF_FW_ARQT 0x00080480 /* Reset Source: EMPR */
1105 #define PF_FW_ARQT_ARQT_S 0
1106 #define PF_FW_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1107 #define PF_FW_ATQBAH 0x00080100 /* Reset Source: EMPR */
1108 #define PF_FW_ATQBAH_ATQBAH_S 0
1109 #define PF_FW_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1110 #define PF_FW_ATQBAL 0x00080000 /* Reset Source: EMPR */
1111 #define PF_FW_ATQBAL_ATQBAL_LSB_S 0
1112 #define PF_FW_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1113 #define PF_FW_ATQBAL_ATQBAL_S 6
1114 #define PF_FW_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1115 #define PF_FW_ATQH 0x00080300 /* Reset Source: EMPR */
1116 #define PF_FW_ATQH_ATQH_S 0
1117 #define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1118 #define PF_FW_ATQLEN 0x00080200 /* Reset Source: EMPR */
1119 #define PF_FW_ATQLEN_ATQLEN_S 0
1120 #define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1121 #define PF_FW_ATQLEN_ATQVFE_S 28
1122 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
1123 #define PF_FW_ATQLEN_ATQOVFL_S 29
1124 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
1125 #define PF_FW_ATQLEN_ATQCRIT_S 30
1126 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
1127 #define PF_FW_ATQLEN_ATQENABLE_S 31
1128 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
1129 #define PF_FW_ATQT 0x00080400 /* Reset Source: EMPR */
1130 #define PF_FW_ATQT_ATQT_S 0
1131 #define PF_FW_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1132 #define PF_MBX_ARQBAH 0x0022E400 /* Reset Source: CORER */
1133 #define PF_MBX_ARQBAH_ARQBAH_S 0
1134 #define PF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1135 #define PF_MBX_ARQBAL 0x0022E380 /* Reset Source: CORER */
1136 #define PF_MBX_ARQBAL_ARQBAL_LSB_S 0
1137 #define PF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1138 #define PF_MBX_ARQBAL_ARQBAL_S 6
1139 #define PF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1140 #define PF_MBX_ARQH 0x0022E500 /* Reset Source: CORER */
1141 #define PF_MBX_ARQH_ARQH_S 0
1142 #define PF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1143 #define PF_MBX_ARQLEN 0x0022E480 /* Reset Source: PFR */
1144 #define PF_MBX_ARQLEN_ARQLEN_S 0
1145 #define PF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1146 #define PF_MBX_ARQLEN_ARQVFE_S 28
1147 #define PF_MBX_ARQLEN_ARQVFE_M BIT(28)
1148 #define PF_MBX_ARQLEN_ARQOVFL_S 29
1149 #define PF_MBX_ARQLEN_ARQOVFL_M BIT(29)
1150 #define PF_MBX_ARQLEN_ARQCRIT_S 30
1151 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
1152 #define PF_MBX_ARQLEN_ARQENABLE_S 31
1153 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
1154 #define PF_MBX_ARQT 0x0022E580 /* Reset Source: CORER */
1155 #define PF_MBX_ARQT_ARQT_S 0
1156 #define PF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1157 #define PF_MBX_ATQBAH 0x0022E180 /* Reset Source: CORER */
1158 #define PF_MBX_ATQBAH_ATQBAH_S 0
1159 #define PF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1160 #define PF_MBX_ATQBAL 0x0022E100 /* Reset Source: CORER */
1161 #define PF_MBX_ATQBAL_ATQBAL_S 6
1162 #define PF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1163 #define PF_MBX_ATQH 0x0022E280 /* Reset Source: CORER */
1164 #define PF_MBX_ATQH_ATQH_S 0
1165 #define PF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1166 #define PF_MBX_ATQLEN 0x0022E200 /* Reset Source: PFR */
1167 #define PF_MBX_ATQLEN_ATQLEN_S 0
1168 #define PF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1169 #define PF_MBX_ATQLEN_ATQVFE_S 28
1170 #define PF_MBX_ATQLEN_ATQVFE_M BIT(28)
1171 #define PF_MBX_ATQLEN_ATQOVFL_S 29
1172 #define PF_MBX_ATQLEN_ATQOVFL_M BIT(29)
1173 #define PF_MBX_ATQLEN_ATQCRIT_S 30
1174 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
1175 #define PF_MBX_ATQLEN_ATQENABLE_S 31
1176 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
1177 #define PF_MBX_ATQT 0x0022E300 /* Reset Source: CORER */
1178 #define PF_MBX_ATQT_ATQT_S 0
1179 #define PF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1180 #define PF_SB_ARQBAH 0x0022FF00 /* Reset Source: CORER */
1181 #define PF_SB_ARQBAH_ARQBAH_S 0
1182 #define PF_SB_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1183 #define PF_SB_ARQBAL 0x0022FE80 /* Reset Source: CORER */
1184 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0
1185 #define PF_SB_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1186 #define PF_SB_ARQBAL_ARQBAL_S 6
1187 #define PF_SB_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1188 #define PF_SB_ARQH 0x00230000 /* Reset Source: CORER */
1189 #define PF_SB_ARQH_ARQH_S 0
1190 #define PF_SB_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1191 #define PF_SB_ARQLEN 0x0022FF80 /* Reset Source: PFR */
1192 #define PF_SB_ARQLEN_ARQLEN_S 0
1193 #define PF_SB_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1194 #define PF_SB_ARQLEN_ARQVFE_S 28
1195 #define PF_SB_ARQLEN_ARQVFE_M BIT(28)
1196 #define PF_SB_ARQLEN_ARQOVFL_S 29
1197 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
1198 #define PF_SB_ARQLEN_ARQCRIT_S 30
1199 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
1200 #define PF_SB_ARQLEN_ARQENABLE_S 31
1201 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
1202 #define PF_SB_ARQT 0x00230080 /* Reset Source: CORER */
1203 #define PF_SB_ARQT_ARQT_S 0
1204 #define PF_SB_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1205 #define PF_SB_ATQBAH 0x0022FC80 /* Reset Source: CORER */
1206 #define PF_SB_ATQBAH_ATQBAH_S 0
1207 #define PF_SB_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1208 #define PF_SB_ATQBAL 0x0022FC00 /* Reset Source: CORER */
1209 #define PF_SB_ATQBAL_ATQBAL_S 6
1210 #define PF_SB_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1211 #define PF_SB_ATQH 0x0022FD80 /* Reset Source: CORER */
1212 #define PF_SB_ATQH_ATQH_S 0
1213 #define PF_SB_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1214 #define PF_SB_ATQLEN 0x0022FD00 /* Reset Source: PFR */
1215 #define PF_SB_ATQLEN_ATQLEN_S 0
1216 #define PF_SB_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1217 #define PF_SB_ATQLEN_ATQVFE_S 28
1218 #define PF_SB_ATQLEN_ATQVFE_M BIT(28)
1219 #define PF_SB_ATQLEN_ATQOVFL_S 29
1220 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
1221 #define PF_SB_ATQLEN_ATQCRIT_S 30
1222 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
1223 #define PF_SB_ATQLEN_ATQENABLE_S 31
1224 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
1225 #define PF_SB_ATQT 0x0022FE00 /* Reset Source: CORER */
1226 #define PF_SB_ATQT_ATQT_S 0
1227 #define PF_SB_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1228 #define PF_SB_REM_DEV_CTL 0x002300F0 /* Reset Source: CORER */
1229 #define PF_SB_REM_DEV_CTL_DEST_EN_S 0
1230 #define PF_SB_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1231 #define PF0_FW_HLP_ARQBAH 0x000801C8 /* Reset Source: EMPR */
1232 #define PF0_FW_HLP_ARQBAH_ARQBAH_S 0
1233 #define PF0_FW_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1234 #define PF0_FW_HLP_ARQBAL 0x000800C8 /* Reset Source: EMPR */
1235 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_S 0
1236 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1237 #define PF0_FW_HLP_ARQBAL_ARQBAL_S 6
1238 #define PF0_FW_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1239 #define PF0_FW_HLP_ARQH 0x000803C8 /* Reset Source: EMPR */
1240 #define PF0_FW_HLP_ARQH_ARQH_S 0
1241 #define PF0_FW_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1242 #define PF0_FW_HLP_ARQLEN 0x000802C8 /* Reset Source: EMPR */
1243 #define PF0_FW_HLP_ARQLEN_ARQLEN_S 0
1244 #define PF0_FW_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1245 #define PF0_FW_HLP_ARQLEN_ARQVFE_S 28
1246 #define PF0_FW_HLP_ARQLEN_ARQVFE_M BIT(28)
1247 #define PF0_FW_HLP_ARQLEN_ARQOVFL_S 29
1248 #define PF0_FW_HLP_ARQLEN_ARQOVFL_M BIT(29)
1249 #define PF0_FW_HLP_ARQLEN_ARQCRIT_S 30
1250 #define PF0_FW_HLP_ARQLEN_ARQCRIT_M BIT(30)
1251 #define PF0_FW_HLP_ARQLEN_ARQENABLE_S 31
1252 #define PF0_FW_HLP_ARQLEN_ARQENABLE_M BIT(31)
1253 #define PF0_FW_HLP_ARQT 0x000804C8 /* Reset Source: EMPR */
1254 #define PF0_FW_HLP_ARQT_ARQT_S 0
1255 #define PF0_FW_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1256 #define PF0_FW_HLP_ATQBAH 0x00080148 /* Reset Source: EMPR */
1257 #define PF0_FW_HLP_ATQBAH_ATQBAH_S 0
1258 #define PF0_FW_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1259 #define PF0_FW_HLP_ATQBAL 0x00080048 /* Reset Source: EMPR */
1260 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_S 0
1261 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1262 #define PF0_FW_HLP_ATQBAL_ATQBAL_S 6
1263 #define PF0_FW_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1264 #define PF0_FW_HLP_ATQH 0x00080348 /* Reset Source: EMPR */
1265 #define PF0_FW_HLP_ATQH_ATQH_S 0
1266 #define PF0_FW_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1267 #define PF0_FW_HLP_ATQLEN 0x00080248 /* Reset Source: EMPR */
1268 #define PF0_FW_HLP_ATQLEN_ATQLEN_S 0
1269 #define PF0_FW_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1270 #define PF0_FW_HLP_ATQLEN_ATQVFE_S 28
1271 #define PF0_FW_HLP_ATQLEN_ATQVFE_M BIT(28)
1272 #define PF0_FW_HLP_ATQLEN_ATQOVFL_S 29
1273 #define PF0_FW_HLP_ATQLEN_ATQOVFL_M BIT(29)
1274 #define PF0_FW_HLP_ATQLEN_ATQCRIT_S 30
1275 #define PF0_FW_HLP_ATQLEN_ATQCRIT_M BIT(30)
1276 #define PF0_FW_HLP_ATQLEN_ATQENABLE_S 31
1277 #define PF0_FW_HLP_ATQLEN_ATQENABLE_M BIT(31)
1278 #define PF0_FW_HLP_ATQT 0x00080448 /* Reset Source: EMPR */
1279 #define PF0_FW_HLP_ATQT_ATQT_S 0
1280 #define PF0_FW_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1281 #define PF0_FW_PSM_ARQBAH 0x000801C4 /* Reset Source: EMPR */
1282 #define PF0_FW_PSM_ARQBAH_ARQBAH_S 0
1283 #define PF0_FW_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1284 #define PF0_FW_PSM_ARQBAL 0x000800C4 /* Reset Source: EMPR */
1285 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_S 0
1286 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1287 #define PF0_FW_PSM_ARQBAL_ARQBAL_S 6
1288 #define PF0_FW_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1289 #define PF0_FW_PSM_ARQH 0x000803C4 /* Reset Source: EMPR */
1290 #define PF0_FW_PSM_ARQH_ARQH_S 0
1291 #define PF0_FW_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1292 #define PF0_FW_PSM_ARQLEN 0x000802C4 /* Reset Source: EMPR */
1293 #define PF0_FW_PSM_ARQLEN_ARQLEN_S 0
1294 #define PF0_FW_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1295 #define PF0_FW_PSM_ARQLEN_ARQVFE_S 28
1296 #define PF0_FW_PSM_ARQLEN_ARQVFE_M BIT(28)
1297 #define PF0_FW_PSM_ARQLEN_ARQOVFL_S 29
1298 #define PF0_FW_PSM_ARQLEN_ARQOVFL_M BIT(29)
1299 #define PF0_FW_PSM_ARQLEN_ARQCRIT_S 30
1300 #define PF0_FW_PSM_ARQLEN_ARQCRIT_M BIT(30)
1301 #define PF0_FW_PSM_ARQLEN_ARQENABLE_S 31
1302 #define PF0_FW_PSM_ARQLEN_ARQENABLE_M BIT(31)
1303 #define PF0_FW_PSM_ARQT 0x000804C4 /* Reset Source: EMPR */
1304 #define PF0_FW_PSM_ARQT_ARQT_S 0
1305 #define PF0_FW_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1306 #define PF0_FW_PSM_ATQBAH 0x00080144 /* Reset Source: EMPR */
1307 #define PF0_FW_PSM_ATQBAH_ATQBAH_S 0
1308 #define PF0_FW_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1309 #define PF0_FW_PSM_ATQBAL 0x00080044 /* Reset Source: EMPR */
1310 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_S 0
1311 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1312 #define PF0_FW_PSM_ATQBAL_ATQBAL_S 6
1313 #define PF0_FW_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1314 #define PF0_FW_PSM_ATQH 0x00080344 /* Reset Source: EMPR */
1315 #define PF0_FW_PSM_ATQH_ATQH_S 0
1316 #define PF0_FW_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1317 #define PF0_FW_PSM_ATQLEN 0x00080244 /* Reset Source: EMPR */
1318 #define PF0_FW_PSM_ATQLEN_ATQLEN_S 0
1319 #define PF0_FW_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1320 #define PF0_FW_PSM_ATQLEN_ATQVFE_S 28
1321 #define PF0_FW_PSM_ATQLEN_ATQVFE_M BIT(28)
1322 #define PF0_FW_PSM_ATQLEN_ATQOVFL_S 29
1323 #define PF0_FW_PSM_ATQLEN_ATQOVFL_M BIT(29)
1324 #define PF0_FW_PSM_ATQLEN_ATQCRIT_S 30
1325 #define PF0_FW_PSM_ATQLEN_ATQCRIT_M BIT(30)
1326 #define PF0_FW_PSM_ATQLEN_ATQENABLE_S 31
1327 #define PF0_FW_PSM_ATQLEN_ATQENABLE_M BIT(31)
1328 #define PF0_FW_PSM_ATQT 0x00080444 /* Reset Source: EMPR */
1329 #define PF0_FW_PSM_ATQT_ATQT_S 0
1330 #define PF0_FW_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1331 #define PF0_MBX_CPM_ARQBAH 0x0022E5D8 /* Reset Source: CORER */
1332 #define PF0_MBX_CPM_ARQBAH_ARQBAH_S 0
1333 #define PF0_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1334 #define PF0_MBX_CPM_ARQBAL 0x0022E5D4 /* Reset Source: CORER */
1335 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1336 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1337 #define PF0_MBX_CPM_ARQBAL_ARQBAL_S 6
1338 #define PF0_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1339 #define PF0_MBX_CPM_ARQH 0x0022E5E0 /* Reset Source: CORER */
1340 #define PF0_MBX_CPM_ARQH_ARQH_S 0
1341 #define PF0_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1342 #define PF0_MBX_CPM_ARQLEN 0x0022E5DC /* Reset Source: PFR */
1343 #define PF0_MBX_CPM_ARQLEN_ARQLEN_S 0
1344 #define PF0_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1345 #define PF0_MBX_CPM_ARQLEN_ARQVFE_S 28
1346 #define PF0_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
1347 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_S 29
1348 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
1349 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_S 30
1350 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
1351 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_S 31
1352 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
1353 #define PF0_MBX_CPM_ARQT 0x0022E5E4 /* Reset Source: CORER */
1354 #define PF0_MBX_CPM_ARQT_ARQT_S 0
1355 #define PF0_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1356 #define PF0_MBX_CPM_ATQBAH 0x0022E5C4 /* Reset Source: CORER */
1357 #define PF0_MBX_CPM_ATQBAH_ATQBAH_S 0
1358 #define PF0_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1359 #define PF0_MBX_CPM_ATQBAL 0x0022E5C0 /* Reset Source: CORER */
1360 #define PF0_MBX_CPM_ATQBAL_ATQBAL_S 6
1361 #define PF0_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1362 #define PF0_MBX_CPM_ATQH 0x0022E5CC /* Reset Source: CORER */
1363 #define PF0_MBX_CPM_ATQH_ATQH_S 0
1364 #define PF0_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1365 #define PF0_MBX_CPM_ATQLEN 0x0022E5C8 /* Reset Source: PFR */
1366 #define PF0_MBX_CPM_ATQLEN_ATQLEN_S 0
1367 #define PF0_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1368 #define PF0_MBX_CPM_ATQLEN_ATQVFE_S 28
1369 #define PF0_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
1370 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_S 29
1371 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
1372 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_S 30
1373 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
1374 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_S 31
1375 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
1376 #define PF0_MBX_CPM_ATQT 0x0022E5D0 /* Reset Source: CORER */
1377 #define PF0_MBX_CPM_ATQT_ATQT_S 0
1378 #define PF0_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1379 #define PF0_MBX_HLP_ARQBAH 0x0022E600 /* Reset Source: CORER */
1380 #define PF0_MBX_HLP_ARQBAH_ARQBAH_S 0
1381 #define PF0_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1382 #define PF0_MBX_HLP_ARQBAL 0x0022E5FC /* Reset Source: CORER */
1383 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1384 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1385 #define PF0_MBX_HLP_ARQBAL_ARQBAL_S 6
1386 #define PF0_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1387 #define PF0_MBX_HLP_ARQH 0x0022E608 /* Reset Source: CORER */
1388 #define PF0_MBX_HLP_ARQH_ARQH_S 0
1389 #define PF0_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1390 #define PF0_MBX_HLP_ARQLEN 0x0022E604 /* Reset Source: PFR */
1391 #define PF0_MBX_HLP_ARQLEN_ARQLEN_S 0
1392 #define PF0_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1393 #define PF0_MBX_HLP_ARQLEN_ARQVFE_S 28
1394 #define PF0_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
1395 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_S 29
1396 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
1397 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_S 30
1398 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
1399 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_S 31
1400 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
1401 #define PF0_MBX_HLP_ARQT 0x0022E60C /* Reset Source: CORER */
1402 #define PF0_MBX_HLP_ARQT_ARQT_S 0
1403 #define PF0_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1404 #define PF0_MBX_HLP_ATQBAH 0x0022E5EC /* Reset Source: CORER */
1405 #define PF0_MBX_HLP_ATQBAH_ATQBAH_S 0
1406 #define PF0_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1407 #define PF0_MBX_HLP_ATQBAL 0x0022E5E8 /* Reset Source: CORER */
1408 #define PF0_MBX_HLP_ATQBAL_ATQBAL_S 6
1409 #define PF0_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1410 #define PF0_MBX_HLP_ATQH 0x0022E5F4 /* Reset Source: CORER */
1411 #define PF0_MBX_HLP_ATQH_ATQH_S 0
1412 #define PF0_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1413 #define PF0_MBX_HLP_ATQLEN 0x0022E5F0 /* Reset Source: PFR */
1414 #define PF0_MBX_HLP_ATQLEN_ATQLEN_S 0
1415 #define PF0_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1416 #define PF0_MBX_HLP_ATQLEN_ATQVFE_S 28
1417 #define PF0_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
1418 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_S 29
1419 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
1420 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_S 30
1421 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
1422 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_S 31
1423 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
1424 #define PF0_MBX_HLP_ATQT 0x0022E5F8 /* Reset Source: CORER */
1425 #define PF0_MBX_HLP_ATQT_ATQT_S 0
1426 #define PF0_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1427 #define PF0_MBX_PSM_ARQBAH 0x0022E628 /* Reset Source: CORER */
1428 #define PF0_MBX_PSM_ARQBAH_ARQBAH_S 0
1429 #define PF0_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1430 #define PF0_MBX_PSM_ARQBAL 0x0022E624 /* Reset Source: CORER */
1431 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1432 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1433 #define PF0_MBX_PSM_ARQBAL_ARQBAL_S 6
1434 #define PF0_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1435 #define PF0_MBX_PSM_ARQH 0x0022E630 /* Reset Source: CORER */
1436 #define PF0_MBX_PSM_ARQH_ARQH_S 0
1437 #define PF0_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1438 #define PF0_MBX_PSM_ARQLEN 0x0022E62C /* Reset Source: PFR */
1439 #define PF0_MBX_PSM_ARQLEN_ARQLEN_S 0
1440 #define PF0_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1441 #define PF0_MBX_PSM_ARQLEN_ARQVFE_S 28
1442 #define PF0_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
1443 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_S 29
1444 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
1445 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_S 30
1446 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
1447 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_S 31
1448 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
1449 #define PF0_MBX_PSM_ARQT 0x0022E634 /* Reset Source: CORER */
1450 #define PF0_MBX_PSM_ARQT_ARQT_S 0
1451 #define PF0_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1452 #define PF0_MBX_PSM_ATQBAH 0x0022E614 /* Reset Source: CORER */
1453 #define PF0_MBX_PSM_ATQBAH_ATQBAH_S 0
1454 #define PF0_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1455 #define PF0_MBX_PSM_ATQBAL 0x0022E610 /* Reset Source: CORER */
1456 #define PF0_MBX_PSM_ATQBAL_ATQBAL_S 6
1457 #define PF0_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1458 #define PF0_MBX_PSM_ATQH 0x0022E61C /* Reset Source: CORER */
1459 #define PF0_MBX_PSM_ATQH_ATQH_S 0
1460 #define PF0_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1461 #define PF0_MBX_PSM_ATQLEN 0x0022E618 /* Reset Source: PFR */
1462 #define PF0_MBX_PSM_ATQLEN_ATQLEN_S 0
1463 #define PF0_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1464 #define PF0_MBX_PSM_ATQLEN_ATQVFE_S 28
1465 #define PF0_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
1466 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_S 29
1467 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
1468 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_S 30
1469 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
1470 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_S 31
1471 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
1472 #define PF0_MBX_PSM_ATQT 0x0022E620 /* Reset Source: CORER */
1473 #define PF0_MBX_PSM_ATQT_ATQT_S 0
1474 #define PF0_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1475 #define PF0_SB_CPM_ARQBAH 0x0022E650 /* Reset Source: CORER */
1476 #define PF0_SB_CPM_ARQBAH_ARQBAH_S 0
1477 #define PF0_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1478 #define PF0_SB_CPM_ARQBAL 0x0022E64C /* Reset Source: CORER */
1479 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1480 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1481 #define PF0_SB_CPM_ARQBAL_ARQBAL_S 6
1482 #define PF0_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1483 #define PF0_SB_CPM_ARQH 0x0022E658 /* Reset Source: CORER */
1484 #define PF0_SB_CPM_ARQH_ARQH_S 0
1485 #define PF0_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1486 #define PF0_SB_CPM_ARQLEN 0x0022E654 /* Reset Source: PFR */
1487 #define PF0_SB_CPM_ARQLEN_ARQLEN_S 0
1488 #define PF0_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1489 #define PF0_SB_CPM_ARQLEN_ARQVFE_S 28
1490 #define PF0_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
1491 #define PF0_SB_CPM_ARQLEN_ARQOVFL_S 29
1492 #define PF0_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
1493 #define PF0_SB_CPM_ARQLEN_ARQCRIT_S 30
1494 #define PF0_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
1495 #define PF0_SB_CPM_ARQLEN_ARQENABLE_S 31
1496 #define PF0_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
1497 #define PF0_SB_CPM_ARQT 0x0022E65C /* Reset Source: CORER */
1498 #define PF0_SB_CPM_ARQT_ARQT_S 0
1499 #define PF0_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1500 #define PF0_SB_CPM_ATQBAH 0x0022E63C /* Reset Source: CORER */
1501 #define PF0_SB_CPM_ATQBAH_ATQBAH_S 0
1502 #define PF0_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1503 #define PF0_SB_CPM_ATQBAL 0x0022E638 /* Reset Source: CORER */
1504 #define PF0_SB_CPM_ATQBAL_ATQBAL_S 6
1505 #define PF0_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1506 #define PF0_SB_CPM_ATQH 0x0022E644 /* Reset Source: CORER */
1507 #define PF0_SB_CPM_ATQH_ATQH_S 0
1508 #define PF0_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1509 #define PF0_SB_CPM_ATQLEN 0x0022E640 /* Reset Source: PFR */
1510 #define PF0_SB_CPM_ATQLEN_ATQLEN_S 0
1511 #define PF0_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1512 #define PF0_SB_CPM_ATQLEN_ATQVFE_S 28
1513 #define PF0_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
1514 #define PF0_SB_CPM_ATQLEN_ATQOVFL_S 29
1515 #define PF0_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
1516 #define PF0_SB_CPM_ATQLEN_ATQCRIT_S 30
1517 #define PF0_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
1518 #define PF0_SB_CPM_ATQLEN_ATQENABLE_S 31
1519 #define PF0_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
1520 #define PF0_SB_CPM_ATQT 0x0022E648 /* Reset Source: CORER */
1521 #define PF0_SB_CPM_ATQT_ATQT_S 0
1522 #define PF0_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1523 #define PF0_SB_CPM_REM_DEV_CTL 0x002300F4 /* Reset Source: CORER */
1524 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1525 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1526 #define PF0_SB_HLP_ARQBAH 0x002300D8 /* Reset Source: CORER */
1527 #define PF0_SB_HLP_ARQBAH_ARQBAH_S 0
1528 #define PF0_SB_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1529 #define PF0_SB_HLP_ARQBAL 0x002300D4 /* Reset Source: CORER */
1530 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_S 0
1531 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1532 #define PF0_SB_HLP_ARQBAL_ARQBAL_S 6
1533 #define PF0_SB_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1534 #define PF0_SB_HLP_ARQH 0x002300E0 /* Reset Source: CORER */
1535 #define PF0_SB_HLP_ARQH_ARQH_S 0
1536 #define PF0_SB_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1537 #define PF0_SB_HLP_ARQLEN 0x002300DC /* Reset Source: PFR */
1538 #define PF0_SB_HLP_ARQLEN_ARQLEN_S 0
1539 #define PF0_SB_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1540 #define PF0_SB_HLP_ARQLEN_ARQVFE_S 28
1541 #define PF0_SB_HLP_ARQLEN_ARQVFE_M BIT(28)
1542 #define PF0_SB_HLP_ARQLEN_ARQOVFL_S 29
1543 #define PF0_SB_HLP_ARQLEN_ARQOVFL_M BIT(29)
1544 #define PF0_SB_HLP_ARQLEN_ARQCRIT_S 30
1545 #define PF0_SB_HLP_ARQLEN_ARQCRIT_M BIT(30)
1546 #define PF0_SB_HLP_ARQLEN_ARQENABLE_S 31
1547 #define PF0_SB_HLP_ARQLEN_ARQENABLE_M BIT(31)
1548 #define PF0_SB_HLP_ARQT 0x002300E4 /* Reset Source: CORER */
1549 #define PF0_SB_HLP_ARQT_ARQT_S 0
1550 #define PF0_SB_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1551 #define PF0_SB_HLP_ATQBAH 0x002300C4 /* Reset Source: CORER */
1552 #define PF0_SB_HLP_ATQBAH_ATQBAH_S 0
1553 #define PF0_SB_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1554 #define PF0_SB_HLP_ATQBAL 0x002300C0 /* Reset Source: CORER */
1555 #define PF0_SB_HLP_ATQBAL_ATQBAL_S 6
1556 #define PF0_SB_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1557 #define PF0_SB_HLP_ATQH 0x002300CC /* Reset Source: CORER */
1558 #define PF0_SB_HLP_ATQH_ATQH_S 0
1559 #define PF0_SB_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1560 #define PF0_SB_HLP_ATQLEN 0x002300C8 /* Reset Source: PFR */
1561 #define PF0_SB_HLP_ATQLEN_ATQLEN_S 0
1562 #define PF0_SB_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1563 #define PF0_SB_HLP_ATQLEN_ATQVFE_S 28
1564 #define PF0_SB_HLP_ATQLEN_ATQVFE_M BIT(28)
1565 #define PF0_SB_HLP_ATQLEN_ATQOVFL_S 29
1566 #define PF0_SB_HLP_ATQLEN_ATQOVFL_M BIT(29)
1567 #define PF0_SB_HLP_ATQLEN_ATQCRIT_S 30
1568 #define PF0_SB_HLP_ATQLEN_ATQCRIT_M BIT(30)
1569 #define PF0_SB_HLP_ATQLEN_ATQENABLE_S 31
1570 #define PF0_SB_HLP_ATQLEN_ATQENABLE_M BIT(31)
1571 #define PF0_SB_HLP_ATQT 0x002300D0 /* Reset Source: CORER */
1572 #define PF0_SB_HLP_ATQT_ATQT_S 0
1573 #define PF0_SB_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1574 #define PF0_SB_HLP_REM_DEV_CTL 0x002300E8 /* Reset Source: CORER */
1575 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_S 0
1576 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1577 #define SB_REM_DEV_DEST(_i) (0x002300F8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
1578 #define SB_REM_DEV_DEST_MAX_INDEX 7
1579 #define SB_REM_DEV_DEST_DEST_S 0
1580 #define SB_REM_DEV_DEST_DEST_M MAKEMASK(0xF, 0)
1581 #define SB_REM_DEV_DEST_DEST_VALID_S 31
1582 #define SB_REM_DEV_DEST_DEST_VALID_M BIT(31)
1583 #define VF_MBX_ARQBAH(_VF) (0x0022B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1584 #define VF_MBX_ARQBAH_MAX_INDEX 255
1585 #define VF_MBX_ARQBAH_ARQBAH_S 0
1586 #define VF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1587 #define VF_MBX_ARQBAL(_VF) (0x0022B400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1588 #define VF_MBX_ARQBAL_MAX_INDEX 255
1589 #define VF_MBX_ARQBAL_ARQBAL_LSB_S 0
1590 #define VF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1591 #define VF_MBX_ARQBAL_ARQBAL_S 6
1592 #define VF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1593 #define VF_MBX_ARQH(_VF) (0x0022C000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1594 #define VF_MBX_ARQH_MAX_INDEX 255
1595 #define VF_MBX_ARQH_ARQH_S 0
1596 #define VF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1597 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1598 #define VF_MBX_ARQLEN_MAX_INDEX 255
1599 #define VF_MBX_ARQLEN_ARQLEN_S 0
1600 #define VF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1601 #define VF_MBX_ARQLEN_ARQVFE_S 28
1602 #define VF_MBX_ARQLEN_ARQVFE_M BIT(28)
1603 #define VF_MBX_ARQLEN_ARQOVFL_S 29
1604 #define VF_MBX_ARQLEN_ARQOVFL_M BIT(29)
1605 #define VF_MBX_ARQLEN_ARQCRIT_S 30
1606 #define VF_MBX_ARQLEN_ARQCRIT_M BIT(30)
1607 #define VF_MBX_ARQLEN_ARQENABLE_S 31
1608 #define VF_MBX_ARQLEN_ARQENABLE_M BIT(31)
1609 #define VF_MBX_ARQT(_VF) (0x0022C400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1610 #define VF_MBX_ARQT_MAX_INDEX 255
1611 #define VF_MBX_ARQT_ARQT_S 0
1612 #define VF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1613 #define VF_MBX_ATQBAH(_VF) (0x0022A400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1614 #define VF_MBX_ATQBAH_MAX_INDEX 255
1615 #define VF_MBX_ATQBAH_ATQBAH_S 0
1616 #define VF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1617 #define VF_MBX_ATQBAL(_VF) (0x0022A000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1618 #define VF_MBX_ATQBAL_MAX_INDEX 255
1619 #define VF_MBX_ATQBAL_ATQBAL_S 6
1620 #define VF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1621 #define VF_MBX_ATQH(_VF) (0x0022AC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1622 #define VF_MBX_ATQH_MAX_INDEX 255
1623 #define VF_MBX_ATQH_ATQH_S 0
1624 #define VF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1625 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1626 #define VF_MBX_ATQLEN_MAX_INDEX 255
1627 #define VF_MBX_ATQLEN_ATQLEN_S 0
1628 #define VF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1629 #define VF_MBX_ATQLEN_ATQVFE_S 28
1630 #define VF_MBX_ATQLEN_ATQVFE_M BIT(28)
1631 #define VF_MBX_ATQLEN_ATQOVFL_S 29
1632 #define VF_MBX_ATQLEN_ATQOVFL_M BIT(29)
1633 #define VF_MBX_ATQLEN_ATQCRIT_S 30
1634 #define VF_MBX_ATQLEN_ATQCRIT_M BIT(30)
1635 #define VF_MBX_ATQLEN_ATQENABLE_S 31
1636 #define VF_MBX_ATQLEN_ATQENABLE_M BIT(31)
1637 #define VF_MBX_ATQT(_VF) (0x0022B000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1638 #define VF_MBX_ATQT_MAX_INDEX 255
1639 #define VF_MBX_ATQT_ATQT_S 0
1640 #define VF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1641 #define VF_MBX_CPM_ARQBAH(_VF128) (0x0022D400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1642 #define VF_MBX_CPM_ARQBAH_MAX_INDEX 127
1643 #define VF_MBX_CPM_ARQBAH_ARQBAH_S 0
1644 #define VF_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1645 #define VF_MBX_CPM_ARQBAL(_VF128) (0x0022D200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1646 #define VF_MBX_CPM_ARQBAL_MAX_INDEX 127
1647 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1648 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1649 #define VF_MBX_CPM_ARQBAL_ARQBAL_S 6
1650 #define VF_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1651 #define VF_MBX_CPM_ARQH(_VF128) (0x0022D800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1652 #define VF_MBX_CPM_ARQH_MAX_INDEX 127
1653 #define VF_MBX_CPM_ARQH_ARQH_S 0
1654 #define VF_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1655 #define VF_MBX_CPM_ARQLEN(_VF128) (0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1656 #define VF_MBX_CPM_ARQLEN_MAX_INDEX 127
1657 #define VF_MBX_CPM_ARQLEN_ARQLEN_S 0
1658 #define VF_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1659 #define VF_MBX_CPM_ARQLEN_ARQVFE_S 28
1660 #define VF_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
1661 #define VF_MBX_CPM_ARQLEN_ARQOVFL_S 29
1662 #define VF_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
1663 #define VF_MBX_CPM_ARQLEN_ARQCRIT_S 30
1664 #define VF_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
1665 #define VF_MBX_CPM_ARQLEN_ARQENABLE_S 31
1666 #define VF_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
1667 #define VF_MBX_CPM_ARQT(_VF128) (0x0022DA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1668 #define VF_MBX_CPM_ARQT_MAX_INDEX 127
1669 #define VF_MBX_CPM_ARQT_ARQT_S 0
1670 #define VF_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1671 #define VF_MBX_CPM_ATQBAH(_VF128) (0x0022CA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1672 #define VF_MBX_CPM_ATQBAH_MAX_INDEX 127
1673 #define VF_MBX_CPM_ATQBAH_ATQBAH_S 0
1674 #define VF_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1675 #define VF_MBX_CPM_ATQBAL(_VF128) (0x0022C800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1676 #define VF_MBX_CPM_ATQBAL_MAX_INDEX 127
1677 #define VF_MBX_CPM_ATQBAL_ATQBAL_S 6
1678 #define VF_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1679 #define VF_MBX_CPM_ATQH(_VF128) (0x0022CE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1680 #define VF_MBX_CPM_ATQH_MAX_INDEX 127
1681 #define VF_MBX_CPM_ATQH_ATQH_S 0
1682 #define VF_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1683 #define VF_MBX_CPM_ATQLEN(_VF128) (0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1684 #define VF_MBX_CPM_ATQLEN_MAX_INDEX 127
1685 #define VF_MBX_CPM_ATQLEN_ATQLEN_S 0
1686 #define VF_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1687 #define VF_MBX_CPM_ATQLEN_ATQVFE_S 28
1688 #define VF_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
1689 #define VF_MBX_CPM_ATQLEN_ATQOVFL_S 29
1690 #define VF_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
1691 #define VF_MBX_CPM_ATQLEN_ATQCRIT_S 30
1692 #define VF_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
1693 #define VF_MBX_CPM_ATQLEN_ATQENABLE_S 31
1694 #define VF_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
1695 #define VF_MBX_CPM_ATQT(_VF128) (0x0022D000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1696 #define VF_MBX_CPM_ATQT_MAX_INDEX 127
1697 #define VF_MBX_CPM_ATQT_ATQT_S 0
1698 #define VF_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1699 #define VF_MBX_HLP_ARQBAH(_VF16) (0x0022DD80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1700 #define VF_MBX_HLP_ARQBAH_MAX_INDEX 15
1701 #define VF_MBX_HLP_ARQBAH_ARQBAH_S 0
1702 #define VF_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1703 #define VF_MBX_HLP_ARQBAL(_VF16) (0x0022DD40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1704 #define VF_MBX_HLP_ARQBAL_MAX_INDEX 15
1705 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1706 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1707 #define VF_MBX_HLP_ARQBAL_ARQBAL_S 6
1708 #define VF_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1709 #define VF_MBX_HLP_ARQH(_VF16) (0x0022DE00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1710 #define VF_MBX_HLP_ARQH_MAX_INDEX 15
1711 #define VF_MBX_HLP_ARQH_ARQH_S 0
1712 #define VF_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1713 #define VF_MBX_HLP_ARQLEN(_VF16) (0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1714 #define VF_MBX_HLP_ARQLEN_MAX_INDEX 15
1715 #define VF_MBX_HLP_ARQLEN_ARQLEN_S 0
1716 #define VF_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1717 #define VF_MBX_HLP_ARQLEN_ARQVFE_S 28
1718 #define VF_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
1719 #define VF_MBX_HLP_ARQLEN_ARQOVFL_S 29
1720 #define VF_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
1721 #define VF_MBX_HLP_ARQLEN_ARQCRIT_S 30
1722 #define VF_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
1723 #define VF_MBX_HLP_ARQLEN_ARQENABLE_S 31
1724 #define VF_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
1725 #define VF_MBX_HLP_ARQT(_VF16) (0x0022DE40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1726 #define VF_MBX_HLP_ARQT_MAX_INDEX 15
1727 #define VF_MBX_HLP_ARQT_ARQT_S 0
1728 #define VF_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1729 #define VF_MBX_HLP_ATQBAH(_VF16) (0x0022DC40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1730 #define VF_MBX_HLP_ATQBAH_MAX_INDEX 15
1731 #define VF_MBX_HLP_ATQBAH_ATQBAH_S 0
1732 #define VF_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1733 #define VF_MBX_HLP_ATQBAL(_VF16) (0x0022DC00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1734 #define VF_MBX_HLP_ATQBAL_MAX_INDEX 15
1735 #define VF_MBX_HLP_ATQBAL_ATQBAL_S 6
1736 #define VF_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1737 #define VF_MBX_HLP_ATQH(_VF16) (0x0022DCC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1738 #define VF_MBX_HLP_ATQH_MAX_INDEX 15
1739 #define VF_MBX_HLP_ATQH_ATQH_S 0
1740 #define VF_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1741 #define VF_MBX_HLP_ATQLEN(_VF16) (0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1742 #define VF_MBX_HLP_ATQLEN_MAX_INDEX 15
1743 #define VF_MBX_HLP_ATQLEN_ATQLEN_S 0
1744 #define VF_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1745 #define VF_MBX_HLP_ATQLEN_ATQVFE_S 28
1746 #define VF_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
1747 #define VF_MBX_HLP_ATQLEN_ATQOVFL_S 29
1748 #define VF_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
1749 #define VF_MBX_HLP_ATQLEN_ATQCRIT_S 30
1750 #define VF_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
1751 #define VF_MBX_HLP_ATQLEN_ATQENABLE_S 31
1752 #define VF_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
1753 #define VF_MBX_HLP_ATQT(_VF16) (0x0022DD00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1754 #define VF_MBX_HLP_ATQT_MAX_INDEX 15
1755 #define VF_MBX_HLP_ATQT_ATQT_S 0
1756 #define VF_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1757 #define VF_MBX_PSM_ARQBAH(_VF16) (0x0022E000 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1758 #define VF_MBX_PSM_ARQBAH_MAX_INDEX 15
1759 #define VF_MBX_PSM_ARQBAH_ARQBAH_S 0
1760 #define VF_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1761 #define VF_MBX_PSM_ARQBAL(_VF16) (0x0022DFC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1762 #define VF_MBX_PSM_ARQBAL_MAX_INDEX 15
1763 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1764 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1765 #define VF_MBX_PSM_ARQBAL_ARQBAL_S 6
1766 #define VF_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1767 #define VF_MBX_PSM_ARQH(_VF16) (0x0022E080 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1768 #define VF_MBX_PSM_ARQH_MAX_INDEX 15
1769 #define VF_MBX_PSM_ARQH_ARQH_S 0
1770 #define VF_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1771 #define VF_MBX_PSM_ARQLEN(_VF16) (0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1772 #define VF_MBX_PSM_ARQLEN_MAX_INDEX 15
1773 #define VF_MBX_PSM_ARQLEN_ARQLEN_S 0
1774 #define VF_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1775 #define VF_MBX_PSM_ARQLEN_ARQVFE_S 28
1776 #define VF_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
1777 #define VF_MBX_PSM_ARQLEN_ARQOVFL_S 29
1778 #define VF_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
1779 #define VF_MBX_PSM_ARQLEN_ARQCRIT_S 30
1780 #define VF_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
1781 #define VF_MBX_PSM_ARQLEN_ARQENABLE_S 31
1782 #define VF_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
1783 #define VF_MBX_PSM_ARQT(_VF16) (0x0022E0C0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1784 #define VF_MBX_PSM_ARQT_MAX_INDEX 15
1785 #define VF_MBX_PSM_ARQT_ARQT_S 0
1786 #define VF_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1787 #define VF_MBX_PSM_ATQBAH(_VF16) (0x0022DEC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1788 #define VF_MBX_PSM_ATQBAH_MAX_INDEX 15
1789 #define VF_MBX_PSM_ATQBAH_ATQBAH_S 0
1790 #define VF_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1791 #define VF_MBX_PSM_ATQBAL(_VF16) (0x0022DE80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1792 #define VF_MBX_PSM_ATQBAL_MAX_INDEX 15
1793 #define VF_MBX_PSM_ATQBAL_ATQBAL_S 6
1794 #define VF_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1795 #define VF_MBX_PSM_ATQH(_VF16) (0x0022DF40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1796 #define VF_MBX_PSM_ATQH_MAX_INDEX 15
1797 #define VF_MBX_PSM_ATQH_ATQH_S 0
1798 #define VF_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1799 #define VF_MBX_PSM_ATQLEN(_VF16) (0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1800 #define VF_MBX_PSM_ATQLEN_MAX_INDEX 15
1801 #define VF_MBX_PSM_ATQLEN_ATQLEN_S 0
1802 #define VF_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1803 #define VF_MBX_PSM_ATQLEN_ATQVFE_S 28
1804 #define VF_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
1805 #define VF_MBX_PSM_ATQLEN_ATQOVFL_S 29
1806 #define VF_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
1807 #define VF_MBX_PSM_ATQLEN_ATQCRIT_S 30
1808 #define VF_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
1809 #define VF_MBX_PSM_ATQLEN_ATQENABLE_S 31
1810 #define VF_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
1811 #define VF_MBX_PSM_ATQT(_VF16) (0x0022DF80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1812 #define VF_MBX_PSM_ATQT_MAX_INDEX 15
1813 #define VF_MBX_PSM_ATQT_ATQT_S 0
1814 #define VF_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1815 #define VF_SB_CPM_ARQBAH(_VF128) (0x0022F400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1816 #define VF_SB_CPM_ARQBAH_MAX_INDEX 127
1817 #define VF_SB_CPM_ARQBAH_ARQBAH_S 0
1818 #define VF_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1819 #define VF_SB_CPM_ARQBAL(_VF128) (0x0022F200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1820 #define VF_SB_CPM_ARQBAL_MAX_INDEX 127
1821 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1822 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1823 #define VF_SB_CPM_ARQBAL_ARQBAL_S 6
1824 #define VF_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1825 #define VF_SB_CPM_ARQH(_VF128) (0x0022F800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1826 #define VF_SB_CPM_ARQH_MAX_INDEX 127
1827 #define VF_SB_CPM_ARQH_ARQH_S 0
1828 #define VF_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1829 #define VF_SB_CPM_ARQLEN(_VF128) (0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1830 #define VF_SB_CPM_ARQLEN_MAX_INDEX 127
1831 #define VF_SB_CPM_ARQLEN_ARQLEN_S 0
1832 #define VF_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1833 #define VF_SB_CPM_ARQLEN_ARQVFE_S 28
1834 #define VF_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
1835 #define VF_SB_CPM_ARQLEN_ARQOVFL_S 29
1836 #define VF_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
1837 #define VF_SB_CPM_ARQLEN_ARQCRIT_S 30
1838 #define VF_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
1839 #define VF_SB_CPM_ARQLEN_ARQENABLE_S 31
1840 #define VF_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
1841 #define VF_SB_CPM_ARQT(_VF128) (0x0022FA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1842 #define VF_SB_CPM_ARQT_MAX_INDEX 127
1843 #define VF_SB_CPM_ARQT_ARQT_S 0
1844 #define VF_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1845 #define VF_SB_CPM_ATQBAH(_VF128) (0x0022EA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1846 #define VF_SB_CPM_ATQBAH_MAX_INDEX 127
1847 #define VF_SB_CPM_ATQBAH_ATQBAH_S 0
1848 #define VF_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1849 #define VF_SB_CPM_ATQBAL(_VF128) (0x0022E800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1850 #define VF_SB_CPM_ATQBAL_MAX_INDEX 127
1851 #define VF_SB_CPM_ATQBAL_ATQBAL_S 6
1852 #define VF_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1853 #define VF_SB_CPM_ATQH(_VF128) (0x0022EE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1854 #define VF_SB_CPM_ATQH_MAX_INDEX 127
1855 #define VF_SB_CPM_ATQH_ATQH_S 0
1856 #define VF_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1857 #define VF_SB_CPM_ATQLEN(_VF128) (0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1858 #define VF_SB_CPM_ATQLEN_MAX_INDEX 127
1859 #define VF_SB_CPM_ATQLEN_ATQLEN_S 0
1860 #define VF_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1861 #define VF_SB_CPM_ATQLEN_ATQVFE_S 28
1862 #define VF_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
1863 #define VF_SB_CPM_ATQLEN_ATQOVFL_S 29
1864 #define VF_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
1865 #define VF_SB_CPM_ATQLEN_ATQCRIT_S 30
1866 #define VF_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
1867 #define VF_SB_CPM_ATQLEN_ATQENABLE_S 31
1868 #define VF_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
1869 #define VF_SB_CPM_ATQT(_VF128) (0x0022F000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1870 #define VF_SB_CPM_ATQT_MAX_INDEX 127
1871 #define VF_SB_CPM_ATQT_ATQT_S 0
1872 #define VF_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1873 #define VF_SB_CPM_REM_DEV_CTL 0x002300EC /* Reset Source: CORER */
1874 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1875 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1876 #define VP_MBX_CPM_PF_VF_CTRL(_VP128) (0x00231800 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1877 #define VP_MBX_CPM_PF_VF_CTRL_MAX_INDEX 127
1878 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1879 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1880 #define VP_MBX_HLP_PF_VF_CTRL(_VP16) (0x00231A00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1881 #define VP_MBX_HLP_PF_VF_CTRL_MAX_INDEX 15
1882 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_S 0
1883 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1884 #define VP_MBX_PF_VF_CTRL(_VSI) (0x00230800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
1885 #define VP_MBX_PF_VF_CTRL_MAX_INDEX 767
1886 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_S 0
1887 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1888 #define VP_MBX_PSM_PF_VF_CTRL(_VP16) (0x00231A40 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1889 #define VP_MBX_PSM_PF_VF_CTRL_MAX_INDEX 15
1890 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_S 0
1891 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1892 #define VP_SB_CPM_PF_VF_CTRL(_VP128) (0x00231C00 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1893 #define VP_SB_CPM_PF_VF_CTRL_MAX_INDEX 127
1894 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1895 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1896 #define GL_DCB_TDSCP2TC_BLOCK_DIS 0x00049218 /* Reset Source: CORER */
1897 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_S 0
1898 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0)
1899 #define GL_DCB_TDSCP2TC_BLOCK_IPV4(_i) (0x00049018 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1900 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_MAX_INDEX 63
1901 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_S 0
1902 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1903 #define GL_DCB_TDSCP2TC_BLOCK_IPV6(_i) (0x00049118 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1904 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_MAX_INDEX 63
1905 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_S 0
1906 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1907 #define GLDCB_GENC 0x00083044 /* Reset Source: CORER */
1908 #define GLDCB_GENC_PCIRTT_S 0
1909 #define GLDCB_GENC_PCIRTT_M MAKEMASK(0xFFFF, 0)
1910 #define GLDCB_PRS_RETSTCC(_i) (0x002000B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1911 #define GLDCB_PRS_RETSTCC_MAX_INDEX 31
1912 #define GLDCB_PRS_RETSTCC_BWSHARE_S 0
1913 #define GLDCB_PRS_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1914 #define GLDCB_PRS_RETSTCC_ETSTC_S 31
1915 #define GLDCB_PRS_RETSTCC_ETSTC_M BIT(31)
1916 #define GLDCB_PRS_RSPMC 0x00200160 /* Reset Source: CORER */
1917 #define GLDCB_PRS_RSPMC_RSPM_S 0
1918 #define GLDCB_PRS_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
1919 #define GLDCB_PRS_RSPMC_RPM_MODE_S 8
1920 #define GLDCB_PRS_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
1921 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_S 10
1922 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
1923 #define GLDCB_PRS_RSPMC_PFCTIMER_S 14
1924 #define GLDCB_PRS_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
1925 #define GLDCB_PRS_RSPMC_RPM_DIS_S 31
1926 #define GLDCB_PRS_RSPMC_RPM_DIS_M BIT(31)
1927 #define GLDCB_RETSTCC(_i) (0x00122140 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1928 #define GLDCB_RETSTCC_MAX_INDEX 31
1929 #define GLDCB_RETSTCC_BWSHARE_S 0
1930 #define GLDCB_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1931 #define GLDCB_RETSTCC_ETSTC_S 31
1932 #define GLDCB_RETSTCC_ETSTC_M BIT(31)
1933 #define GLDCB_RETSTCS(_i) (0x001221C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1934 #define GLDCB_RETSTCS_MAX_INDEX 31
1935 #define GLDCB_RETSTCS_CREDITS_S 0
1936 #define GLDCB_RETSTCS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
1937 #define GLDCB_RTC2PFC_RCB 0x00122100 /* Reset Source: CORER */
1938 #define GLDCB_RTC2PFC_RCB_TC2PFC_S 0
1939 #define GLDCB_RTC2PFC_RCB_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1940 #define GLDCB_SWT_RETSTCC(_i) (0x0020A040 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1941 #define GLDCB_SWT_RETSTCC_MAX_INDEX 31
1942 #define GLDCB_SWT_RETSTCC_BWSHARE_S 0
1943 #define GLDCB_SWT_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1944 #define GLDCB_SWT_RETSTCC_ETSTC_S 31
1945 #define GLDCB_SWT_RETSTCC_ETSTC_M BIT(31)
1946 #define GLDCB_TC2PFC 0x001D2694 /* Reset Source: CORER */
1947 #define GLDCB_TC2PFC_TC2PFC_S 0
1948 #define GLDCB_TC2PFC_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1949 #define GLDCB_TCB_MNG_SP 0x000AE12C /* Reset Source: CORER */
1950 #define GLDCB_TCB_MNG_SP_MNG_SP_S 0
1951 #define GLDCB_TCB_MNG_SP_MNG_SP_M BIT(0)
1952 #define GLDCB_TCB_TCLL_CFG 0x000AE134 /* Reset Source: CORER */
1953 #define GLDCB_TCB_TCLL_CFG_LLTC_S 0
1954 #define GLDCB_TCB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
1955 #define GLDCB_TCB_WB_SP 0x000AE310 /* Reset Source: CORER */
1956 #define GLDCB_TCB_WB_SP_WB_SP_S 0
1957 #define GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
1958 #define GLDCB_TCUPM_IMM_EN 0x000BC824 /* Reset Source: CORER */
1959 #define GLDCB_TCUPM_IMM_EN_IMM_EN_S 0
1960 #define GLDCB_TCUPM_IMM_EN_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1961 #define GLDCB_TCUPM_LEGACY_TC 0x000BC828 /* Reset Source: CORER */
1962 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_S 0
1963 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_M MAKEMASK(0xFFFFFFFF, 0)
1964 #define GLDCB_TCUPM_NO_EXCEED_DIS 0x000BC830 /* Reset Source: CORER */
1965 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_S 0
1966 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0)
1967 #define GLDCB_TCUPM_WB_DIS 0x000BC834 /* Reset Source: CORER */
1968 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_S 0
1969 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M BIT(0)
1970 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_S 1
1971 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_M BIT(1)
1972 #define GLDCB_TFPFCI 0x0009949C /* Reset Source: CORER */
1973 #define GLDCB_TFPFCI_GLDCB_TFPFCI_S 0
1974 #define GLDCB_TFPFCI_GLDCB_TFPFCI_M MAKEMASK(0xFFFFFFFF, 0)
1975 #define GLDCB_TLPM_IMM_TCB 0x000A0190 /* Reset Source: CORER */
1976 #define GLDCB_TLPM_IMM_TCB_IMM_EN_S 0
1977 #define GLDCB_TLPM_IMM_TCB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1978 #define GLDCB_TLPM_IMM_TCUPM 0x000A018C /* Reset Source: CORER */
1979 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_S 0
1980 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1981 #define GLDCB_TLPM_PCI_DM 0x000A0180 /* Reset Source: CORER */
1982 #define GLDCB_TLPM_PCI_DM_MONITOR_S 0
1983 #define GLDCB_TLPM_PCI_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
1984 #define GLDCB_TLPM_PCI_DTHR 0x000A0184 /* Reset Source: CORER */
1985 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_S 0
1986 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_M MAKEMASK(0xFFF, 0)
1987 #define GLDCB_TPB_IMM_TLPM 0x00099468 /* Reset Source: CORER */
1988 #define GLDCB_TPB_IMM_TLPM_IMM_EN_S 0
1989 #define GLDCB_TPB_IMM_TLPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1990 #define GLDCB_TPB_IMM_TPB 0x0009946C /* Reset Source: CORER */
1991 #define GLDCB_TPB_IMM_TPB_IMM_EN_S 0
1992 #define GLDCB_TPB_IMM_TPB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1993 #define GLDCB_TPB_TCLL_CFG 0x00099464 /* Reset Source: CORER */
1994 #define GLDCB_TPB_TCLL_CFG_LLTC_S 0
1995 #define GLDCB_TPB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
1996 #define GLTCB_BULK_DWRR_REG_QUANTA 0x000AE0E0 /* Reset Source: CORER */
1997 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
1998 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
1999 #define GLTCB_BULK_DWRR_REG_SAT 0x000AE0F0 /* Reset Source: CORER */
2000 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_S 0
2001 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2002 #define GLTCB_BULK_DWRR_WB_QUANTA 0x000AE0E4 /* Reset Source: CORER */
2003 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
2004 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2005 #define GLTCB_BULK_DWRR_WB_SAT 0x000AE0F4 /* Reset Source: CORER */
2006 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_S 0
2007 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2008 #define GLTCB_CREDIT_EXP_CTL 0x000AE120 /* Reset Source: CORER */
2009 #define GLTCB_CREDIT_EXP_CTL_EN_S 0
2010 #define GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
2011 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1
2012 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
2013 #define GLTCB_LL_DWRR_REG_QUANTA 0x000AE0E8 /* Reset Source: CORER */
2014 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_S 0
2015 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2016 #define GLTCB_LL_DWRR_REG_SAT 0x000AE0F8 /* Reset Source: CORER */
2017 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_S 0
2018 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2019 #define GLTCB_LL_DWRR_WB_QUANTA 0x000AE0EC /* Reset Source: CORER */
2020 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_S 0
2021 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2022 #define GLTCB_LL_DWRR_WB_SAT 0x000AE0FC /* Reset Source: CORER */
2023 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_S 0
2024 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2025 #define GLTCB_WB_RL 0x000AE238 /* Reset Source: CORER */
2026 #define GLTCB_WB_RL_PERIOD_S 0
2027 #define GLTCB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
2028 #define GLTCB_WB_RL_EN_S 16
2029 #define GLTCB_WB_RL_EN_M BIT(16)
2030 #define GLTPB_WB_RL 0x00099460 /* Reset Source: CORER */
2031 #define GLTPB_WB_RL_PERIOD_S 0
2032 #define GLTPB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
2033 #define GLTPB_WB_RL_EN_S 16
2034 #define GLTPB_WB_RL_EN_M BIT(16)
2035 #define PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */
2036 #define PRTDCB_FCCFG_TFCE_S 3
2037 #define PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3)
2038 #define PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */
2039 #define PRTDCB_FCRTV_FC_REFRESH_TH_S 0
2040 #define PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0)
2041 #define PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */
2042 #define PRTDCB_FCTTVN_MAX_INDEX 3
2043 #define PRTDCB_FCTTVN_TTV_2N_S 0
2044 #define PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0)
2045 #define PRTDCB_FCTTVN_TTV_2N_P1_S 16
2046 #define PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16)
2047 #define PRTDCB_GENC 0x00083000 /* Reset Source: CORER */
2048 #define PRTDCB_GENC_NUMTC_S 2
2049 #define PRTDCB_GENC_NUMTC_M MAKEMASK(0xF, 2)
2050 #define PRTDCB_GENC_FCOEUP_S 6
2051 #define PRTDCB_GENC_FCOEUP_M MAKEMASK(0x7, 6)
2052 #define PRTDCB_GENC_FCOEUP_VALID_S 9
2053 #define PRTDCB_GENC_FCOEUP_VALID_M BIT(9)
2054 #define PRTDCB_GENC_PFCLDA_S 16
2055 #define PRTDCB_GENC_PFCLDA_M MAKEMASK(0xFFFF, 16)
2056 #define PRTDCB_GENS 0x00083020 /* Reset Source: CORER */
2057 #define PRTDCB_GENS_DCBX_STATUS_S 0
2058 #define PRTDCB_GENS_DCBX_STATUS_M MAKEMASK(0x7, 0)
2059 #define PRTDCB_PRS_RETSC 0x002001A0 /* Reset Source: CORER */
2060 #define PRTDCB_PRS_RETSC_ETS_MODE_S 0
2061 #define PRTDCB_PRS_RETSC_ETS_MODE_M BIT(0)
2062 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_S 1
2063 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_M BIT(1)
2064 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_S 2
2065 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2066 #define PRTDCB_PRS_RPRRC 0x00200180 /* Reset Source: CORER */
2067 #define PRTDCB_PRS_RPRRC_BWSHARE_S 0
2068 #define PRTDCB_PRS_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2069 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_S 31
2070 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_M BIT(31)
2071 #define PRTDCB_RETSC 0x001222A0 /* Reset Source: CORER */
2072 #define PRTDCB_RETSC_ETS_MODE_S 0
2073 #define PRTDCB_RETSC_ETS_MODE_M BIT(0)
2074 #define PRTDCB_RETSC_NON_ETS_MODE_S 1
2075 #define PRTDCB_RETSC_NON_ETS_MODE_M BIT(1)
2076 #define PRTDCB_RETSC_ETS_MAX_EXP_S 2
2077 #define PRTDCB_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2078 #define PRTDCB_RPRRC 0x001220C0 /* Reset Source: CORER */
2079 #define PRTDCB_RPRRC_BWSHARE_S 0
2080 #define PRTDCB_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2081 #define PRTDCB_RPRRC_BWSHARE_DIS_S 31
2082 #define PRTDCB_RPRRC_BWSHARE_DIS_M BIT(31)
2083 #define PRTDCB_RPRRS 0x001220E0 /* Reset Source: CORER */
2084 #define PRTDCB_RPRRS_CREDITS_S 0
2085 #define PRTDCB_RPRRS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
2086 #define PRTDCB_RUP_TDPU 0x00040960 /* Reset Source: CORER */
2087 #define PRTDCB_RUP_TDPU_NOVLANUP_S 0
2088 #define PRTDCB_RUP_TDPU_NOVLANUP_M MAKEMASK(0x7, 0)
2089 #define PRTDCB_RUP2TC 0x001D2640 /* Reset Source: CORER */
2090 #define PRTDCB_RUP2TC_UP0TC_S 0
2091 #define PRTDCB_RUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2092 #define PRTDCB_RUP2TC_UP1TC_S 3
2093 #define PRTDCB_RUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2094 #define PRTDCB_RUP2TC_UP2TC_S 6
2095 #define PRTDCB_RUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2096 #define PRTDCB_RUP2TC_UP3TC_S 9
2097 #define PRTDCB_RUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2098 #define PRTDCB_RUP2TC_UP4TC_S 12
2099 #define PRTDCB_RUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2100 #define PRTDCB_RUP2TC_UP5TC_S 15
2101 #define PRTDCB_RUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2102 #define PRTDCB_RUP2TC_UP6TC_S 18
2103 #define PRTDCB_RUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2104 #define PRTDCB_RUP2TC_UP7TC_S 21
2105 #define PRTDCB_RUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2106 #define PRTDCB_SWT_RETSC 0x0020A140 /* Reset Source: CORER */
2107 #define PRTDCB_SWT_RETSC_ETS_MODE_S 0
2108 #define PRTDCB_SWT_RETSC_ETS_MODE_M BIT(0)
2109 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_S 1
2110 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_M BIT(1)
2111 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_S 2
2112 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2113 #define PRTDCB_TCB_DWRR_CREDITS 0x000AE000 /* Reset Source: CORER */
2114 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2115 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2116 #define PRTDCB_TCB_DWRR_QUANTA 0x000AE020 /* Reset Source: CORER */
2117 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2118 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2119 #define PRTDCB_TCB_DWRR_SAT 0x000AE040 /* Reset Source: CORER */
2120 #define PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2121 #define PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2122 #define PRTDCB_TCUPM_NO_EXCEED_DM 0x000BC3C0 /* Reset Source: CORER */
2123 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_S 0
2124 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2125 #define PRTDCB_TCUPM_REG_CM 0x000BC360 /* Reset Source: CORER */
2126 #define PRTDCB_TCUPM_REG_CM_MONITOR_S 0
2127 #define PRTDCB_TCUPM_REG_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2128 #define PRTDCB_TCUPM_REG_CTHR 0x000BC380 /* Reset Source: CORER */
2129 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_S 0
2130 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_M MAKEMASK(0x7FFF, 0)
2131 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_S 15
2132 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_M MAKEMASK(0x7FFF, 15)
2133 #define PRTDCB_TCUPM_REG_DM 0x000BC3A0 /* Reset Source: CORER */
2134 #define PRTDCB_TCUPM_REG_DM_MONITOR_S 0
2135 #define PRTDCB_TCUPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2136 #define PRTDCB_TCUPM_REG_DTHR 0x000BC3E0 /* Reset Source: CORER */
2137 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_S 0
2138 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2139 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_S 12
2140 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2141 #define PRTDCB_TCUPM_REG_PE_HB_DM 0x000BC400 /* Reset Source: CORER */
2142 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_S 0
2143 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2144 #define PRTDCB_TCUPM_REG_PE_HB_DTHR 0x000BC420 /* Reset Source: CORER */
2145 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_S 0
2146 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2147 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_S 12
2148 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2149 #define PRTDCB_TCUPM_WAIT_PFC_CM 0x000BC440 /* Reset Source: CORER */
2150 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_S 0
2151 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2152 #define PRTDCB_TCUPM_WAIT_PFC_CTHR 0x000BC460 /* Reset Source: CORER */
2153 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_S 0
2154 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_M MAKEMASK(0x7FFF, 0)
2155 #define PRTDCB_TCUPM_WAIT_PFC_DM 0x000BC480 /* Reset Source: CORER */
2156 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_S 0
2157 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2158 #define PRTDCB_TCUPM_WAIT_PFC_DTHR 0x000BC4A0 /* Reset Source: CORER */
2159 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2160 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2161 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM 0x000BC4C0 /* Reset Source: CORER */
2162 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_S 0
2163 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2164 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR 0x000BC4E0 /* Reset Source: CORER */
2165 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_S 0
2166 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2167 #define PRTDCB_TDPUC 0x00040940 /* Reset Source: CORER */
2168 #define PRTDCB_TDPUC_MAX_TXFRAME_S 0
2169 #define PRTDCB_TDPUC_MAX_TXFRAME_M MAKEMASK(0xFFFF, 0)
2170 #define PRTDCB_TDPUC_MAL_LENGTH_S 16
2171 #define PRTDCB_TDPUC_MAL_LENGTH_M BIT(16)
2172 #define PRTDCB_TDPUC_MAL_CMD_S 17
2173 #define PRTDCB_TDPUC_MAL_CMD_M BIT(17)
2174 #define PRTDCB_TDPUC_TTL_DROP_S 18
2175 #define PRTDCB_TDPUC_TTL_DROP_M BIT(18)
2176 #define PRTDCB_TDPUC_UR_DROP_S 19
2177 #define PRTDCB_TDPUC_UR_DROP_M BIT(19)
2178 #define PRTDCB_TDPUC_DUMMY_S 20
2179 #define PRTDCB_TDPUC_DUMMY_M BIT(20)
2180 #define PRTDCB_TDPUC_BIG_PKT_SIZE_S 21
2181 #define PRTDCB_TDPUC_BIG_PKT_SIZE_M BIT(21)
2182 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_S 22
2183 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_M BIT(22)
2184 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_S 23
2185 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_M BIT(23)
2186 #define PRTDCB_TDPUC_RCU_ANTISPOOF_S 24
2187 #define PRTDCB_TDPUC_RCU_ANTISPOOF_M BIT(24)
2188 #define PRTDCB_TDPUC_NIC_DSI_S 25
2189 #define PRTDCB_TDPUC_NIC_DSI_M BIT(25)
2190 #define PRTDCB_TDPUC_NIC_IPSEC_S 26
2191 #define PRTDCB_TDPUC_NIC_IPSEC_M BIT(26)
2192 #define PRTDCB_TDPUC_CLEAR_DROP_S 31
2193 #define PRTDCB_TDPUC_CLEAR_DROP_M BIT(31)
2194 #define PRTDCB_TFCS 0x001E4560 /* Reset Source: GLOBR */
2195 #define PRTDCB_TFCS_TXOFF_S 0
2196 #define PRTDCB_TFCS_TXOFF_M BIT(0)
2197 #define PRTDCB_TFCS_TXOFF0_S 8
2198 #define PRTDCB_TFCS_TXOFF0_M BIT(8)
2199 #define PRTDCB_TFCS_TXOFF1_S 9
2200 #define PRTDCB_TFCS_TXOFF1_M BIT(9)
2201 #define PRTDCB_TFCS_TXOFF2_S 10
2202 #define PRTDCB_TFCS_TXOFF2_M BIT(10)
2203 #define PRTDCB_TFCS_TXOFF3_S 11
2204 #define PRTDCB_TFCS_TXOFF3_M BIT(11)
2205 #define PRTDCB_TFCS_TXOFF4_S 12
2206 #define PRTDCB_TFCS_TXOFF4_M BIT(12)
2207 #define PRTDCB_TFCS_TXOFF5_S 13
2208 #define PRTDCB_TFCS_TXOFF5_M BIT(13)
2209 #define PRTDCB_TFCS_TXOFF6_S 14
2210 #define PRTDCB_TFCS_TXOFF6_M BIT(14)
2211 #define PRTDCB_TFCS_TXOFF7_S 15
2212 #define PRTDCB_TFCS_TXOFF7_M BIT(15)
2213 #define PRTDCB_TLPM_REG_DM 0x000A0000 /* Reset Source: CORER */
2214 #define PRTDCB_TLPM_REG_DM_MONITOR_S 0
2215 #define PRTDCB_TLPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2216 #define PRTDCB_TLPM_REG_DTHR 0x000A0020 /* Reset Source: CORER */
2217 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_S 0
2218 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2219 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_S 12
2220 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2221 #define PRTDCB_TLPM_WAIT_PFC_DM 0x000A0040 /* Reset Source: CORER */
2222 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_S 0
2223 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2224 #define PRTDCB_TLPM_WAIT_PFC_DTHR 0x000A0060 /* Reset Source: CORER */
2225 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2226 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2227 #define PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
2228 #define PRTDCB_TPFCTS_MAX_INDEX 7
2229 #define PRTDCB_TPFCTS_PFCTIMER_S 0
2230 #define PRTDCB_TPFCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
2231 #define PRTDCB_TUP2TC 0x001D26C0 /* Reset Source: CORER */
2232 #define PRTDCB_TUP2TC_UP0TC_S 0
2233 #define PRTDCB_TUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2234 #define PRTDCB_TUP2TC_UP1TC_S 3
2235 #define PRTDCB_TUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2236 #define PRTDCB_TUP2TC_UP2TC_S 6
2237 #define PRTDCB_TUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2238 #define PRTDCB_TUP2TC_UP3TC_S 9
2239 #define PRTDCB_TUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2240 #define PRTDCB_TUP2TC_UP4TC_S 12
2241 #define PRTDCB_TUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2242 #define PRTDCB_TUP2TC_UP5TC_S 15
2243 #define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2244 #define PRTDCB_TUP2TC_UP6TC_S 18
2245 #define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2246 #define PRTDCB_TUP2TC_UP7TC_S 21
2247 #define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2248 #define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */
2249 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0
2250 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
2251 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
2252 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
2253 #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2254 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7
2255 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
2256 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2257 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4
2258 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2259 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8
2260 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2261 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_S 12
2262 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2263 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_S 16
2264 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2265 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_S 20
2266 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2267 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_S 24
2268 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2269 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_S 28
2270 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2271 #define PRTDCB_TX_DSCP2UP_IPV6_LUT(_i) (0x00040AA0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2272 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_MAX_INDEX 7
2273 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_S 0
2274 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2275 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_S 4
2276 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2277 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_S 8
2278 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2279 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_S 12
2280 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2281 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_S 16
2282 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2283 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_S 20
2284 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2285 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_S 24
2286 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2287 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_S 28
2288 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2289 #define PRTTCB_BULK_DWRR_REG_CREDITS 0x000AE060 /* Reset Source: CORER */
2290 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2291 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2292 #define PRTTCB_BULK_DWRR_WB_CREDITS 0x000AE080 /* Reset Source: CORER */
2293 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2294 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2295 #define PRTTCB_CREDIT_EXP 0x000AE100 /* Reset Source: CORER */
2296 #define PRTTCB_CREDIT_EXP_EXPANSION_S 0
2297 #define PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2298 #define PRTTCB_LL_DWRR_REG_CREDITS 0x000AE0A0 /* Reset Source: CORER */
2299 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2300 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2301 #define PRTTCB_LL_DWRR_WB_CREDITS 0x000AE0C0 /* Reset Source: CORER */
2302 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2303 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2304 #define TCDCB_TCUPM_WAIT_CM(_i) (0x000BC520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2305 #define TCDCB_TCUPM_WAIT_CM_MAX_INDEX 31
2306 #define TCDCB_TCUPM_WAIT_CM_MONITOR_S 0
2307 #define TCDCB_TCUPM_WAIT_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2308 #define TCDCB_TCUPM_WAIT_CTHR(_i) (0x000BC5A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2309 #define TCDCB_TCUPM_WAIT_CTHR_MAX_INDEX 31
2310 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_S 0
2311 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_M MAKEMASK(0x7FFF, 0)
2312 #define TCDCB_TCUPM_WAIT_DM(_i) (0x000BC620 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2313 #define TCDCB_TCUPM_WAIT_DM_MAX_INDEX 31
2314 #define TCDCB_TCUPM_WAIT_DM_MONITOR_S 0
2315 #define TCDCB_TCUPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2316 #define TCDCB_TCUPM_WAIT_DTHR(_i) (0x000BC6A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2317 #define TCDCB_TCUPM_WAIT_DTHR_MAX_INDEX 31
2318 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_S 0
2319 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2320 #define TCDCB_TCUPM_WAIT_PE_HB_DM(_i) (0x000BC720 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2321 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MAX_INDEX 31
2322 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_S 0
2323 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2324 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR(_i) (0x000BC7A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2325 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_MAX_INDEX 31
2326 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_S 0
2327 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2328 #define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2329 #define TCDCB_TLPM_WAIT_DM_MAX_INDEX 31
2330 #define TCDCB_TLPM_WAIT_DM_MONITOR_S 0
2331 #define TCDCB_TLPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2332 #define TCDCB_TLPM_WAIT_DTHR(_i) (0x000A0100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2333 #define TCDCB_TLPM_WAIT_DTHR_MAX_INDEX 31
2334 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_S 0
2335 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2336 #define TCTCB_WB_RL_TC_CFG(_i) (0x000AE138 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2337 #define TCTCB_WB_RL_TC_CFG_MAX_INDEX 31
2338 #define TCTCB_WB_RL_TC_CFG_TOKENS_S 0
2339 #define TCTCB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2340 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_S 12
2341 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2342 #define TCTCB_WB_RL_TC_STAT(_i) (0x000AE1B8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2343 #define TCTCB_WB_RL_TC_STAT_MAX_INDEX 31
2344 #define TCTCB_WB_RL_TC_STAT_BUCKET_S 0
2345 #define TCTCB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2346 #define TPB_BULK_DWRR_REG_QUANTA 0x00099340 /* Reset Source: CORER */
2347 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
2348 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2349 #define TPB_BULK_DWRR_REG_SAT 0x00099350 /* Reset Source: CORER */
2350 #define TPB_BULK_DWRR_REG_SAT_SATURATION_S 0
2351 #define TPB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2352 #define TPB_BULK_DWRR_WB_QUANTA 0x00099344 /* Reset Source: CORER */
2353 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
2354 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2355 #define TPB_BULK_DWRR_WB_SAT 0x00099354 /* Reset Source: CORER */
2356 #define TPB_BULK_DWRR_WB_SAT_SATURATION_S 0
2357 #define TPB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2358 #define TPB_GLDCB_TCB_WB_SP 0x0009966C /* Reset Source: CORER */
2359 #define TPB_GLDCB_TCB_WB_SP_WB_SP_S 0
2360 #define TPB_GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
2361 #define TPB_GLTCB_CREDIT_EXP_CTL 0x00099664 /* Reset Source: CORER */
2362 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_S 0
2363 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
2364 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1
2365 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
2366 #define TPB_LL_DWRR_REG_QUANTA 0x00099348 /* Reset Source: CORER */
2367 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_S 0
2368 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2369 #define TPB_LL_DWRR_REG_SAT 0x00099358 /* Reset Source: CORER */
2370 #define TPB_LL_DWRR_REG_SAT_SATURATION_S 0
2371 #define TPB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2372 #define TPB_LL_DWRR_WB_QUANTA 0x0009934C /* Reset Source: CORER */
2373 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_S 0
2374 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2375 #define TPB_LL_DWRR_WB_SAT 0x0009935C /* Reset Source: CORER */
2376 #define TPB_LL_DWRR_WB_SAT_SATURATION_S 0
2377 #define TPB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2378 #define TPB_PRTDCB_TCB_DWRR_CREDITS 0x000991C0 /* Reset Source: CORER */
2379 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2380 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2381 #define TPB_PRTDCB_TCB_DWRR_QUANTA 0x00099220 /* Reset Source: CORER */
2382 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2383 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2384 #define TPB_PRTDCB_TCB_DWRR_SAT 0x00099260 /* Reset Source: CORER */
2385 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2386 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2387 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS 0x000992A0 /* Reset Source: CORER */
2388 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2389 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2390 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS 0x000992C0 /* Reset Source: CORER */
2391 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2392 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2393 #define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */
2394 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0
2395 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2396 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */
2397 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2398 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2399 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */
2400 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2401 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2402 #define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2403 #define TPB_WB_RL_TC_CFG_MAX_INDEX 31
2404 #define TPB_WB_RL_TC_CFG_TOKENS_S 0
2405 #define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2406 #define TPB_WB_RL_TC_CFG_BURST_SIZE_S 12
2407 #define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2408 #define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2409 #define TPB_WB_RL_TC_STAT_MAX_INDEX 31
2410 #define TPB_WB_RL_TC_STAT_BUCKET_S 0
2411 #define TPB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2412 #define GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2413 #define GL_ACLEXT_CDMD_L1SEL_MAX_INDEX 2
2414 #define GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0
2415 #define GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2416 #define GL_ACLEXT_CDMD_L1SEL_TX_SEL_S 8
2417 #define GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2418 #define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S 16
2419 #define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2420 #define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S 24
2421 #define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2422 #define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2423 #define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2424 #define GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2425 #define GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2426 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2427 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2428 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2429 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2430 #define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2431 #define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2432 #define GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2433 #define GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX 2
2434 #define GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0
2435 #define GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2436 #define GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2437 #define GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX 2
2438 #define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2439 #define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2440 #define GL_ACLEXT_DFLT_L2PRFL_ACL(_i) (0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2441 #define GL_ACLEXT_DFLT_L2PRFL_ACL_MAX_INDEX 2
2442 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S 0
2443 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2444 #define GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2445 #define GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2446 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0
2447 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2448 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S 16
2449 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2450 #define GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2451 #define GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2452 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0
2453 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2454 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S 16
2455 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2456 #define GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2457 #define GL_ACLEXT_FLGS_L1TBL_MAX_INDEX 2
2458 #define GL_ACLEXT_FLGS_L1TBL_LSB_S 0
2459 #define GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2460 #define GL_ACLEXT_FLGS_L1TBL_MSB_S 16
2461 #define GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2462 #define GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2463 #define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
2464 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
2465 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2466 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2467 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2468 #define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2469 #define GL_ACLEXT_FORCE_PID_MAX_INDEX 2
2470 #define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
2471 #define GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2472 #define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31
2473 #define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2474 #define GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2475 #define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2
2476 #define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0
2477 #define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2478 #define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S 31
2479 #define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2480 #define GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2481 #define GL_ACLEXT_K2N_L2DATA_MAX_INDEX 2
2482 #define GL_ACLEXT_K2N_L2DATA_DATA0_S 0
2483 #define GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2484 #define GL_ACLEXT_K2N_L2DATA_DATA1_S 8
2485 #define GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2486 #define GL_ACLEXT_K2N_L2DATA_DATA2_S 16
2487 #define GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2488 #define GL_ACLEXT_K2N_L2DATA_DATA3_S 24
2489 #define GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2490 #define GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2491 #define GL_ACLEXT_L2_PMASK0_MAX_INDEX 2
2492 #define GL_ACLEXT_L2_PMASK0_BITMASK_S 0
2493 #define GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2494 #define GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2495 #define GL_ACLEXT_L2_PMASK1_MAX_INDEX 2
2496 #define GL_ACLEXT_L2_PMASK1_BITMASK_S 0
2497 #define GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2498 #define GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2499 #define GL_ACLEXT_L2_TMASK0_MAX_INDEX 2
2500 #define GL_ACLEXT_L2_TMASK0_BITMASK_S 0
2501 #define GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2502 #define GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2503 #define GL_ACLEXT_L2_TMASK1_MAX_INDEX 2
2504 #define GL_ACLEXT_L2_TMASK1_BITMASK_S 0
2505 #define GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2506 #define GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2507 #define GL_ACLEXT_L2BMP0_3_MAX_INDEX 2
2508 #define GL_ACLEXT_L2BMP0_3_BMP0_S 0
2509 #define GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2510 #define GL_ACLEXT_L2BMP0_3_BMP1_S 8
2511 #define GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2512 #define GL_ACLEXT_L2BMP0_3_BMP2_S 16
2513 #define GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2514 #define GL_ACLEXT_L2BMP0_3_BMP3_S 24
2515 #define GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2516 #define GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2517 #define GL_ACLEXT_L2BMP4_7_MAX_INDEX 2
2518 #define GL_ACLEXT_L2BMP4_7_BMP4_S 0
2519 #define GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2520 #define GL_ACLEXT_L2BMP4_7_BMP5_S 8
2521 #define GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2522 #define GL_ACLEXT_L2BMP4_7_BMP6_S 16
2523 #define GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2524 #define GL_ACLEXT_L2BMP4_7_BMP7_S 24
2525 #define GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2526 #define GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2527 #define GL_ACLEXT_L2PRTMOD_MAX_INDEX 2
2528 #define GL_ACLEXT_L2PRTMOD_XLT1_S 0
2529 #define GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2530 #define GL_ACLEXT_L2PRTMOD_XLT2_S 8
2531 #define GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2532 #define GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2533 #define GL_ACLEXT_N2N_L2ADDR_MAX_INDEX 2
2534 #define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0
2535 #define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2536 #define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S 31
2537 #define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2538 #define GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2539 #define GL_ACLEXT_N2N_L2DATA_MAX_INDEX 2
2540 #define GL_ACLEXT_N2N_L2DATA_DATA0_S 0
2541 #define GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2542 #define GL_ACLEXT_N2N_L2DATA_DATA1_S 8
2543 #define GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2544 #define GL_ACLEXT_N2N_L2DATA_DATA2_S 16
2545 #define GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2546 #define GL_ACLEXT_N2N_L2DATA_DATA3_S 24
2547 #define GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2548 #define GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2549 #define GL_ACLEXT_P2P_L1ADDR_MAX_INDEX 2
2550 #define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0
2551 #define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2552 #define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S 31
2553 #define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2554 #define GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2555 #define GL_ACLEXT_P2P_L1DATA_MAX_INDEX 2
2556 #define GL_ACLEXT_P2P_L1DATA_DATA_S 0
2557 #define GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2558 #define GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2559 #define GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX 2
2560 #define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2561 #define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2562 #define GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2563 #define GL_ACLEXT_PLVL_SEL_MAX_INDEX 2
2564 #define GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0
2565 #define GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2566 #define GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2567 #define GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX 2
2568 #define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0
2569 #define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2570 #define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S 31
2571 #define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2572 #define GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2573 #define GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX 2
2574 #define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0
2575 #define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2576 #define GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2577 #define GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2578 #define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2579 #define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2580 #define GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2581 #define GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX 2
2582 #define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0
2583 #define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2584 #define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S 31
2585 #define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2586 #define GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2587 #define GL_ACLEXT_XLT0_L1DATA_MAX_INDEX 2
2588 #define GL_ACLEXT_XLT0_L1DATA_DATA_S 0
2589 #define GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2590 #define GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2591 #define GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX 2
2592 #define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0
2593 #define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2594 #define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S 31
2595 #define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2596 #define GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2597 #define GL_ACLEXT_XLT1_L2DATA_MAX_INDEX 2
2598 #define GL_ACLEXT_XLT1_L2DATA_DATA_S 0
2599 #define GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2600 #define GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2601 #define GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX 2
2602 #define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0
2603 #define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2604 #define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S 31
2605 #define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
2606 #define GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2607 #define GL_ACLEXT_XLT2_L2DATA_MAX_INDEX 2
2608 #define GL_ACLEXT_XLT2_L2DATA_DATA_S 0
2609 #define GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2610 #define GL_PREEXT_CDMD_L1SEL(_i) (0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2611 #define GL_PREEXT_CDMD_L1SEL_MAX_INDEX 2
2612 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_S 0
2613 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2614 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_S 8
2615 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2616 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_S 16
2617 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2618 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_S 24
2619 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2620 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2621 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2622 #define GL_PREEXT_CTLTBL_L2ADDR(_i) (0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2623 #define GL_PREEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2624 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2625 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2626 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2627 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2628 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2629 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2630 #define GL_PREEXT_CTLTBL_L2DATA(_i) (0x0020F090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2631 #define GL_PREEXT_CTLTBL_L2DATA_MAX_INDEX 2
2632 #define GL_PREEXT_CTLTBL_L2DATA_DATA_S 0
2633 #define GL_PREEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2634 #define GL_PREEXT_DFLT_L2PRFL(_i) (0x0020F138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2635 #define GL_PREEXT_DFLT_L2PRFL_MAX_INDEX 2
2636 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2637 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2638 #define GL_PREEXT_FLGS_L1SEL0_1(_i) (0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2639 #define GL_PREEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2640 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S 0
2641 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2642 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_S 16
2643 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2644 #define GL_PREEXT_FLGS_L1SEL2_3(_i) (0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2645 #define GL_PREEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2646 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S 0
2647 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2648 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_S 16
2649 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2650 #define GL_PREEXT_FLGS_L1TBL(_i) (0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2651 #define GL_PREEXT_FLGS_L1TBL_MAX_INDEX 2
2652 #define GL_PREEXT_FLGS_L1TBL_LSB_S 0
2653 #define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2654 #define GL_PREEXT_FLGS_L1TBL_MSB_S 16
2655 #define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2656 #define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2657 #define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2
2658 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0
2659 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2660 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2661 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2662 #define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2663 #define GL_PREEXT_FORCE_PID_MAX_INDEX 2
2664 #define GL_PREEXT_FORCE_PID_STATIC_PID_S 0
2665 #define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2666 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S 31
2667 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2668 #define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2669 #define GL_PREEXT_K2N_L2ADDR_MAX_INDEX 2
2670 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_S 0
2671 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2672 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_S 31
2673 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2674 #define GL_PREEXT_K2N_L2DATA(_i) (0x0020F150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2675 #define GL_PREEXT_K2N_L2DATA_MAX_INDEX 2
2676 #define GL_PREEXT_K2N_L2DATA_DATA0_S 0
2677 #define GL_PREEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2678 #define GL_PREEXT_K2N_L2DATA_DATA1_S 8
2679 #define GL_PREEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2680 #define GL_PREEXT_K2N_L2DATA_DATA2_S 16
2681 #define GL_PREEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2682 #define GL_PREEXT_K2N_L2DATA_DATA3_S 24
2683 #define GL_PREEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2684 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2685 #define GL_PREEXT_L2_PMASK0_MAX_INDEX 2
2686 #define GL_PREEXT_L2_PMASK0_BITMASK_S 0
2687 #define GL_PREEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2688 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2689 #define GL_PREEXT_L2_PMASK1_MAX_INDEX 2
2690 #define GL_PREEXT_L2_PMASK1_BITMASK_S 0
2691 #define GL_PREEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2692 #define GL_PREEXT_L2_TMASK0(_i) (0x0020F498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2693 #define GL_PREEXT_L2_TMASK0_MAX_INDEX 2
2694 #define GL_PREEXT_L2_TMASK0_BITMASK_S 0
2695 #define GL_PREEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2696 #define GL_PREEXT_L2_TMASK1(_i) (0x0020F4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2697 #define GL_PREEXT_L2_TMASK1_MAX_INDEX 2
2698 #define GL_PREEXT_L2_TMASK1_BITMASK_S 0
2699 #define GL_PREEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2700 #define GL_PREEXT_L2BMP0_3(_i) (0x0020F0A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2701 #define GL_PREEXT_L2BMP0_3_MAX_INDEX 2
2702 #define GL_PREEXT_L2BMP0_3_BMP0_S 0
2703 #define GL_PREEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2704 #define GL_PREEXT_L2BMP0_3_BMP1_S 8
2705 #define GL_PREEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2706 #define GL_PREEXT_L2BMP0_3_BMP2_S 16
2707 #define GL_PREEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2708 #define GL_PREEXT_L2BMP0_3_BMP3_S 24
2709 #define GL_PREEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2710 #define GL_PREEXT_L2BMP4_7(_i) (0x0020F0B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2711 #define GL_PREEXT_L2BMP4_7_MAX_INDEX 2
2712 #define GL_PREEXT_L2BMP4_7_BMP4_S 0
2713 #define GL_PREEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2714 #define GL_PREEXT_L2BMP4_7_BMP5_S 8
2715 #define GL_PREEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2716 #define GL_PREEXT_L2BMP4_7_BMP6_S 16
2717 #define GL_PREEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2718 #define GL_PREEXT_L2BMP4_7_BMP7_S 24
2719 #define GL_PREEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2720 #define GL_PREEXT_L2PRTMOD(_i) (0x0020F09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2721 #define GL_PREEXT_L2PRTMOD_MAX_INDEX 2
2722 #define GL_PREEXT_L2PRTMOD_XLT1_S 0
2723 #define GL_PREEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2724 #define GL_PREEXT_L2PRTMOD_XLT2_S 8
2725 #define GL_PREEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2726 #define GL_PREEXT_N2N_L2ADDR(_i) (0x0020F15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2727 #define GL_PREEXT_N2N_L2ADDR_MAX_INDEX 2
2728 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_S 0
2729 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2730 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_S 31
2731 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2732 #define GL_PREEXT_N2N_L2DATA(_i) (0x0020F168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2733 #define GL_PREEXT_N2N_L2DATA_MAX_INDEX 2
2734 #define GL_PREEXT_N2N_L2DATA_DATA0_S 0
2735 #define GL_PREEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2736 #define GL_PREEXT_N2N_L2DATA_DATA1_S 8
2737 #define GL_PREEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2738 #define GL_PREEXT_N2N_L2DATA_DATA2_S 16
2739 #define GL_PREEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2740 #define GL_PREEXT_N2N_L2DATA_DATA3_S 24
2741 #define GL_PREEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2742 #define GL_PREEXT_P2P_L1ADDR(_i) (0x0020F024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2743 #define GL_PREEXT_P2P_L1ADDR_MAX_INDEX 2
2744 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_S 0
2745 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2746 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_S 31
2747 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2748 #define GL_PREEXT_P2P_L1DATA(_i) (0x0020F030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2749 #define GL_PREEXT_P2P_L1DATA_MAX_INDEX 2
2750 #define GL_PREEXT_P2P_L1DATA_DATA_S 0
2751 #define GL_PREEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2752 #define GL_PREEXT_PID_L2GKTYPE(_i) (0x0020F0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2753 #define GL_PREEXT_PID_L2GKTYPE_MAX_INDEX 2
2754 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2755 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2756 #define GL_PREEXT_PLVL_SEL(_i) (0x0020F00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2757 #define GL_PREEXT_PLVL_SEL_MAX_INDEX 2
2758 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_S 0
2759 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2760 #define GL_PREEXT_TCAM_L2ADDR(_i) (0x0020F114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2761 #define GL_PREEXT_TCAM_L2ADDR_MAX_INDEX 2
2762 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_S 0
2763 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2764 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_S 31
2765 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2766 #define GL_PREEXT_TCAM_L2DATALSB(_i) (0x0020F120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2767 #define GL_PREEXT_TCAM_L2DATALSB_MAX_INDEX 2
2768 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_S 0
2769 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2770 #define GL_PREEXT_TCAM_L2DATAMSB(_i) (0x0020F12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2771 #define GL_PREEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2772 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2773 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2774 #define GL_PREEXT_XLT0_L1ADDR(_i) (0x0020F03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2775 #define GL_PREEXT_XLT0_L1ADDR_MAX_INDEX 2
2776 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_S 0
2777 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2778 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_S 31
2779 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2780 #define GL_PREEXT_XLT0_L1DATA(_i) (0x0020F048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2781 #define GL_PREEXT_XLT0_L1DATA_MAX_INDEX 2
2782 #define GL_PREEXT_XLT0_L1DATA_DATA_S 0
2783 #define GL_PREEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2784 #define GL_PREEXT_XLT1_L2ADDR(_i) (0x0020F0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2785 #define GL_PREEXT_XLT1_L2ADDR_MAX_INDEX 2
2786 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_S 0
2787 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2788 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_S 31
2789 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2790 #define GL_PREEXT_XLT1_L2DATA(_i) (0x0020F0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2791 #define GL_PREEXT_XLT1_L2DATA_MAX_INDEX 2
2792 #define GL_PREEXT_XLT1_L2DATA_DATA_S 0
2793 #define GL_PREEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2794 #define GL_PREEXT_XLT2_L2ADDR(_i) (0x0020F0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2795 #define GL_PREEXT_XLT2_L2ADDR_MAX_INDEX 2
2796 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_S 0
2797 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2798 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_S 31
2799 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
2800 #define GL_PREEXT_XLT2_L2DATA(_i) (0x0020F0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2801 #define GL_PREEXT_XLT2_L2DATA_MAX_INDEX 2
2802 #define GL_PREEXT_XLT2_L2DATA_DATA_S 0
2803 #define GL_PREEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2804 #define GL_PSTEXT_CDMD_L1SEL(_i) (0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2805 #define GL_PSTEXT_CDMD_L1SEL_MAX_INDEX 2
2806 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S 0
2807 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2808 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_S 8
2809 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2810 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_S 16
2811 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2812 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_S 24
2813 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2814 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2815 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2816 #define GL_PSTEXT_CTLTBL_L2ADDR(_i) (0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2817 #define GL_PSTEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2818 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2819 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2820 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2821 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2822 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2823 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2824 #define GL_PSTEXT_CTLTBL_L2DATA(_i) (0x0020E090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2825 #define GL_PSTEXT_CTLTBL_L2DATA_MAX_INDEX 2
2826 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_S 0
2827 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2828 #define GL_PSTEXT_DFLT_L2PRFL(_i) (0x0020E138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2829 #define GL_PSTEXT_DFLT_L2PRFL_MAX_INDEX 2
2830 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2831 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2832 #define GL_PSTEXT_FL15_BMPLSB(_i) (0x0020E480 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2833 #define GL_PSTEXT_FL15_BMPLSB_MAX_INDEX 2
2834 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_S 0
2835 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_M MAKEMASK(0xFFFFFFFF, 0)
2836 #define GL_PSTEXT_FL15_BMPMSB(_i) (0x0020E48C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2837 #define GL_PSTEXT_FL15_BMPMSB_MAX_INDEX 2
2838 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_S 0
2839 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_M MAKEMASK(0xFFFFFFFF, 0)
2840 #define GL_PSTEXT_FLGS_L1SEL0_1(_i) (0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2841 #define GL_PSTEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2842 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S 0
2843 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2844 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_S 16
2845 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2846 #define GL_PSTEXT_FLGS_L1SEL2_3(_i) (0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2847 #define GL_PSTEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2848 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S 0
2849 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2850 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_S 16
2851 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2852 #define GL_PSTEXT_FLGS_L1TBL(_i) (0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2853 #define GL_PSTEXT_FLGS_L1TBL_MAX_INDEX 2
2854 #define GL_PSTEXT_FLGS_L1TBL_LSB_S 0
2855 #define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2856 #define GL_PSTEXT_FLGS_L1TBL_MSB_S 16
2857 #define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2858 #define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2859 #define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2
2860 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0
2861 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2862 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2863 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2864 #define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2865 #define GL_PSTEXT_FORCE_PID_MAX_INDEX 2
2866 #define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0
2867 #define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2868 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S 31
2869 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2870 #define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2871 #define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX 2
2872 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_S 0
2873 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2874 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_S 31
2875 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2876 #define GL_PSTEXT_K2N_L2DATA(_i) (0x0020E150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2877 #define GL_PSTEXT_K2N_L2DATA_MAX_INDEX 2
2878 #define GL_PSTEXT_K2N_L2DATA_DATA0_S 0
2879 #define GL_PSTEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2880 #define GL_PSTEXT_K2N_L2DATA_DATA1_S 8
2881 #define GL_PSTEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2882 #define GL_PSTEXT_K2N_L2DATA_DATA2_S 16
2883 #define GL_PSTEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2884 #define GL_PSTEXT_K2N_L2DATA_DATA3_S 24
2885 #define GL_PSTEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2886 #define GL_PSTEXT_L2_PMASK0(_i) (0x0020E0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2887 #define GL_PSTEXT_L2_PMASK0_MAX_INDEX 2
2888 #define GL_PSTEXT_L2_PMASK0_BITMASK_S 0
2889 #define GL_PSTEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2890 #define GL_PSTEXT_L2_PMASK1(_i) (0x0020E108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2891 #define GL_PSTEXT_L2_PMASK1_MAX_INDEX 2
2892 #define GL_PSTEXT_L2_PMASK1_BITMASK_S 0
2893 #define GL_PSTEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2894 #define GL_PSTEXT_L2_TMASK0(_i) (0x0020E498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2895 #define GL_PSTEXT_L2_TMASK0_MAX_INDEX 2
2896 #define GL_PSTEXT_L2_TMASK0_BITMASK_S 0
2897 #define GL_PSTEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2898 #define GL_PSTEXT_L2_TMASK1(_i) (0x0020E4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2899 #define GL_PSTEXT_L2_TMASK1_MAX_INDEX 2
2900 #define GL_PSTEXT_L2_TMASK1_BITMASK_S 0
2901 #define GL_PSTEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2902 #define GL_PSTEXT_L2PRTMOD(_i) (0x0020E09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2903 #define GL_PSTEXT_L2PRTMOD_MAX_INDEX 2
2904 #define GL_PSTEXT_L2PRTMOD_XLT1_S 0
2905 #define GL_PSTEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2906 #define GL_PSTEXT_L2PRTMOD_XLT2_S 8
2907 #define GL_PSTEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2908 #define GL_PSTEXT_N2N_L2ADDR(_i) (0x0020E15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2909 #define GL_PSTEXT_N2N_L2ADDR_MAX_INDEX 2
2910 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_S 0
2911 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2912 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_S 31
2913 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2914 #define GL_PSTEXT_N2N_L2DATA(_i) (0x0020E168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2915 #define GL_PSTEXT_N2N_L2DATA_MAX_INDEX 2
2916 #define GL_PSTEXT_N2N_L2DATA_DATA0_S 0
2917 #define GL_PSTEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2918 #define GL_PSTEXT_N2N_L2DATA_DATA1_S 8
2919 #define GL_PSTEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2920 #define GL_PSTEXT_N2N_L2DATA_DATA2_S 16
2921 #define GL_PSTEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2922 #define GL_PSTEXT_N2N_L2DATA_DATA3_S 24
2923 #define GL_PSTEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2924 #define GL_PSTEXT_P2P_L1ADDR(_i) (0x0020E024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2925 #define GL_PSTEXT_P2P_L1ADDR_MAX_INDEX 2
2926 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_S 0
2927 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2928 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_S 31
2929 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2930 #define GL_PSTEXT_P2P_L1DATA(_i) (0x0020E030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2931 #define GL_PSTEXT_P2P_L1DATA_MAX_INDEX 2
2932 #define GL_PSTEXT_P2P_L1DATA_DATA_S 0
2933 #define GL_PSTEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2934 #define GL_PSTEXT_PID_L2GKTYPE(_i) (0x0020E0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2935 #define GL_PSTEXT_PID_L2GKTYPE_MAX_INDEX 2
2936 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2937 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2938 #define GL_PSTEXT_PLVL_SEL(_i) (0x0020E00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2939 #define GL_PSTEXT_PLVL_SEL_MAX_INDEX 2
2940 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_S 0
2941 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2942 #define GL_PSTEXT_PRFLM_CTRL(_i) (0x0020E474 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2943 #define GL_PSTEXT_PRFLM_CTRL_MAX_INDEX 2
2944 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_S 0
2945 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_M MAKEMASK(0xFF, 0)
2946 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_S 30
2947 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_M BIT(30)
2948 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_S 31
2949 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_M BIT(31)
2950 #define GL_PSTEXT_PRFLM_DATA_0(_i) (0x0020E174 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2951 #define GL_PSTEXT_PRFLM_DATA_0_MAX_INDEX 63
2952 #define GL_PSTEXT_PRFLM_DATA_0_PROT_S 0
2953 #define GL_PSTEXT_PRFLM_DATA_0_PROT_M MAKEMASK(0xFF, 0)
2954 #define GL_PSTEXT_PRFLM_DATA_0_OFF_S 16
2955 #define GL_PSTEXT_PRFLM_DATA_0_OFF_M MAKEMASK(0x1FF, 16)
2956 #define GL_PSTEXT_PRFLM_DATA_1(_i) (0x0020E274 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2957 #define GL_PSTEXT_PRFLM_DATA_1_MAX_INDEX 63
2958 #define GL_PSTEXT_PRFLM_DATA_1_PROT_S 0
2959 #define GL_PSTEXT_PRFLM_DATA_1_PROT_M MAKEMASK(0xFF, 0)
2960 #define GL_PSTEXT_PRFLM_DATA_1_OFF_S 16
2961 #define GL_PSTEXT_PRFLM_DATA_1_OFF_M MAKEMASK(0x1FF, 16)
2962 #define GL_PSTEXT_PRFLM_DATA_2(_i) (0x0020E374 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2963 #define GL_PSTEXT_PRFLM_DATA_2_MAX_INDEX 63
2964 #define GL_PSTEXT_PRFLM_DATA_2_PROT_S 0
2965 #define GL_PSTEXT_PRFLM_DATA_2_PROT_M MAKEMASK(0xFF, 0)
2966 #define GL_PSTEXT_PRFLM_DATA_2_OFF_S 16
2967 #define GL_PSTEXT_PRFLM_DATA_2_OFF_M MAKEMASK(0x1FF, 16)
2968 #define GL_PSTEXT_TCAM_L2ADDR(_i) (0x0020E114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2969 #define GL_PSTEXT_TCAM_L2ADDR_MAX_INDEX 2
2970 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_S 0
2971 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2972 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_S 31
2973 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2974 #define GL_PSTEXT_TCAM_L2DATALSB(_i) (0x0020E120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2975 #define GL_PSTEXT_TCAM_L2DATALSB_MAX_INDEX 2
2976 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_S 0
2977 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2978 #define GL_PSTEXT_TCAM_L2DATAMSB(_i) (0x0020E12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2979 #define GL_PSTEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2980 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2981 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2982 #define GL_PSTEXT_XLT0_L1ADDR(_i) (0x0020E03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2983 #define GL_PSTEXT_XLT0_L1ADDR_MAX_INDEX 2
2984 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_S 0
2985 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2986 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_S 31
2987 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2988 #define GL_PSTEXT_XLT0_L1DATA(_i) (0x0020E048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2989 #define GL_PSTEXT_XLT0_L1DATA_MAX_INDEX 2
2990 #define GL_PSTEXT_XLT0_L1DATA_DATA_S 0
2991 #define GL_PSTEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2992 #define GL_PSTEXT_XLT1_L2ADDR(_i) (0x0020E0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2993 #define GL_PSTEXT_XLT1_L2ADDR_MAX_INDEX 2
2994 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_S 0
2995 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2996 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_S 31
2997 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2998 #define GL_PSTEXT_XLT1_L2DATA(_i) (0x0020E0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2999 #define GL_PSTEXT_XLT1_L2DATA_MAX_INDEX 2
3000 #define GL_PSTEXT_XLT1_L2DATA_DATA_S 0
3001 #define GL_PSTEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3002 #define GL_PSTEXT_XLT2_L2ADDR(_i) (0x0020E0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3003 #define GL_PSTEXT_XLT2_L2ADDR_MAX_INDEX 2
3004 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_S 0
3005 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
3006 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_S 31
3007 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
3008 #define GL_PSTEXT_XLT2_L2DATA(_i) (0x0020E0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3009 #define GL_PSTEXT_XLT2_L2DATA_MAX_INDEX 2
3010 #define GL_PSTEXT_XLT2_L2DATA_DATA_S 0
3011 #define GL_PSTEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3012 #define GLFLXP_PTYPE_TRANSLATION(_i) (0x0045C000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3013 #define GLFLXP_PTYPE_TRANSLATION_MAX_INDEX 255
3014 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_S 0
3015 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_M MAKEMASK(0xFF, 0)
3016 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_S 8
3017 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_M MAKEMASK(0xFF, 8)
3018 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_S 16
3019 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_M MAKEMASK(0xFF, 16)
3020 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_S 24
3021 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_M MAKEMASK(0xFF, 24)
3022 #define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3023 #define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX 255
3024 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0
3025 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)
3026 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4
3027 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
3028 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8
3029 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
3030 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
3031 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
3032 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
3033 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
3034 #define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */
3035 #define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255
3036 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0
3037 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0)
3038 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S 8
3039 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8)
3040 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S 16
3041 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16)
3042 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_S 24
3043 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_M MAKEMASK(0xFF, 24)
3044 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...4 */ /* Reset Source: CORER */
3045 #define GLFLXP_RXDID_FLAGS_MAX_INDEX 63
3046 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
3047 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M MAKEMASK(0x3F, 0)
3048 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
3049 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M MAKEMASK(0x3F, 8)
3050 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16
3051 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M MAKEMASK(0x3F, 16)
3052 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24
3053 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M MAKEMASK(0x3F, 24)
3054 #define GLFLXP_RXDID_FLAGS1_OVERRIDE(_i) (0x0045D600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3055 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_MAX_INDEX 63
3056 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0
3057 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0)
3058 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045C800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3059 #define GLFLXP_RXDID_FLX_WRD_0_MAX_INDEX 63
3060 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
3061 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M MAKEMASK(0xFF, 0)
3062 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_S 8
3063 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3064 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
3065 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3066 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045C900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3067 #define GLFLXP_RXDID_FLX_WRD_1_MAX_INDEX 63
3068 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
3069 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M MAKEMASK(0xFF, 0)
3070 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_S 8
3071 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3072 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
3073 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3074 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045CA00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3075 #define GLFLXP_RXDID_FLX_WRD_2_MAX_INDEX 63
3076 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
3077 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M MAKEMASK(0xFF, 0)
3078 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_S 8
3079 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3080 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
3081 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3082 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045CB00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3083 #define GLFLXP_RXDID_FLX_WRD_3_MAX_INDEX 63
3084 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
3085 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M MAKEMASK(0xFF, 0)
3086 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_S 8
3087 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3088 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
3089 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3090 #define GLFLXP_RXDID_FLX_WRD_4(_i) (0x0045CC00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3091 #define GLFLXP_RXDID_FLX_WRD_4_MAX_INDEX 63
3092 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S 0
3093 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M MAKEMASK(0xFF, 0)
3094 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_S 8
3095 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3096 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_S 30
3097 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3098 #define GLFLXP_RXDID_FLX_WRD_5(_i) (0x0045CD00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3099 #define GLFLXP_RXDID_FLX_WRD_5_MAX_INDEX 63
3100 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S 0
3101 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M MAKEMASK(0xFF, 0)
3102 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_S 8
3103 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3104 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S 30
3105 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3106 #define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 */ /* Reset Source: CORER */
3107 #define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX 63
3108 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0
3109 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)
3110 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8
3111 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)
3112 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
3113 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
3114 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24
3115 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)
3116 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
3117 #define QRXFLXP_CNTXT_MAX_INDEX 2047
3118 #define QRXFLXP_CNTXT_RXDID_IDX_S 0
3119 #define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0)
3120 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8
3121 #define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8)
3122 #define QRXFLXP_CNTXT_TS_S 11
3123 #define QRXFLXP_CNTXT_TS_M BIT(11)
3124 #define GL_FWSTS 0x00083048 /* Reset Source: POR */
3125 #define GL_FWSTS_FWS0B_S 0
3126 #define GL_FWSTS_FWS0B_M MAKEMASK(0xFF, 0)
3127 #define GL_FWSTS_FWROWD_S 8
3128 #define GL_FWSTS_FWROWD_M BIT(8)
3129 #define GL_FWSTS_FWRI_S 9
3130 #define GL_FWSTS_FWRI_M BIT(9)
3131 #define GL_FWSTS_FWS1B_S 16
3132 #define GL_FWSTS_FWS1B_M MAKEMASK(0xFF, 16)
3133 #define GL_TCVMLR_DRAIN_CNTR_CTL 0x000A21E0 /* Reset Source: CORER */
3134 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_S 0
3135 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M BIT(0)
3136 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_S 1
3137 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_M MAKEMASK(0x7, 1)
3138 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_S 4
3139 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_M MAKEMASK(0x3FFF, 4)
3140 #define GL_TCVMLR_DRAIN_DONE_DEC 0x000A21A8 /* Reset Source: CORER */
3141 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_S 0
3142 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M BIT(0)
3143 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_S 1
3144 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_M MAKEMASK(0x1F, 1)
3145 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_S 6
3146 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_M MAKEMASK(0xFF, 6)
3147 #define GL_TCVMLR_DRAIN_DONE_TCLAN(_i) (0x000A20A8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3148 #define GL_TCVMLR_DRAIN_DONE_TCLAN_MAX_INDEX 31
3149 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_S 0
3150 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_M MAKEMASK(0xFF, 0)
3151 #define GL_TCVMLR_DRAIN_DONE_TPB(_i) (0x000A2128 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3152 #define GL_TCVMLR_DRAIN_DONE_TPB_MAX_INDEX 31
3153 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_S 0
3154 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_M MAKEMASK(0xFF, 0)
3155 #define GL_TCVMLR_DRAIN_MARKER 0x000A2008 /* Reset Source: CORER */
3156 #define GL_TCVMLR_DRAIN_MARKER_PORT_S 0
3157 #define GL_TCVMLR_DRAIN_MARKER_PORT_M MAKEMASK(0x7, 0)
3158 #define GL_TCVMLR_DRAIN_MARKER_TC_S 3
3159 #define GL_TCVMLR_DRAIN_MARKER_TC_M MAKEMASK(0x1F, 3)
3160 #define GL_TCVMLR_ERR_STAT 0x000A2024 /* Reset Source: CORER */
3161 #define GL_TCVMLR_ERR_STAT_ERROR_S 0
3162 #define GL_TCVMLR_ERR_STAT_ERROR_M BIT(0)
3163 #define GL_TCVMLR_ERR_STAT_FW_REQ_S 1
3164 #define GL_TCVMLR_ERR_STAT_FW_REQ_M BIT(1)
3165 #define GL_TCVMLR_ERR_STAT_STAT_S 2
3166 #define GL_TCVMLR_ERR_STAT_STAT_M MAKEMASK(0x7, 2)
3167 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_S 5
3168 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_M MAKEMASK(0x7, 5)
3169 #define GL_TCVMLR_ERR_STAT_ENT_ID_S 8
3170 #define GL_TCVMLR_ERR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 8)
3171 #define GL_TCVMLR_QCFG 0x000A2010 /* Reset Source: CORER */
3172 #define GL_TCVMLR_QCFG_QID_S 0
3173 #define GL_TCVMLR_QCFG_QID_M MAKEMASK(0x3FFF, 0)
3174 #define GL_TCVMLR_QCFG_OP_S 14
3175 #define GL_TCVMLR_QCFG_OP_M BIT(14)
3176 #define GL_TCVMLR_QCFG_PORT_S 15
3177 #define GL_TCVMLR_QCFG_PORT_M MAKEMASK(0x7, 15)
3178 #define GL_TCVMLR_QCFG_TC_S 18
3179 #define GL_TCVMLR_QCFG_TC_M MAKEMASK(0x1F, 18)
3180 #define GL_TCVMLR_QCFG_RD 0x000A2014 /* Reset Source: CORER */
3181 #define GL_TCVMLR_QCFG_RD_QID_S 0
3182 #define GL_TCVMLR_QCFG_RD_QID_M MAKEMASK(0x3FFF, 0)
3183 #define GL_TCVMLR_QCFG_RD_PORT_S 14
3184 #define GL_TCVMLR_QCFG_RD_PORT_M MAKEMASK(0x7, 14)
3185 #define GL_TCVMLR_QCFG_RD_TC_S 17
3186 #define GL_TCVMLR_QCFG_RD_TC_M MAKEMASK(0x1F, 17)
3187 #define GL_TCVMLR_QCNTR 0x000A200C /* Reset Source: CORER */
3188 #define GL_TCVMLR_QCNTR_CNTR_S 0
3189 #define GL_TCVMLR_QCNTR_CNTR_M MAKEMASK(0x7FFF, 0)
3190 #define GL_TCVMLR_QCTL 0x000A2004 /* Reset Source: CORER */
3191 #define GL_TCVMLR_QCTL_QID_S 0
3192 #define GL_TCVMLR_QCTL_QID_M MAKEMASK(0x3FFF, 0)
3193 #define GL_TCVMLR_QCTL_OP_S 14
3194 #define GL_TCVMLR_QCTL_OP_M BIT(14)
3195 #define GL_TCVMLR_REQ_STAT 0x000A2018 /* Reset Source: CORER */
3196 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_S 0
3197 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3198 #define GL_TCVMLR_REQ_STAT_ENT_ID_S 3
3199 #define GL_TCVMLR_REQ_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3200 #define GL_TCVMLR_REQ_STAT_OP_S 17
3201 #define GL_TCVMLR_REQ_STAT_OP_M BIT(17)
3202 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_S 18
3203 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_M MAKEMASK(0x7, 18)
3204 #define GL_TCVMLR_STAT 0x000A201C /* Reset Source: CORER */
3205 #define GL_TCVMLR_STAT_ENT_TYPE_S 0
3206 #define GL_TCVMLR_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3207 #define GL_TCVMLR_STAT_ENT_ID_S 3
3208 #define GL_TCVMLR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3209 #define GL_TCVMLR_STAT_STATUS_S 17
3210 #define GL_TCVMLR_STAT_STATUS_M MAKEMASK(0x7, 17)
3211 #define GL_XLR_MARKER_TRIG_TCVMLR 0x000A2000 /* Reset Source: CORER */
3212 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_S 0
3213 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3214 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_S 10
3215 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3216 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_S 12
3217 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_M MAKEMASK(0x7, 12)
3218 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_S 16
3219 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3220 #define GL_XLR_MARKER_TRIG_VMLR 0x00093804 /* Reset Source: CORER */
3221 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_S 0
3222 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3223 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_S 10
3224 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3225 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_S 12
3226 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_M MAKEMASK(0x7, 12)
3227 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_S 16
3228 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3229 #define GLGEN_ANA_ABORT_PTYPE 0x0020C21C /* Reset Source: CORER */
3230 #define GLGEN_ANA_ABORT_PTYPE_ABORT_S 0
3231 #define GLGEN_ANA_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3232 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT 0x0020C208 /* Reset Source: CORER */
3233 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3234 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3235 #define GLGEN_ANA_CFG_CTRL 0x0020C104 /* Reset Source: CORER */
3236 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_S 0
3237 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3238 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_S 18
3239 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3240 #define GLGEN_ANA_CFG_CTRL_RESRVED_S 26
3241 #define GLGEN_ANA_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3242 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_S 29
3243 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3244 #define GLGEN_ANA_CFG_HTBL_LU_RESULT 0x0020C158 /* Reset Source: CORER */
3245 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_S 0
3246 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3247 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1
3248 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3249 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_S 4
3250 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3251 #define GLGEN_ANA_CFG_LU_KEY(_i) (0x0020C14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3252 #define GLGEN_ANA_CFG_LU_KEY_MAX_INDEX 2
3253 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_S 0
3254 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3255 #define GLGEN_ANA_CFG_RDDATA(_i) (0x0020C10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3256 #define GLGEN_ANA_CFG_RDDATA_MAX_INDEX 15
3257 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_S 0
3258 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3259 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT 0x0020C15C /* Reset Source: CORER */
3260 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_S 0
3261 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3262 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_S 1
3263 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3264 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_S 4
3265 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3266 #define GLGEN_ANA_CFG_WRDATA 0x0020C108 /* Reset Source: CORER */
3267 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_S 0
3268 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3269 #define GLGEN_ANA_DEF_PTYPE 0x0020C100 /* Reset Source: CORER */
3270 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S 0
3271 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3272 #define GLGEN_ANA_ERR_CTRL 0x0020C220 /* Reset Source: CORER */
3273 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S 0
3274 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3275 #define GLGEN_ANA_FLAG_MAP(_i) (0x0020C000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3276 #define GLGEN_ANA_FLAG_MAP_MAX_INDEX 63
3277 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_S 0
3278 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_M BIT(0)
3279 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_S 1
3280 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3281 #define GLGEN_ANA_INV_NODE_PTYPE 0x0020C210 /* Reset Source: CORER */
3282 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3283 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3284 #define GLGEN_ANA_INV_PTYPE_MARKER 0x0020C218 /* Reset Source: CORER */
3285 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3286 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3287 #define GLGEN_ANA_LAST_PROT_ID(_i) (0x0020C1E4 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
3288 #define GLGEN_ANA_LAST_PROT_ID_MAX_INDEX 5
3289 #define GLGEN_ANA_LAST_PROT_ID_EN_S 0
3290 #define GLGEN_ANA_LAST_PROT_ID_EN_M BIT(0)
3291 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_S 1
3292 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M MAKEMASK(0xFF, 1)
3293 #define GLGEN_ANA_NMPG_KEYMASK(_i) (0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3294 #define GLGEN_ANA_NMPG_KEYMASK_MAX_INDEX 3
3295 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S 0
3296 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3297 #define GLGEN_ANA_NMPG0_HASHKEY(_i) (0x0020C1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3298 #define GLGEN_ANA_NMPG0_HASHKEY_MAX_INDEX 3
3299 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_S 0
3300 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3301 #define GLGEN_ANA_NO_HIT_PG_NM_PG 0x0020C204 /* Reset Source: CORER */
3302 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_S 0
3303 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3304 #define GLGEN_ANA_OUT_OF_PKT 0x0020C200 /* Reset Source: CORER */
3305 #define GLGEN_ANA_OUT_OF_PKT_NPC_S 0
3306 #define GLGEN_ANA_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3307 #define GLGEN_ANA_P2P(_i) (0x0020C160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3308 #define GLGEN_ANA_P2P_MAX_INDEX 15
3309 #define GLGEN_ANA_P2P_TARGET_PROF_S 0
3310 #define GLGEN_ANA_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3311 #define GLGEN_ANA_PG_KEYMASK(_i) (0x0020C1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3312 #define GLGEN_ANA_PG_KEYMASK_MAX_INDEX 3
3313 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_S 0
3314 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3315 #define GLGEN_ANA_PG0_HASHKEY(_i) (0x0020C1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3316 #define GLGEN_ANA_PG0_HASHKEY_MAX_INDEX 3
3317 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_S 0
3318 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3319 #define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */
3320 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3321 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3322 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
3323 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3324 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
3325 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3326 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
3327 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3328 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16
3329 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3330 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
3331 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
3332 #define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */
3333 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0
3334 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3335 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */
3336 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3337 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3338 #define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */
3339 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0
3340 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3341 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S 18
3342 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3343 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S 26
3344 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3345 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S 29
3346 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3347 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT 0x0020D158 /* Reset Source: CORER */
3348 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_S 0
3349 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3350 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1
3351 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3352 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_S 4
3353 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3354 #define GLGEN_ANA_TX_CFG_LU_KEY(_i) (0x0020D14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3355 #define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX 2
3356 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0
3357 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3358 #define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3359 #define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX 15
3360 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0
3361 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3362 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */
3363 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
3364 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3365 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
3366 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3367 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
3368 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3369 #define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */
3370 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0
3371 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3372 #define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */
3373 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0
3374 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3375 #define GLGEN_ANA_TX_DFD_PACE_OUT 0x0020D4CC /* Reset Source: CORER */
3376 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S 0
3377 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M BIT(0)
3378 #define GLGEN_ANA_TX_ERR_CTRL 0x0020D220 /* Reset Source: CORER */
3379 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_S 0
3380 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3381 #define GLGEN_ANA_TX_FLAG_MAP(_i) (0x0020D000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3382 #define GLGEN_ANA_TX_FLAG_MAP_MAX_INDEX 63
3383 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_S 0
3384 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M BIT(0)
3385 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_S 1
3386 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3387 #define GLGEN_ANA_TX_INV_NODE_PTYPE 0x0020D210 /* Reset Source: CORER */
3388 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3389 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3390 #define GLGEN_ANA_TX_INV_PROT_ID 0x0020D214 /* Reset Source: CORER */
3391 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_S 0
3392 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_M MAKEMASK(0xFF, 0)
3393 #define GLGEN_ANA_TX_INV_PTYPE_MARKER 0x0020D218 /* Reset Source: CORER */
3394 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3395 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3396 #define GLGEN_ANA_TX_NMPG_KEYMASK(_i) (0x0020D1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3397 #define GLGEN_ANA_TX_NMPG_KEYMASK_MAX_INDEX 3
3398 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_S 0
3399 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3400 #define GLGEN_ANA_TX_NMPG0_HASHKEY(_i) (0x0020D1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3401 #define GLGEN_ANA_TX_NMPG0_HASHKEY_MAX_INDEX 3
3402 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_S 0
3403 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3404 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG 0x0020D204 /* Reset Source: CORER */
3405 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_S 0
3406 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3407 #define GLGEN_ANA_TX_P2P(_i) (0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3408 #define GLGEN_ANA_TX_P2P_MAX_INDEX 15
3409 #define GLGEN_ANA_TX_P2P_TARGET_PROF_S 0
3410 #define GLGEN_ANA_TX_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3411 #define GLGEN_ANA_TX_PG_KEYMASK(_i) (0x0020D1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3412 #define GLGEN_ANA_TX_PG_KEYMASK_MAX_INDEX 3
3413 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_S 0
3414 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3415 #define GLGEN_ANA_TX_PG0_HASHKEY(_i) (0x0020D1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3416 #define GLGEN_ANA_TX_PG0_HASHKEY_MAX_INDEX 3
3417 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_S 0
3418 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3419 #define GLGEN_ANA_TX_PROFIL_CTRL 0x0020D1FC /* Reset Source: CORER */
3420 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3421 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3422 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
3423 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3424 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
3425 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3426 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
3427 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3428 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_S 16
3429 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3430 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
3431 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
3432 #define GLGEN_ASSERT_HLP 0x000B81E4 /* Reset Source: POR */
3433 #define GLGEN_ASSERT_HLP_CORE_ON_RST_S 0
3434 #define GLGEN_ASSERT_HLP_CORE_ON_RST_M BIT(0)
3435 #define GLGEN_ASSERT_HLP_FULL_ON_RST_S 1
3436 #define GLGEN_ASSERT_HLP_FULL_ON_RST_M BIT(1)
3437 #define GLGEN_CLKSTAT 0x000B8184 /* Reset Source: POR */
3438 #define GLGEN_CLKSTAT_U_CLK_SPEED_S 0
3439 #define GLGEN_CLKSTAT_U_CLK_SPEED_M MAKEMASK(0x7, 0)
3440 #define GLGEN_CLKSTAT_L_CLK_SPEED_S 3
3441 #define GLGEN_CLKSTAT_L_CLK_SPEED_M MAKEMASK(0x7, 3)
3442 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_S 6
3443 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_M MAKEMASK(0x7, 6)
3444 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_S 9
3445 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_M MAKEMASK(0x7, 9)
3446 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_S 12
3447 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_M MAKEMASK(0x7, 12)
3448 #define GLGEN_CLKSTAT_PE_CLK_SPEED_S 18
3449 #define GLGEN_CLKSTAT_PE_CLK_SPEED_M MAKEMASK(0x7, 18)
3450 #define GLGEN_CLKSTAT_SRC 0x000B826C /* Reset Source: POR */
3451 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_S 0
3452 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_M MAKEMASK(0x3, 0)
3453 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_S 2
3454 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_M MAKEMASK(0x3, 2)
3455 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4
3456 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M MAKEMASK(0x3, 4)
3457 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_S 6
3458 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_M MAKEMASK(0x3, 6)
3459 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_S 8
3460 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_M MAKEMASK(0xF, 8)
3461 #define GLGEN_ECC_ERR_INT_TOG_MASK_H 0x00093A00 /* Reset Source: CORER */
3462 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_S 0
3463 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3464 #define GLGEN_ECC_ERR_INT_TOG_MASK_L 0x000939FC /* Reset Source: CORER */
3465 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_S 0
3466 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3467 #define GLGEN_ECC_ERR_RST_MASK_H 0x000939F8 /* Reset Source: CORER */
3468 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_S 0
3469 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3470 #define GLGEN_ECC_ERR_RST_MASK_L 0x000939F4 /* Reset Source: CORER */
3471 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_S 0
3472 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3473 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: POR */
3474 #define GLGEN_GPIO_CTL_MAX_INDEX 6
3475 #define GLGEN_GPIO_CTL_IN_VALUE_S 0
3476 #define GLGEN_GPIO_CTL_IN_VALUE_M BIT(0)
3477 #define GLGEN_GPIO_CTL_IN_TRANSIT_S 1
3478 #define GLGEN_GPIO_CTL_IN_TRANSIT_M BIT(1)
3479 #define GLGEN_GPIO_CTL_OUT_VALUE_S 2
3480 #define GLGEN_GPIO_CTL_OUT_VALUE_M BIT(2)
3481 #define GLGEN_GPIO_CTL_NO_P_UP_S 3
3482 #define GLGEN_GPIO_CTL_NO_P_UP_M BIT(3)
3483 #define GLGEN_GPIO_CTL_PIN_DIR_S 4
3484 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
3485 #define GLGEN_GPIO_CTL_TRI_CTL_S 5
3486 #define GLGEN_GPIO_CTL_TRI_CTL_M BIT(5)
3487 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8
3488 #define GLGEN_GPIO_CTL_PIN_FUNC_M MAKEMASK(0xF, 8)
3489 #define GLGEN_GPIO_CTL_INT_MODE_S 12
3490 #define GLGEN_GPIO_CTL_INT_MODE_M MAKEMASK(0x3, 12)
3491 #define GLGEN_MARKER_COUNT 0x000939E8 /* Reset Source: CORER */
3492 #define GLGEN_MARKER_COUNT_MARKER_COUNT_S 0
3493 #define GLGEN_MARKER_COUNT_MARKER_COUNT_M MAKEMASK(0xFF, 0)
3494 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_S 31
3495 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_M BIT(31)
3496 #define GLGEN_RSTAT 0x000B8188 /* Reset Source: POR */
3497 #define GLGEN_RSTAT_DEVSTATE_S 0
3498 #define GLGEN_RSTAT_DEVSTATE_M MAKEMASK(0x3, 0)
3499 #define GLGEN_RSTAT_RESET_TYPE_S 2
3500 #define GLGEN_RSTAT_RESET_TYPE_M MAKEMASK(0x3, 2)
3501 #define GLGEN_RSTAT_CORERCNT_S 4
3502 #define GLGEN_RSTAT_CORERCNT_M MAKEMASK(0x3, 4)
3503 #define GLGEN_RSTAT_GLOBRCNT_S 6
3504 #define GLGEN_RSTAT_GLOBRCNT_M MAKEMASK(0x3, 6)
3505 #define GLGEN_RSTAT_EMPRCNT_S 8
3506 #define GLGEN_RSTAT_EMPRCNT_M MAKEMASK(0x3, 8)
3507 #define GLGEN_RSTAT_TIME_TO_RST_S 10
3508 #define GLGEN_RSTAT_TIME_TO_RST_M MAKEMASK(0x3F, 10)
3509 #define GLGEN_RSTAT_RTRIG_FLR_S 16
3510 #define GLGEN_RSTAT_RTRIG_FLR_M BIT(16)
3511 #define GLGEN_RSTAT_RTRIG_ECC_S 17
3512 #define GLGEN_RSTAT_RTRIG_ECC_M BIT(17)
3513 #define GLGEN_RSTAT_RTRIG_FW_AUX_S 18
3514 #define GLGEN_RSTAT_RTRIG_FW_AUX_M BIT(18)
3515 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
3516 #define GLGEN_RSTCTL_GRSTDEL_S 0
3517 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, 0)
3518 #define GLGEN_RSTCTL_ECC_RST_ENA_S 8
3519 #define GLGEN_RSTCTL_ECC_RST_ENA_M BIT(8)
3520 #define GLGEN_RSTCTL_ECC_RT_EN_S 30
3521 #define GLGEN_RSTCTL_ECC_RT_EN_M BIT(30)
3522 #define GLGEN_RSTCTL_FLR_RT_EN_S 31
3523 #define GLGEN_RSTCTL_FLR_RT_EN_M BIT(31)
3524 #define GLGEN_RTRIG 0x000B8190 /* Reset Source: CORER */
3525 #define GLGEN_RTRIG_CORER_S 0
3526 #define GLGEN_RTRIG_CORER_M BIT(0)
3527 #define GLGEN_RTRIG_GLOBR_S 1
3528 #define GLGEN_RTRIG_GLOBR_M BIT(1)
3529 #define GLGEN_RTRIG_EMPFWR_S 2
3530 #define GLGEN_RTRIG_EMPFWR_M BIT(2)
3531 #define GLGEN_STAT 0x000B612C /* Reset Source: POR */
3532 #define GLGEN_STAT_RSVD4FW_S 0
3533 #define GLGEN_STAT_RSVD4FW_M MAKEMASK(0xFF, 0)
3534 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3535 #define GLGEN_VFLRSTAT_MAX_INDEX 7
3536 #define GLGEN_VFLRSTAT_VFLRS_S 0
3537 #define GLGEN_VFLRSTAT_VFLRS_M MAKEMASK(0xFFFFFFFF, 0)
3538 #define GLGEN_XLR_MSK2HLP_RDY 0x000939F0 /* Reset Source: CORER */
3539 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_S 0
3540 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0)
3541 #define GLGEN_XLR_TRNS_WAIT_COUNT 0x000939EC /* Reset Source: CORER */
3542 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_S 0
3543 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0)
3544 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_S 8
3545 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8)
3546 #define GLVFGEN_TIMER 0x000B8214 /* Reset Source: POR */
3547 #define GLVFGEN_TIMER_GTIME_S 0
3548 #define GLVFGEN_TIMER_GTIME_M MAKEMASK(0xFFFFFFFF, 0)
3549 #define PFGEN_CTRL 0x00091000 /* Reset Source: CORER */
3550 #define PFGEN_CTRL_PFSWR_S 0
3551 #define PFGEN_CTRL_PFSWR_M BIT(0)
3552 #define PFGEN_DRUN 0x00091180 /* Reset Source: CORER */
3553 #define PFGEN_DRUN_DRVUNLD_S 0
3554 #define PFGEN_DRUN_DRVUNLD_M BIT(0)
3555 #define PFGEN_PFRSTAT 0x00091080 /* Reset Source: CORER */
3556 #define PFGEN_PFRSTAT_PFRD_S 0
3557 #define PFGEN_PFRSTAT_PFRD_M BIT(0)
3558 #define PFGEN_PORTNUM 0x001D2400 /* Reset Source: CORER */
3559 #define PFGEN_PORTNUM_PORT_NUM_S 0
3560 #define PFGEN_PORTNUM_PORT_NUM_M MAKEMASK(0x7, 0)
3561 #define PFGEN_STATE 0x00088000 /* Reset Source: CORER */
3562 #define PFGEN_STATE_PFPEEN_S 0
3563 #define PFGEN_STATE_PFPEEN_M BIT(0)
3564 #define PFGEN_STATE_RSVD_S 1
3565 #define PFGEN_STATE_RSVD_M BIT(1)
3566 #define PFGEN_STATE_PFLINKEN_S 2
3567 #define PFGEN_STATE_PFLINKEN_M BIT(2)
3568 #define PFGEN_STATE_PFSCEN_S 3
3569 #define PFGEN_STATE_PFSCEN_M BIT(3)
3570 #define PRT_TCVMLR_DRAIN_CNTR 0x000A21C0 /* Reset Source: CORER */
3571 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_S 0
3572 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_M MAKEMASK(0x3FFF, 0)
3573 #define PRTGEN_CNF 0x000B8120 /* Reset Source: POR */
3574 #define PRTGEN_CNF_PORT_DIS_S 0
3575 #define PRTGEN_CNF_PORT_DIS_M BIT(0)
3576 #define PRTGEN_CNF_ALLOW_PORT_DIS_S 1
3577 #define PRTGEN_CNF_ALLOW_PORT_DIS_M BIT(1)
3578 #define PRTGEN_CNF_EMP_PORT_DIS_S 2
3579 #define PRTGEN_CNF_EMP_PORT_DIS_M BIT(2)
3580 #define PRTGEN_CNF2 0x000B8160 /* Reset Source: POR */
3581 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_S 0
3582 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M BIT(0)
3583 #define PRTGEN_CNF3 0x000B8280 /* Reset Source: POR */
3584 #define PRTGEN_CNF3_PORT_STAGERING_EN_S 0
3585 #define PRTGEN_CNF3_PORT_STAGERING_EN_M BIT(0)
3586 #define PRTGEN_STATUS 0x000B8100 /* Reset Source: POR */
3587 #define PRTGEN_STATUS_PORT_VALID_S 0
3588 #define PRTGEN_STATUS_PORT_VALID_M BIT(0)
3589 #define PRTGEN_STATUS_PORT_ACTIVE_S 1
3590 #define PRTGEN_STATUS_PORT_ACTIVE_M BIT(1)
3591 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: VFR */
3592 #define VFGEN_RSTAT_MAX_INDEX 255
3593 #define VFGEN_RSTAT_VFR_STATE_S 0
3594 #define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, 0)
3595 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3596 #define VPGEN_VFRSTAT_MAX_INDEX 255
3597 #define VPGEN_VFRSTAT_VFRD_S 0
3598 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
3599 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3600 #define VPGEN_VFRTRIG_MAX_INDEX 255
3601 #define VPGEN_VFRTRIG_VFSWR_S 0
3602 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
3603 #define VSIGEN_RSTAT(_VSI) (0x00092800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3604 #define VSIGEN_RSTAT_MAX_INDEX 767
3605 #define VSIGEN_RSTAT_VMRD_S 0
3606 #define VSIGEN_RSTAT_VMRD_M BIT(0)
3607 #define VSIGEN_RTRIG(_VSI) (0x00091800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3608 #define VSIGEN_RTRIG_MAX_INDEX 767
3609 #define VSIGEN_RTRIG_VMSWR_S 0
3610 #define VSIGEN_RTRIG_VMSWR_M BIT(0)
3611 #define GLHMC_APBVTINUSEBASE(_i) (0x00524A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3612 #define GLHMC_APBVTINUSEBASE_MAX_INDEX 7
3613 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_S 0
3614 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
3615 #define GLHMC_CEQPART(_i) (0x005031C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3616 #define GLHMC_CEQPART_MAX_INDEX 7
3617 #define GLHMC_CEQPART_PMCEQBASE_S 0
3618 #define GLHMC_CEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
3619 #define GLHMC_CEQPART_PMCEQSIZE_S 16
3620 #define GLHMC_CEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
3621 #define GLHMC_DBCQMAX 0x005220F0 /* Reset Source: CORER */
3622 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_S 0
3623 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_M MAKEMASK(0xFFFFF, 0)
3624 #define GLHMC_DBCQPART(_i) (0x00503180 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3625 #define GLHMC_DBCQPART_MAX_INDEX 7
3626 #define GLHMC_DBCQPART_PMDBCQBASE_S 0
3627 #define GLHMC_DBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
3628 #define GLHMC_DBCQPART_PMDBCQSIZE_S 16
3629 #define GLHMC_DBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
3630 #define GLHMC_DBQPMAX 0x005220EC /* Reset Source: CORER */
3631 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_S 0
3632 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_M MAKEMASK(0x7FFFF, 0)
3633 #define GLHMC_DBQPPART(_i) (0x005044C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3634 #define GLHMC_DBQPPART_MAX_INDEX 7
3635 #define GLHMC_DBQPPART_PMDBQPBASE_S 0
3636 #define GLHMC_DBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
3637 #define GLHMC_DBQPPART_PMDBQPSIZE_S 16
3638 #define GLHMC_DBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
3639 #define GLHMC_FSIAVBASE(_i) (0x00525600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3640 #define GLHMC_FSIAVBASE_MAX_INDEX 7
3641 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_S 0
3642 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
3643 #define GLHMC_FSIAVCNT(_i) (0x00525700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3644 #define GLHMC_FSIAVCNT_MAX_INDEX 7
3645 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_S 0
3646 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
3647 #define GLHMC_FSIAVMAX 0x00522068 /* Reset Source: CORER */
3648 #define GLHMC_FSIAVMAX_PMFSIAVMAX_S 0
3649 #define GLHMC_FSIAVMAX_PMFSIAVMAX_M MAKEMASK(0x3FFFF, 0)
3650 #define GLHMC_FSIAVOBJSZ 0x00522064 /* Reset Source: CORER */
3651 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S 0
3652 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M MAKEMASK(0xF, 0)
3653 #define GLHMC_FSIMCBASE(_i) (0x00526000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3654 #define GLHMC_FSIMCBASE_MAX_INDEX 7
3655 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_S 0
3656 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
3657 #define GLHMC_FSIMCCNT(_i) (0x00526100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3658 #define GLHMC_FSIMCCNT_MAX_INDEX 7
3659 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_S 0
3660 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
3661 #define GLHMC_FSIMCMAX 0x00522060 /* Reset Source: CORER */
3662 #define GLHMC_FSIMCMAX_PMFSIMCMAX_S 0
3663 #define GLHMC_FSIMCMAX_PMFSIMCMAX_M MAKEMASK(0x3FFF, 0)
3664 #define GLHMC_FSIMCOBJSZ 0x0052205C /* Reset Source: CORER */
3665 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S 0
3666 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M MAKEMASK(0xF, 0)
3667 #define GLHMC_FWPDINV 0x0052207C /* Reset Source: CORER */
3668 #define GLHMC_FWPDINV_PMSDIDX_S 0
3669 #define GLHMC_FWPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
3670 #define GLHMC_FWPDINV_PMSDPARTSEL_S 15
3671 #define GLHMC_FWPDINV_PMSDPARTSEL_M BIT(15)
3672 #define GLHMC_FWPDINV_PMPDIDX_S 16
3673 #define GLHMC_FWPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
3674 #define GLHMC_FWPDINV_FPMAT 0x0010207C /* Reset Source: CORER */
3675 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_S 0
3676 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
3677 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S 15
3678 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
3679 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_S 16
3680 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
3681 #define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */
3682 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0
3683 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3684 #define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */
3685 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
3686 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3687 #define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */
3688 #define GLHMC_FWSDDATALOW_PMSDVALID_S 0
3689 #define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
3690 #define GLHMC_FWSDDATALOW_PMSDTYPE_S 1
3691 #define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1)
3692 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S 2
3693 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3694 #define GLHMC_FWSDDATALOW_PMSDDATALOW_S 12
3695 #define GLHMC_FWSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3696 #define GLHMC_FWSDDATALOW_FPMAT 0x00102074 /* Reset Source: CORER */
3697 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_S 0
3698 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
3699 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_S 1
3700 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
3701 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_S 2
3702 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3703 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_S 12
3704 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3705 #define GLHMC_PEARPBASE(_i) (0x00524800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3706 #define GLHMC_PEARPBASE_MAX_INDEX 7
3707 #define GLHMC_PEARPBASE_FPMPEARPBASE_S 0
3708 #define GLHMC_PEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
3709 #define GLHMC_PEARPCNT(_i) (0x00524900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3710 #define GLHMC_PEARPCNT_MAX_INDEX 7
3711 #define GLHMC_PEARPCNT_FPMPEARPCNT_S 0
3712 #define GLHMC_PEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3713 #define GLHMC_PEARPMAX 0x00522038 /* Reset Source: CORER */
3714 #define GLHMC_PEARPMAX_PMPEARPMAX_S 0
3715 #define GLHMC_PEARPMAX_PMPEARPMAX_M MAKEMASK(0x1FFFF, 0)
3716 #define GLHMC_PEARPOBJSZ 0x00522034 /* Reset Source: CORER */
3717 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S 0
3718 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M MAKEMASK(0x7, 0)
3719 #define GLHMC_PECQBASE(_i) (0x00524200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3720 #define GLHMC_PECQBASE_MAX_INDEX 7
3721 #define GLHMC_PECQBASE_FPMPECQBASE_S 0
3722 #define GLHMC_PECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
3723 #define GLHMC_PECQCNT(_i) (0x00524300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3724 #define GLHMC_PECQCNT_MAX_INDEX 7
3725 #define GLHMC_PECQCNT_FPMPECQCNT_S 0
3726 #define GLHMC_PECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
3727 #define GLHMC_PECQOBJSZ 0x00522020 /* Reset Source: CORER */
3728 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_S 0
3729 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_M MAKEMASK(0xF, 0)
3730 #define GLHMC_PEHDRBASE(_i) (0x00526200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3731 #define GLHMC_PEHDRBASE_MAX_INDEX 7
3732 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S 0
3733 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
3734 #define GLHMC_PEHDRCNT(_i) (0x00526300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3735 #define GLHMC_PEHDRCNT_MAX_INDEX 7
3736 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S 0
3737 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
3738 #define GLHMC_PEHDRMAX 0x00522008 /* Reset Source: CORER */
3739 #define GLHMC_PEHDRMAX_PMPEHDRMAX_S 0
3740 #define GLHMC_PEHDRMAX_PMPEHDRMAX_M MAKEMASK(0x7FFFF, 0)
3741 #define GLHMC_PEHDRMAX_RSVD_S 19
3742 #define GLHMC_PEHDRMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3743 #define GLHMC_PEHDROBJSZ 0x00522004 /* Reset Source: CORER */
3744 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S 0
3745 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M MAKEMASK(0xF, 0)
3746 #define GLHMC_PEHDROBJSZ_RSVD_S 4
3747 #define GLHMC_PEHDROBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3748 #define GLHMC_PEHTCNT(_i) (0x00524700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3749 #define GLHMC_PEHTCNT_MAX_INDEX 7
3750 #define GLHMC_PEHTCNT_FPMPEHTCNT_S 0
3751 #define GLHMC_PEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3752 #define GLHMC_PEHTCNT_FPMAT(_i) (0x00104700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3753 #define GLHMC_PEHTCNT_FPMAT_MAX_INDEX 7
3754 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_S 0
3755 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3756 #define GLHMC_PEHTEBASE(_i) (0x00524600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3757 #define GLHMC_PEHTEBASE_MAX_INDEX 7
3758 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_S 0
3759 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3760 #define GLHMC_PEHTEBASE_FPMAT(_i) (0x00104600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3761 #define GLHMC_PEHTEBASE_FPMAT_MAX_INDEX 7
3762 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
3763 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3764 #define GLHMC_PEHTEOBJSZ 0x0052202C /* Reset Source: CORER */
3765 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S 0
3766 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3767 #define GLHMC_PEHTEOBJSZ_FPMAT 0x0010202C /* Reset Source: CORER */
3768 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S 0
3769 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3770 #define GLHMC_PEHTMAX 0x00522030 /* Reset Source: CORER */
3771 #define GLHMC_PEHTMAX_PMPEHTMAX_S 0
3772 #define GLHMC_PEHTMAX_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3773 #define GLHMC_PEHTMAX_FPMAT 0x00102030 /* Reset Source: CORER */
3774 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_S 0
3775 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3776 #define GLHMC_PEMDBASE(_i) (0x00526400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3777 #define GLHMC_PEMDBASE_MAX_INDEX 7
3778 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_S 0
3779 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
3780 #define GLHMC_PEMDCNT(_i) (0x00526500 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3781 #define GLHMC_PEMDCNT_MAX_INDEX 7
3782 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_S 0
3783 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
3784 #define GLHMC_PEMDMAX 0x00522010 /* Reset Source: CORER */
3785 #define GLHMC_PEMDMAX_PMPEMDMAX_S 0
3786 #define GLHMC_PEMDMAX_PMPEMDMAX_M MAKEMASK(0xFFFFFF, 0)
3787 #define GLHMC_PEMDMAX_RSVD_S 24
3788 #define GLHMC_PEMDMAX_RSVD_M MAKEMASK(0xFF, 24)
3789 #define GLHMC_PEMDOBJSZ 0x0052200C /* Reset Source: CORER */
3790 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_S 0
3791 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_M MAKEMASK(0xF, 0)
3792 #define GLHMC_PEMDOBJSZ_RSVD_S 4
3793 #define GLHMC_PEMDOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3794 #define GLHMC_PEMRBASE(_i) (0x00524C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3795 #define GLHMC_PEMRBASE_MAX_INDEX 7
3796 #define GLHMC_PEMRBASE_FPMPEMRBASE_S 0
3797 #define GLHMC_PEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
3798 #define GLHMC_PEMRCNT(_i) (0x00524D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3799 #define GLHMC_PEMRCNT_MAX_INDEX 7
3800 #define GLHMC_PEMRCNT_FPMPEMRSZ_S 0
3801 #define GLHMC_PEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
3802 #define GLHMC_PEMRMAX 0x00522040 /* Reset Source: CORER */
3803 #define GLHMC_PEMRMAX_PMPEMRMAX_S 0
3804 #define GLHMC_PEMRMAX_PMPEMRMAX_M MAKEMASK(0x7FFFFF, 0)
3805 #define GLHMC_PEMROBJSZ 0x0052203C /* Reset Source: CORER */
3806 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S 0
3807 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M MAKEMASK(0xF, 0)
3808 #define GLHMC_PEOOISCBASE(_i) (0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3809 #define GLHMC_PEOOISCBASE_MAX_INDEX 7
3810 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S 0
3811 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
3812 #define GLHMC_PEOOISCCNT(_i) (0x00526700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3813 #define GLHMC_PEOOISCCNT_MAX_INDEX 7
3814 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S 0
3815 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
3816 #define GLHMC_PEOOISCFFLBASE(_i) (0x00526C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3817 #define GLHMC_PEOOISCFFLBASE_MAX_INDEX 7
3818 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
3819 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3820 #define GLHMC_PEOOISCFFLCNT_PMAT(_i) (0x00526D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3821 #define GLHMC_PEOOISCFFLCNT_PMAT_MAX_INDEX 7
3822 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_S 0
3823 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3824 #define GLHMC_PEOOISCFFLMAX 0x005220A4 /* Reset Source: CORER */
3825 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S 0
3826 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M MAKEMASK(0x7FFFF, 0)
3827 #define GLHMC_PEOOISCFFLMAX_RSVD_S 19
3828 #define GLHMC_PEOOISCFFLMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3829 #define GLHMC_PEOOISCMAX 0x00522018 /* Reset Source: CORER */
3830 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_S 0
3831 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_M MAKEMASK(0x7FFFF, 0)
3832 #define GLHMC_PEOOISCMAX_RSVD_S 19
3833 #define GLHMC_PEOOISCMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3834 #define GLHMC_PEOOISCOBJSZ 0x00522014 /* Reset Source: CORER */
3835 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S 0
3836 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M MAKEMASK(0xF, 0)
3837 #define GLHMC_PEOOISCOBJSZ_RSVD_S 4
3838 #define GLHMC_PEOOISCOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3839 #define GLHMC_PEPBLBASE(_i) (0x00525800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3840 #define GLHMC_PEPBLBASE_MAX_INDEX 7
3841 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_S 0
3842 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
3843 #define GLHMC_PEPBLCNT(_i) (0x00525900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3844 #define GLHMC_PEPBLCNT_MAX_INDEX 7
3845 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_S 0
3846 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3847 #define GLHMC_PEPBLMAX 0x0052206C /* Reset Source: CORER */
3848 #define GLHMC_PEPBLMAX_PMPEPBLMAX_S 0
3849 #define GLHMC_PEPBLMAX_PMPEPBLMAX_M MAKEMASK(0x1FFFFFFF, 0)
3850 #define GLHMC_PEQ1BASE(_i) (0x00525200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3851 #define GLHMC_PEQ1BASE_MAX_INDEX 7
3852 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_S 0
3853 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
3854 #define GLHMC_PEQ1CNT(_i) (0x00525300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3855 #define GLHMC_PEQ1CNT_MAX_INDEX 7
3856 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_S 0
3857 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
3858 #define GLHMC_PEQ1FLBASE(_i) (0x00525400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3859 #define GLHMC_PEQ1FLBASE_MAX_INDEX 7
3860 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S 0
3861 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
3862 #define GLHMC_PEQ1FLMAX 0x00522058 /* Reset Source: CORER */
3863 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S 0
3864 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M MAKEMASK(0x3FFFFFF, 0)
3865 #define GLHMC_PEQ1MAX 0x00522054 /* Reset Source: CORER */
3866 #define GLHMC_PEQ1MAX_PMPEQ1MAX_S 0
3867 #define GLHMC_PEQ1MAX_PMPEQ1MAX_M MAKEMASK(0xFFFFFFF, 0)
3868 #define GLHMC_PEQ1OBJSZ 0x00522050 /* Reset Source: CORER */
3869 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S 0
3870 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M MAKEMASK(0xF, 0)
3871 #define GLHMC_PEQPBASE(_i) (0x00524000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3872 #define GLHMC_PEQPBASE_MAX_INDEX 7
3873 #define GLHMC_PEQPBASE_FPMPEQPBASE_S 0
3874 #define GLHMC_PEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
3875 #define GLHMC_PEQPCNT(_i) (0x00524100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3876 #define GLHMC_PEQPCNT_MAX_INDEX 7
3877 #define GLHMC_PEQPCNT_FPMPEQPCNT_S 0
3878 #define GLHMC_PEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3879 #define GLHMC_PEQPOBJSZ 0x0052201C /* Reset Source: CORER */
3880 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S 0
3881 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M MAKEMASK(0xF, 0)
3882 #define GLHMC_PERRFBASE(_i) (0x00526800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3883 #define GLHMC_PERRFBASE_MAX_INDEX 7
3884 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_S 0
3885 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
3886 #define GLHMC_PERRFCNT(_i) (0x00526900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3887 #define GLHMC_PERRFCNT_MAX_INDEX 7
3888 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_S 0
3889 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
3890 #define GLHMC_PERRFFLBASE(_i) (0x00526A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3891 #define GLHMC_PERRFFLBASE_MAX_INDEX 7
3892 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S 0
3893 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3894 #define GLHMC_PERRFFLCNT_PMAT(_i) (0x00526B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3895 #define GLHMC_PERRFFLCNT_PMAT_MAX_INDEX 7
3896 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S 0
3897 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3898 #define GLHMC_PERRFFLMAX 0x005220A0 /* Reset Source: CORER */
3899 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_S 0
3900 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_M MAKEMASK(0x3FFFFFF, 0)
3901 #define GLHMC_PERRFFLMAX_RSVD_S 26
3902 #define GLHMC_PERRFFLMAX_RSVD_M MAKEMASK(0x3F, 26)
3903 #define GLHMC_PERRFMAX 0x0052209C /* Reset Source: CORER */
3904 #define GLHMC_PERRFMAX_PMPERRFMAX_S 0
3905 #define GLHMC_PERRFMAX_PMPERRFMAX_M MAKEMASK(0xFFFFFFF, 0)
3906 #define GLHMC_PERRFMAX_RSVD_S 28
3907 #define GLHMC_PERRFMAX_RSVD_M MAKEMASK(0xF, 28)
3908 #define GLHMC_PERRFOBJSZ 0x00522098 /* Reset Source: CORER */
3909 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S 0
3910 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M MAKEMASK(0xF, 0)
3911 #define GLHMC_PERRFOBJSZ_RSVD_S 4
3912 #define GLHMC_PERRFOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3913 #define GLHMC_PETIMERBASE(_i) (0x00525A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3914 #define GLHMC_PETIMERBASE_MAX_INDEX 7
3915 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_S 0
3916 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
3917 #define GLHMC_PETIMERCNT(_i) (0x00525B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3918 #define GLHMC_PETIMERCNT_MAX_INDEX 7
3919 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_S 0
3920 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
3921 #define GLHMC_PETIMERMAX 0x00522084 /* Reset Source: CORER */
3922 #define GLHMC_PETIMERMAX_PMPETIMERMAX_S 0
3923 #define GLHMC_PETIMERMAX_PMPETIMERMAX_M MAKEMASK(0x1FFFFFFF, 0)
3924 #define GLHMC_PETIMEROBJSZ 0x00522080 /* Reset Source: CORER */
3925 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S 0
3926 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M MAKEMASK(0xF, 0)
3927 #define GLHMC_PEXFBASE(_i) (0x00524E00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3928 #define GLHMC_PEXFBASE_MAX_INDEX 7
3929 #define GLHMC_PEXFBASE_FPMPEXFBASE_S 0
3930 #define GLHMC_PEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
3931 #define GLHMC_PEXFCNT(_i) (0x00524F00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3932 #define GLHMC_PEXFCNT_MAX_INDEX 7
3933 #define GLHMC_PEXFCNT_FPMPEXFCNT_S 0
3934 #define GLHMC_PEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
3935 #define GLHMC_PEXFFLBASE(_i) (0x00525000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3936 #define GLHMC_PEXFFLBASE_MAX_INDEX 7
3937 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S 0
3938 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
3939 #define GLHMC_PEXFFLMAX 0x0052204C /* Reset Source: CORER */
3940 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S 0
3941 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M MAKEMASK(0xFFFFFFF, 0)
3942 #define GLHMC_PEXFMAX 0x00522048 /* Reset Source: CORER */
3943 #define GLHMC_PEXFMAX_PMPEXFMAX_S 0
3944 #define GLHMC_PEXFMAX_PMPEXFMAX_M MAKEMASK(0xFFFFFFF, 0)
3945 #define GLHMC_PEXFOBJSZ 0x00522044 /* Reset Source: CORER */
3946 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S 0
3947 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M MAKEMASK(0xF, 0)
3948 #define GLHMC_PFPESDPART(_i) (0x00520880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3949 #define GLHMC_PFPESDPART_MAX_INDEX 7
3950 #define GLHMC_PFPESDPART_PMSDBASE_S 0
3951 #define GLHMC_PFPESDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
3952 #define GLHMC_PFPESDPART_PMSDSIZE_S 16
3953 #define GLHMC_PFPESDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3954 #define GLHMC_PFPESDPART_FPMAT(_i) (0x00100880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3955 #define GLHMC_PFPESDPART_FPMAT_MAX_INDEX 7
3956 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_S 0
3957 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
3958 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_S 16
3959 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3960 #define GLHMC_SDPART(_i) (0x00520800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3961 #define GLHMC_SDPART_MAX_INDEX 7
3962 #define GLHMC_SDPART_PMSDBASE_S 0
3963 #define GLHMC_SDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
3964 #define GLHMC_SDPART_PMSDSIZE_S 16
3965 #define GLHMC_SDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3966 #define GLHMC_SDPART_FPMAT(_i) (0x00100800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3967 #define GLHMC_SDPART_FPMAT_MAX_INDEX 7
3968 #define GLHMC_SDPART_FPMAT_PMSDBASE_S 0
3969 #define GLHMC_SDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
3970 #define GLHMC_SDPART_FPMAT_PMSDSIZE_S 16
3971 #define GLHMC_SDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3972 #define GLHMC_VFAPBVTINUSEBASE(_i) (0x0052CA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3973 #define GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
3974 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_S 0
3975 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
3976 #define GLHMC_VFCEQPART(_i) (0x00502F00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3977 #define GLHMC_VFCEQPART_MAX_INDEX 31
3978 #define GLHMC_VFCEQPART_PMCEQBASE_S 0
3979 #define GLHMC_VFCEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
3980 #define GLHMC_VFCEQPART_PMCEQSIZE_S 16
3981 #define GLHMC_VFCEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
3982 #define GLHMC_VFDBCQPART(_i) (0x00502E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3983 #define GLHMC_VFDBCQPART_MAX_INDEX 31
3984 #define GLHMC_VFDBCQPART_PMDBCQBASE_S 0
3985 #define GLHMC_VFDBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
3986 #define GLHMC_VFDBCQPART_PMDBCQSIZE_S 16
3987 #define GLHMC_VFDBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
3988 #define GLHMC_VFDBQPPART(_i) (0x00504520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3989 #define GLHMC_VFDBQPPART_MAX_INDEX 31
3990 #define GLHMC_VFDBQPPART_PMDBQPBASE_S 0
3991 #define GLHMC_VFDBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
3992 #define GLHMC_VFDBQPPART_PMDBQPSIZE_S 16
3993 #define GLHMC_VFDBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
3994 #define GLHMC_VFFSIAVBASE(_i) (0x0052D600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3995 #define GLHMC_VFFSIAVBASE_MAX_INDEX 31
3996 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_S 0
3997 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
3998 #define GLHMC_VFFSIAVCNT(_i) (0x0052D700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3999 #define GLHMC_VFFSIAVCNT_MAX_INDEX 31
4000 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_S 0
4001 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
4002 #define GLHMC_VFFSIMCBASE(_i) (0x0052E000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4003 #define GLHMC_VFFSIMCBASE_MAX_INDEX 31
4004 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_S 0
4005 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
4006 #define GLHMC_VFFSIMCCNT(_i) (0x0052E100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4007 #define GLHMC_VFFSIMCCNT_MAX_INDEX 31
4008 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_S 0
4009 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
4010 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4011 #define GLHMC_VFPDINV_MAX_INDEX 31
4012 #define GLHMC_VFPDINV_PMSDIDX_S 0
4013 #define GLHMC_VFPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
4014 #define GLHMC_VFPDINV_PMSDPARTSEL_S 15
4015 #define GLHMC_VFPDINV_PMSDPARTSEL_M BIT(15)
4016 #define GLHMC_VFPDINV_PMPDIDX_S 16
4017 #define GLHMC_VFPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
4018 #define GLHMC_VFPDINV_FPMAT(_i) (0x00108300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4019 #define GLHMC_VFPDINV_FPMAT_MAX_INDEX 31
4020 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_S 0
4021 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4022 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_S 15
4023 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
4024 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_S 16
4025 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
4026 #define GLHMC_VFPEARPBASE(_i) (0x0052C800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4027 #define GLHMC_VFPEARPBASE_MAX_INDEX 31
4028 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_S 0
4029 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
4030 #define GLHMC_VFPEARPCNT(_i) (0x0052C900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4031 #define GLHMC_VFPEARPCNT_MAX_INDEX 31
4032 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_S 0
4033 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
4034 #define GLHMC_VFPECQBASE(_i) (0x0052C200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4035 #define GLHMC_VFPECQBASE_MAX_INDEX 31
4036 #define GLHMC_VFPECQBASE_FPMPECQBASE_S 0
4037 #define GLHMC_VFPECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
4038 #define GLHMC_VFPECQCNT(_i) (0x0052C300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4039 #define GLHMC_VFPECQCNT_MAX_INDEX 31
4040 #define GLHMC_VFPECQCNT_FPMPECQCNT_S 0
4041 #define GLHMC_VFPECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
4042 #define GLHMC_VFPEHDRBASE(_i) (0x0052E200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4043 #define GLHMC_VFPEHDRBASE_MAX_INDEX 31
4044 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_S 0
4045 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
4046 #define GLHMC_VFPEHDRCNT(_i) (0x0052E300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4047 #define GLHMC_VFPEHDRCNT_MAX_INDEX 31
4048 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_S 0
4049 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
4050 #define GLHMC_VFPEHTCNT(_i) (0x0052C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4051 #define GLHMC_VFPEHTCNT_MAX_INDEX 31
4052 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_S 0
4053 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4054 #define GLHMC_VFPEHTCNT_FPMAT(_i) (0x0010C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4055 #define GLHMC_VFPEHTCNT_FPMAT_MAX_INDEX 31
4056 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S 0
4057 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4058 #define GLHMC_VFPEHTEBASE(_i) (0x0052C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4059 #define GLHMC_VFPEHTEBASE_MAX_INDEX 31
4060 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_S 0
4061 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4062 #define GLHMC_VFPEHTEBASE_FPMAT(_i) (0x0010C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4063 #define GLHMC_VFPEHTEBASE_FPMAT_MAX_INDEX 31
4064 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
4065 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4066 #define GLHMC_VFPEMDBASE(_i) (0x0052E400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4067 #define GLHMC_VFPEMDBASE_MAX_INDEX 31
4068 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_S 0
4069 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
4070 #define GLHMC_VFPEMDCNT(_i) (0x0052E500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4071 #define GLHMC_VFPEMDCNT_MAX_INDEX 31
4072 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_S 0
4073 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
4074 #define GLHMC_VFPEMRBASE(_i) (0x0052CC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4075 #define GLHMC_VFPEMRBASE_MAX_INDEX 31
4076 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0
4077 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
4078 #define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4079 #define GLHMC_VFPEMRCNT_MAX_INDEX 31
4080 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0
4081 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
4082 #define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4083 #define GLHMC_VFPEOOISCBASE_MAX_INDEX 31
4084 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
4085 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
4086 #define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4087 #define GLHMC_VFPEOOISCCNT_MAX_INDEX 31
4088 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0
4089 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
4090 #define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4091 #define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX 31
4092 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
4093 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4094 #define GLHMC_VFPEPBLBASE(_i) (0x0052D800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4095 #define GLHMC_VFPEPBLBASE_MAX_INDEX 31
4096 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_S 0
4097 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
4098 #define GLHMC_VFPEPBLCNT(_i) (0x0052D900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4099 #define GLHMC_VFPEPBLCNT_MAX_INDEX 31
4100 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_S 0
4101 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
4102 #define GLHMC_VFPEQ1BASE(_i) (0x0052D200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4103 #define GLHMC_VFPEQ1BASE_MAX_INDEX 31
4104 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_S 0
4105 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
4106 #define GLHMC_VFPEQ1CNT(_i) (0x0052D300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4107 #define GLHMC_VFPEQ1CNT_MAX_INDEX 31
4108 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_S 0
4109 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
4110 #define GLHMC_VFPEQ1FLBASE(_i) (0x0052D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4111 #define GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
4112 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_S 0
4113 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
4114 #define GLHMC_VFPEQPBASE(_i) (0x0052C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4115 #define GLHMC_VFPEQPBASE_MAX_INDEX 31
4116 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_S 0
4117 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
4118 #define GLHMC_VFPEQPCNT(_i) (0x0052C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4119 #define GLHMC_VFPEQPCNT_MAX_INDEX 31
4120 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_S 0
4121 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
4122 #define GLHMC_VFPERRFBASE(_i) (0x0052E800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4123 #define GLHMC_VFPERRFBASE_MAX_INDEX 31
4124 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0
4125 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
4126 #define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4127 #define GLHMC_VFPERRFCNT_MAX_INDEX 31
4128 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0
4129 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
4130 #define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4131 #define GLHMC_VFPERRFFLBASE_MAX_INDEX 31
4132 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
4133 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4134 #define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4135 #define GLHMC_VFPETIMERBASE_MAX_INDEX 31
4136 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0
4137 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
4138 #define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4139 #define GLHMC_VFPETIMERCNT_MAX_INDEX 31
4140 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0
4141 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
4142 #define GLHMC_VFPEXFBASE(_i) (0x0052CE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4143 #define GLHMC_VFPEXFBASE_MAX_INDEX 31
4144 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_S 0
4145 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
4146 #define GLHMC_VFPEXFCNT(_i) (0x0052CF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4147 #define GLHMC_VFPEXFCNT_MAX_INDEX 31
4148 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_S 0
4149 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
4150 #define GLHMC_VFPEXFFLBASE(_i) (0x0052D000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4151 #define GLHMC_VFPEXFFLBASE_MAX_INDEX 31
4152 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0
4153 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
4154 #define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4155 #define GLHMC_VFSDDATAHIGH_MAX_INDEX 31
4156 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0
4157 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4158 #define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4159 #define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31
4160 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4161 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4162 #define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4163 #define GLHMC_VFSDDATALOW_MAX_INDEX 31
4164 #define GLHMC_VFSDDATALOW_PMSDVALID_S 0
4165 #define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)
4166 #define GLHMC_VFSDDATALOW_PMSDTYPE_S 1
4167 #define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1)
4168 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S 2
4169 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4170 #define GLHMC_VFSDDATALOW_PMSDDATALOW_S 12
4171 #define GLHMC_VFSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4172 #define GLHMC_VFSDDATALOW_FPMAT(_i) (0x00108100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4173 #define GLHMC_VFSDDATALOW_FPMAT_MAX_INDEX 31
4174 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_S 0
4175 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4176 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_S 1
4177 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
4178 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_S 2
4179 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4180 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_S 12
4181 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4182 #define GLHMC_VFSDPART(_i) (0x00528800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4183 #define GLHMC_VFSDPART_MAX_INDEX 31
4184 #define GLHMC_VFSDPART_PMSDBASE_S 0
4185 #define GLHMC_VFSDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
4186 #define GLHMC_VFSDPART_PMSDSIZE_S 16
4187 #define GLHMC_VFSDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4188 #define GLHMC_VFSDPART_FPMAT(_i) (0x00108800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4189 #define GLHMC_VFSDPART_FPMAT_MAX_INDEX 31
4190 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_S 0
4191 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
4192 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_S 16
4193 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4194 #define GLMDOC_CACHESIZE 0x0051C06C /* Reset Source: CORER */
4195 #define GLMDOC_CACHESIZE_WORD_SIZE_S 0
4196 #define GLMDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4197 #define GLMDOC_CACHESIZE_SETS_S 8
4198 #define GLMDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4199 #define GLMDOC_CACHESIZE_WAYS_S 20
4200 #define GLMDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4201 #define GLPBLOC0_CACHESIZE 0x00518074 /* Reset Source: CORER */
4202 #define GLPBLOC0_CACHESIZE_WORD_SIZE_S 0
4203 #define GLPBLOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4204 #define GLPBLOC0_CACHESIZE_SETS_S 8
4205 #define GLPBLOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4206 #define GLPBLOC0_CACHESIZE_WAYS_S 20
4207 #define GLPBLOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4208 #define GLPBLOC1_CACHESIZE 0x0051A074 /* Reset Source: CORER */
4209 #define GLPBLOC1_CACHESIZE_WORD_SIZE_S 0
4210 #define GLPBLOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4211 #define GLPBLOC1_CACHESIZE_SETS_S 8
4212 #define GLPBLOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4213 #define GLPBLOC1_CACHESIZE_WAYS_S 20
4214 #define GLPBLOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4215 #define GLPDOC_CACHESIZE 0x00530048 /* Reset Source: CORER */
4216 #define GLPDOC_CACHESIZE_WORD_SIZE_S 0
4217 #define GLPDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4218 #define GLPDOC_CACHESIZE_SETS_S 8
4219 #define GLPDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4220 #define GLPDOC_CACHESIZE_WAYS_S 20
4221 #define GLPDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4222 #define GLPDOC_CACHESIZE_FPMAT 0x00110088 /* Reset Source: CORER */
4223 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_S 0
4224 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_M MAKEMASK(0xFF, 0)
4225 #define GLPDOC_CACHESIZE_FPMAT_SETS_S 8
4226 #define GLPDOC_CACHESIZE_FPMAT_SETS_M MAKEMASK(0xFFF, 8)
4227 #define GLPDOC_CACHESIZE_FPMAT_WAYS_S 20
4228 #define GLPDOC_CACHESIZE_FPMAT_WAYS_M MAKEMASK(0xF, 20)
4229 #define GLPEOC0_CACHESIZE 0x005140A8 /* Reset Source: CORER */
4230 #define GLPEOC0_CACHESIZE_WORD_SIZE_S 0
4231 #define GLPEOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4232 #define GLPEOC0_CACHESIZE_SETS_S 8
4233 #define GLPEOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4234 #define GLPEOC0_CACHESIZE_WAYS_S 20
4235 #define GLPEOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4236 #define GLPEOC1_CACHESIZE 0x005160A8 /* Reset Source: CORER */
4237 #define GLPEOC1_CACHESIZE_WORD_SIZE_S 0
4238 #define GLPEOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4239 #define GLPEOC1_CACHESIZE_SETS_S 8
4240 #define GLPEOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4241 #define GLPEOC1_CACHESIZE_WAYS_S 20
4242 #define GLPEOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4243 #define PFHMC_ERRORDATA 0x00520500 /* Reset Source: PFR */
4244 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_S 0
4245 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4246 #define PFHMC_ERRORDATA_FPMAT 0x00100500 /* Reset Source: PFR */
4247 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_S 0
4248 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4249 #define PFHMC_ERRORINFO 0x00520400 /* Reset Source: PFR */
4250 #define PFHMC_ERRORINFO_PMF_INDEX_S 0
4251 #define PFHMC_ERRORINFO_PMF_INDEX_M MAKEMASK(0x1F, 0)
4252 #define PFHMC_ERRORINFO_PMF_ISVF_S 7
4253 #define PFHMC_ERRORINFO_PMF_ISVF_M BIT(7)
4254 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_S 8
4255 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4256 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S 16
4257 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4258 #define PFHMC_ERRORINFO_ERROR_DETECTED_S 31
4259 #define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31)
4260 #define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */
4261 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0
4262 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0)
4263 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S 7
4264 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)
4265 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8
4266 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4267 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
4268 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4269 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31
4270 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)
4271 #define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */
4272 #define PFHMC_PDINV_PMSDIDX_S 0
4273 #define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
4274 #define PFHMC_PDINV_PMSDPARTSEL_S 15
4275 #define PFHMC_PDINV_PMSDPARTSEL_M BIT(15)
4276 #define PFHMC_PDINV_PMPDIDX_S 16
4277 #define PFHMC_PDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
4278 #define PFHMC_PDINV_FPMAT 0x00100300 /* Reset Source: PFR */
4279 #define PFHMC_PDINV_FPMAT_PMSDIDX_S 0
4280 #define PFHMC_PDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4281 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_S 15
4282 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_M BIT(15)
4283 #define PFHMC_PDINV_FPMAT_PMPDIDX_S 16
4284 #define PFHMC_PDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
4285 #define PFHMC_SDCMD 0x00520000 /* Reset Source: PFR */
4286 #define PFHMC_SDCMD_PMSDIDX_S 0
4287 #define PFHMC_SDCMD_PMSDIDX_M MAKEMASK(0xFFF, 0)
4288 #define PFHMC_SDCMD_PMSDPARTSEL_S 15
4289 #define PFHMC_SDCMD_PMSDPARTSEL_M BIT(15)
4290 #define PFHMC_SDCMD_PMSDWR_S 31
4291 #define PFHMC_SDCMD_PMSDWR_M BIT(31)
4292 #define PFHMC_SDCMD_FPMAT 0x00100000 /* Reset Source: PFR */
4293 #define PFHMC_SDCMD_FPMAT_PMSDIDX_S 0
4294 #define PFHMC_SDCMD_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4295 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_S 15
4296 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_M BIT(15)
4297 #define PFHMC_SDCMD_FPMAT_PMSDWR_S 31
4298 #define PFHMC_SDCMD_FPMAT_PMSDWR_M BIT(31)
4299 #define PFHMC_SDDATAHIGH 0x00520200 /* Reset Source: PFR */
4300 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_S 0
4301 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4302 #define PFHMC_SDDATAHIGH_FPMAT 0x00100200 /* Reset Source: PFR */
4303 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4304 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4305 #define PFHMC_SDDATALOW 0x00520100 /* Reset Source: PFR */
4306 #define PFHMC_SDDATALOW_PMSDVALID_S 0
4307 #define PFHMC_SDDATALOW_PMSDVALID_M BIT(0)
4308 #define PFHMC_SDDATALOW_PMSDTYPE_S 1
4309 #define PFHMC_SDDATALOW_PMSDTYPE_M BIT(1)
4310 #define PFHMC_SDDATALOW_PMSDBPCOUNT_S 2
4311 #define PFHMC_SDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4312 #define PFHMC_SDDATALOW_PMSDDATALOW_S 12
4313 #define PFHMC_SDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4314 #define PFHMC_SDDATALOW_FPMAT 0x00100100 /* Reset Source: PFR */
4315 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_S 0
4316 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4317 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_S 1
4318 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
4319 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_S 2
4320 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4321 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_S 12
4322 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4323 #define GL_DSI_REPC 0x00294208 /* Reset Source: CORER */
4324 #define GL_DSI_REPC_NO_DESC_CNT_S 0
4325 #define GL_DSI_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
4326 #define GL_DSI_REPC_ERROR_CNT_S 16
4327 #define GL_DSI_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
4328 #define GL_MDCK_TDAT_TCLAN 0x000FC0DC /* Reset Source: CORER */
4329 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_S 0
4330 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0)
4331 #define GL_MDCK_TDAT_TCLAN_UR_S 1
4332 #define GL_MDCK_TDAT_TCLAN_UR_M BIT(1)
4333 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_S 2
4334 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_M BIT(2)
4335 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_S 3
4336 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_M BIT(3)
4337 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_S 4
4338 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_M BIT(4)
4339 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_S 5
4340 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_M BIT(5)
4341 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_S 6
4342 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_M BIT(6)
4343 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_S 7
4344 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_M BIT(7)
4345 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_S 8
4346 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_M BIT(8)
4347 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9
4348 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)
4349 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10
4350 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)
4351 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11
4352 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
4353 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12
4354 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
4355 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
4356 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
4357 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14
4358 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
4359 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15
4360 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)
4361 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16
4362 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)
4363 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17
4364 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)
4365 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_S 18
4366 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_M BIT(18)
4367 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_S 19
4368 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19)
4369 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_S 20
4370 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20)
4371 #define GLCORE_CLKCTL_H 0x000B81E8 /* Reset Source: POR */
4372 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S 0
4373 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M MAKEMASK(0x3, 0)
4374 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_S 2
4375 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_M MAKEMASK(0x3, 2)
4376 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_S 4
4377 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_M MAKEMASK(0x3, 4)
4378 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_S 6
4379 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_M MAKEMASK(0x3, 6)
4380 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_S 8
4381 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_M MAKEMASK(0x7, 8)
4382 #define GLCORE_CLKCTL_L 0x000B8254 /* Reset Source: POR */
4383 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_S 0
4384 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_M MAKEMASK(0x3, 0)
4385 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_S 2
4386 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_M MAKEMASK(0x3, 2)
4387 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_S 4
4388 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_M MAKEMASK(0x3, 4)
4389 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_S 6
4390 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_M MAKEMASK(0x3, 6)
4391 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_S 8
4392 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_M MAKEMASK(0x7, 8)
4393 #define GLCORE_CLKCTL_M 0x000B8258 /* Reset Source: POR */
4394 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_S 0
4395 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_M MAKEMASK(0x3, 0)
4396 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_S 2
4397 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_M MAKEMASK(0x3, 2)
4398 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_S 4
4399 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_M MAKEMASK(0x3, 4)
4400 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_S 6
4401 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_M MAKEMASK(0x3, 6)
4402 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_S 8
4403 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_M MAKEMASK(0x7, 8)
4404 #define GLFOC_CACHESIZE 0x000AA074 /* Reset Source: CORER */
4405 #define GLFOC_CACHESIZE_WORD_SIZE_S 0
4406 #define GLFOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4407 #define GLFOC_CACHESIZE_SETS_S 8
4408 #define GLFOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4409 #define GLFOC_CACHESIZE_WAYS_S 20
4410 #define GLFOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4411 #define GLMAC_CLKSTAT 0x000B8210 /* Reset Source: POR */
4412 #define GLMAC_CLKSTAT_P0_CLK_SPEED_S 0
4413 #define GLMAC_CLKSTAT_P0_CLK_SPEED_M MAKEMASK(0xF, 0)
4414 #define GLMAC_CLKSTAT_P1_CLK_SPEED_S 4
4415 #define GLMAC_CLKSTAT_P1_CLK_SPEED_M MAKEMASK(0xF, 4)
4416 #define GLMAC_CLKSTAT_P2_CLK_SPEED_S 8
4417 #define GLMAC_CLKSTAT_P2_CLK_SPEED_M MAKEMASK(0xF, 8)
4418 #define GLMAC_CLKSTAT_P3_CLK_SPEED_S 12
4419 #define GLMAC_CLKSTAT_P3_CLK_SPEED_M MAKEMASK(0xF, 12)
4420 #define GLMAC_CLKSTAT_P4_CLK_SPEED_S 16
4421 #define GLMAC_CLKSTAT_P4_CLK_SPEED_M MAKEMASK(0xF, 16)
4422 #define GLMAC_CLKSTAT_P5_CLK_SPEED_S 20
4423 #define GLMAC_CLKSTAT_P5_CLK_SPEED_M MAKEMASK(0xF, 20)
4424 #define GLMAC_CLKSTAT_P6_CLK_SPEED_S 24
4425 #define GLMAC_CLKSTAT_P6_CLK_SPEED_M MAKEMASK(0xF, 24)
4426 #define GLMAC_CLKSTAT_P7_CLK_SPEED_S 28
4427 #define GLMAC_CLKSTAT_P7_CLK_SPEED_M MAKEMASK(0xF, 28)
4428 #define GLTPB_100G_MAC_FC_THRESH 0x00099510 /* Reset Source: CORER */
4429 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0
4430 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4431 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16
4432 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4433 #define GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */
4434 #define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0
4435 #define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4436 #define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16
4437 #define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4438 #define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */
4439 #define GLTPB_PACING_10G_N_S 0
4440 #define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0)
4441 #define GLTPB_PACING_10G_K_S 8
4442 #define GLTPB_PACING_10G_K_M MAKEMASK(0xFF, 8)
4443 #define GLTPB_PACING_10G_S_S 16
4444 #define GLTPB_PACING_10G_S_M MAKEMASK(0x1FF, 16)
4445 #define GLTPB_PACING_25G 0x000994E0 /* Reset Source: CORER */
4446 #define GLTPB_PACING_25G_N_S 0
4447 #define GLTPB_PACING_25G_N_M MAKEMASK(0xFF, 0)
4448 #define GLTPB_PACING_25G_K_S 8
4449 #define GLTPB_PACING_25G_K_M MAKEMASK(0xFF, 8)
4450 #define GLTPB_PACING_25G_S_S 16
4451 #define GLTPB_PACING_25G_S_M MAKEMASK(0x1FF, 16)
4452 #define GLTPB_PORT_PACING_SPEED 0x000994E8 /* Reset Source: CORER */
4453 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_S 0
4454 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M BIT(0)
4455 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_S 1
4456 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_M BIT(1)
4457 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_S 2
4458 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_M BIT(2)
4459 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_S 3
4460 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_M BIT(3)
4461 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_S 4
4462 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_M BIT(4)
4463 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_S 5
4464 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_M BIT(5)
4465 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_S 6
4466 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M BIT(6)
4467 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_S 7
4468 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M BIT(7)
4469 #define TPB_CFG_SCHEDULED_BC_THRESHOLD 0x00099494 /* Reset Source: CORER */
4470 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0
4471 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0)
4472 #define GL_UFUSE_SOC 0x000A400C /* Reset Source: POR */
4473 #define GL_UFUSE_SOC_PORT_MODE_S 0
4474 #define GL_UFUSE_SOC_PORT_MODE_M MAKEMASK(0x3, 0)
4475 #define GL_UFUSE_SOC_BANDWIDTH_S 2
4476 #define GL_UFUSE_SOC_BANDWIDTH_M MAKEMASK(0x3, 2)
4477 #define GL_UFUSE_SOC_PE_DISABLE_S 4
4478 #define GL_UFUSE_SOC_PE_DISABLE_M BIT(4)
4479 #define GL_UFUSE_SOC_SWITCH_MODE_S 5
4480 #define GL_UFUSE_SOC_SWITCH_MODE_M BIT(5)
4481 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_S 6
4482 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_M BIT(6)
4483 #define GL_UFUSE_SOC_SERIAL_50G_S 7
4484 #define GL_UFUSE_SOC_SERIAL_50G_M BIT(7)
4485 #define GL_UFUSE_SOC_NIC_ID_S 8
4486 #define GL_UFUSE_SOC_NIC_ID_M BIT(8)
4487 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_S 9
4488 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_M BIT(9)
4489 #define GL_UFUSE_SOC_SOC_TYPE_S 10
4490 #define GL_UFUSE_SOC_SOC_TYPE_M BIT(10)
4491 #define GL_UFUSE_SOC_BTS_MODE_S 11
4492 #define GL_UFUSE_SOC_BTS_MODE_M BIT(11)
4493 #define GL_UFUSE_SOC_SPARE_FUSES_S 12
4494 #define GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12)
4495 #define EMPINT_GPIO_ENA 0x000880C0 /* Reset Source: POR */
4496 #define EMPINT_GPIO_ENA_GPIO0_ENA_S 0
4497 #define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4498 #define EMPINT_GPIO_ENA_GPIO1_ENA_S 1
4499 #define EMPINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
4500 #define EMPINT_GPIO_ENA_GPIO2_ENA_S 2
4501 #define EMPINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
4502 #define EMPINT_GPIO_ENA_GPIO3_ENA_S 3
4503 #define EMPINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
4504 #define EMPINT_GPIO_ENA_GPIO4_ENA_S 4
4505 #define EMPINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
4506 #define EMPINT_GPIO_ENA_GPIO5_ENA_S 5
4507 #define EMPINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
4508 #define EMPINT_GPIO_ENA_GPIO6_ENA_S 6
4509 #define EMPINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
4510 #define GLGEN_MAC_LINK_TOPO 0x000B81DC /* Reset Source: GLOBR */
4511 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S 0
4512 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M MAKEMASK(0x3, 0)
4513 #define GLINT_CEQCTL(_INT) (0x0015C000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4514 #define GLINT_CEQCTL_MAX_INDEX 2047
4515 #define GLINT_CEQCTL_MSIX_INDX_S 0
4516 #define GLINT_CEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4517 #define GLINT_CEQCTL_ITR_INDX_S 11
4518 #define GLINT_CEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4519 #define GLINT_CEQCTL_CAUSE_ENA_S 30
4520 #define GLINT_CEQCTL_CAUSE_ENA_M BIT(30)
4521 #define GLINT_CEQCTL_INTEVENT_S 31
4522 #define GLINT_CEQCTL_INTEVENT_M BIT(31)
4523 #define GLINT_CTL 0x0016CC54 /* Reset Source: CORER */
4524 #define GLINT_CTL_DIS_AUTOMASK_S 0
4525 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
4526 #define GLINT_CTL_RSVD_S 1
4527 #define GLINT_CTL_RSVD_M MAKEMASK(0x7FFF, 1)
4528 #define GLINT_CTL_ITR_GRAN_200_S 16
4529 #define GLINT_CTL_ITR_GRAN_200_M MAKEMASK(0xF, 16)
4530 #define GLINT_CTL_ITR_GRAN_100_S 20
4531 #define GLINT_CTL_ITR_GRAN_100_M MAKEMASK(0xF, 20)
4532 #define GLINT_CTL_ITR_GRAN_50_S 24
4533 #define GLINT_CTL_ITR_GRAN_50_M MAKEMASK(0xF, 24)
4534 #define GLINT_CTL_ITR_GRAN_25_S 28
4535 #define GLINT_CTL_ITR_GRAN_25_M MAKEMASK(0xF, 28)
4536 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4537 #define GLINT_DYN_CTL_MAX_INDEX 2047
4538 #define GLINT_DYN_CTL_INTENA_S 0
4539 #define GLINT_DYN_CTL_INTENA_M BIT(0)
4540 #define GLINT_DYN_CTL_CLEARPBA_S 1
4541 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
4542 #define GLINT_DYN_CTL_SWINT_TRIG_S 2
4543 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
4544 #define GLINT_DYN_CTL_ITR_INDX_S 3
4545 #define GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
4546 #define GLINT_DYN_CTL_INTERVAL_S 5
4547 #define GLINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
4548 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24
4549 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
4550 #define GLINT_DYN_CTL_SW_ITR_INDX_S 25
4551 #define GLINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
4552 #define GLINT_DYN_CTL_WB_ON_ITR_S 30
4553 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
4554 #define GLINT_DYN_CTL_INTENA_MSK_S 31
4555 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
4556 #define GLINT_FW_TOOL_CTL 0x0016C840 /* Reset Source: CORER */
4557 #define GLINT_FW_TOOL_CTL_MSIX_INDX_S 0
4558 #define GLINT_FW_TOOL_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4559 #define GLINT_FW_TOOL_CTL_ITR_INDX_S 11
4560 #define GLINT_FW_TOOL_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4561 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_S 30
4562 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_M BIT(30)
4563 #define GLINT_FW_TOOL_CTL_INTEVENT_S 31
4564 #define GLINT_FW_TOOL_CTL_INTEVENT_M BIT(31)
4565 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: CORER */
4566 #define GLINT_ITR_MAX_INDEX 2
4567 #define GLINT_ITR_INTERVAL_S 0
4568 #define GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, 0)
4569 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4570 #define GLINT_RATE_MAX_INDEX 2047
4571 #define GLINT_RATE_INTERVAL_S 0
4572 #define GLINT_RATE_INTERVAL_M MAKEMASK(0x3F, 0)
4573 #define GLINT_RATE_INTRL_ENA_S 6
4574 #define GLINT_RATE_INTRL_ENA_M BIT(6)
4575 #define GLINT_TSYN_PFMSTR(_i) (0x0016CCC0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
4576 #define GLINT_TSYN_PFMSTR_MAX_INDEX 1
4577 #define GLINT_TSYN_PFMSTR_PF_MASTER_S 0
4578 #define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0)
4579 #define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */
4580 #define GLINT_TSYN_PHY_PHY_INDX_S 0
4581 #define GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0)
4582 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4583 #define GLINT_VECT2FUNC_MAX_INDEX 2047
4584 #define GLINT_VECT2FUNC_VF_NUM_S 0
4585 #define GLINT_VECT2FUNC_VF_NUM_M MAKEMASK(0xFF, 0)
4586 #define GLINT_VECT2FUNC_PF_NUM_S 12
4587 #define GLINT_VECT2FUNC_PF_NUM_M MAKEMASK(0x7, 12)
4588 #define GLINT_VECT2FUNC_IS_PF_S 16
4589 #define GLINT_VECT2FUNC_IS_PF_M BIT(16)
4590 #define PF0INT_FW_HLP_CTL 0x0016C844 /* Reset Source: CORER */
4591 #define PF0INT_FW_HLP_CTL_MSIX_INDX_S 0
4592 #define PF0INT_FW_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4593 #define PF0INT_FW_HLP_CTL_ITR_INDX_S 11
4594 #define PF0INT_FW_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4595 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_S 30
4596 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_M BIT(30)
4597 #define PF0INT_FW_HLP_CTL_INTEVENT_S 31
4598 #define PF0INT_FW_HLP_CTL_INTEVENT_M BIT(31)
4599 #define PF0INT_FW_PSM_CTL 0x0016C848 /* Reset Source: CORER */
4600 #define PF0INT_FW_PSM_CTL_MSIX_INDX_S 0
4601 #define PF0INT_FW_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4602 #define PF0INT_FW_PSM_CTL_ITR_INDX_S 11
4603 #define PF0INT_FW_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4604 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_S 30
4605 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_M BIT(30)
4606 #define PF0INT_FW_PSM_CTL_INTEVENT_S 31
4607 #define PF0INT_FW_PSM_CTL_INTEVENT_M BIT(31)
4608 #define PF0INT_MBX_CPM_CTL 0x0016B2C0 /* Reset Source: CORER */
4609 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_S 0
4610 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4611 #define PF0INT_MBX_CPM_CTL_ITR_INDX_S 11
4612 #define PF0INT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4613 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_S 30
4614 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
4615 #define PF0INT_MBX_CPM_CTL_INTEVENT_S 31
4616 #define PF0INT_MBX_CPM_CTL_INTEVENT_M BIT(31)
4617 #define PF0INT_MBX_HLP_CTL 0x0016B2C4 /* Reset Source: CORER */
4618 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_S 0
4619 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4620 #define PF0INT_MBX_HLP_CTL_ITR_INDX_S 11
4621 #define PF0INT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4622 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_S 30
4623 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
4624 #define PF0INT_MBX_HLP_CTL_INTEVENT_S 31
4625 #define PF0INT_MBX_HLP_CTL_INTEVENT_M BIT(31)
4626 #define PF0INT_MBX_PSM_CTL 0x0016B2C8 /* Reset Source: CORER */
4627 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_S 0
4628 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4629 #define PF0INT_MBX_PSM_CTL_ITR_INDX_S 11
4630 #define PF0INT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4631 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_S 30
4632 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
4633 #define PF0INT_MBX_PSM_CTL_INTEVENT_S 31
4634 #define PF0INT_MBX_PSM_CTL_INTEVENT_M BIT(31)
4635 #define PF0INT_OICR_CPM 0x0016CC40 /* Reset Source: CORER */
4636 #define PF0INT_OICR_CPM_INTEVENT_S 0
4637 #define PF0INT_OICR_CPM_INTEVENT_M BIT(0)
4638 #define PF0INT_OICR_CPM_QUEUE_S 1
4639 #define PF0INT_OICR_CPM_QUEUE_M BIT(1)
4640 #define PF0INT_OICR_CPM_RSV1_S 2
4641 #define PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2)
4642 #define PF0INT_OICR_CPM_HH_COMP_S 10
4643 #define PF0INT_OICR_CPM_HH_COMP_M BIT(10)
4644 #define PF0INT_OICR_CPM_TSYN_TX_S 11
4645 #define PF0INT_OICR_CPM_TSYN_TX_M BIT(11)
4646 #define PF0INT_OICR_CPM_TSYN_EVNT_S 12
4647 #define PF0INT_OICR_CPM_TSYN_EVNT_M BIT(12)
4648 #define PF0INT_OICR_CPM_TSYN_TGT_S 13
4649 #define PF0INT_OICR_CPM_TSYN_TGT_M BIT(13)
4650 #define PF0INT_OICR_CPM_HLP_RDY_S 14
4651 #define PF0INT_OICR_CPM_HLP_RDY_M BIT(14)
4652 #define PF0INT_OICR_CPM_CPM_RDY_S 15
4653 #define PF0INT_OICR_CPM_CPM_RDY_M BIT(15)
4654 #define PF0INT_OICR_CPM_ECC_ERR_S 16
4655 #define PF0INT_OICR_CPM_ECC_ERR_M BIT(16)
4656 #define PF0INT_OICR_CPM_RSV2_S 17
4657 #define PF0INT_OICR_CPM_RSV2_M MAKEMASK(0x3, 17)
4658 #define PF0INT_OICR_CPM_MAL_DETECT_S 19
4659 #define PF0INT_OICR_CPM_MAL_DETECT_M BIT(19)
4660 #define PF0INT_OICR_CPM_GRST_S 20
4661 #define PF0INT_OICR_CPM_GRST_M BIT(20)
4662 #define PF0INT_OICR_CPM_PCI_EXCEPTION_S 21
4663 #define PF0INT_OICR_CPM_PCI_EXCEPTION_M BIT(21)
4664 #define PF0INT_OICR_CPM_GPIO_S 22
4665 #define PF0INT_OICR_CPM_GPIO_M BIT(22)
4666 #define PF0INT_OICR_CPM_RSV3_S 23
4667 #define PF0INT_OICR_CPM_RSV3_M BIT(23)
4668 #define PF0INT_OICR_CPM_STORM_DETECT_S 24
4669 #define PF0INT_OICR_CPM_STORM_DETECT_M BIT(24)
4670 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_S 25
4671 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_M BIT(25)
4672 #define PF0INT_OICR_CPM_HMC_ERR_S 26
4673 #define PF0INT_OICR_CPM_HMC_ERR_M BIT(26)
4674 #define PF0INT_OICR_CPM_PE_PUSH_S 27
4675 #define PF0INT_OICR_CPM_PE_PUSH_M BIT(27)
4676 #define PF0INT_OICR_CPM_PE_CRITERR_S 28
4677 #define PF0INT_OICR_CPM_PE_CRITERR_M BIT(28)
4678 #define PF0INT_OICR_CPM_VFLR_S 29
4679 #define PF0INT_OICR_CPM_VFLR_M BIT(29)
4680 #define PF0INT_OICR_CPM_XLR_HW_DONE_S 30
4681 #define PF0INT_OICR_CPM_XLR_HW_DONE_M BIT(30)
4682 #define PF0INT_OICR_CPM_SWINT_S 31
4683 #define PF0INT_OICR_CPM_SWINT_M BIT(31)
4684 #define PF0INT_OICR_CTL_CPM 0x0016CC48 /* Reset Source: CORER */
4685 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_S 0
4686 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4687 #define PF0INT_OICR_CTL_CPM_ITR_INDX_S 11
4688 #define PF0INT_OICR_CTL_CPM_ITR_INDX_M MAKEMASK(0x3, 11)
4689 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_S 30
4690 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_M BIT(30)
4691 #define PF0INT_OICR_CTL_CPM_INTEVENT_S 31
4692 #define PF0INT_OICR_CTL_CPM_INTEVENT_M BIT(31)
4693 #define PF0INT_OICR_CTL_HLP 0x0016CC5C /* Reset Source: CORER */
4694 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_S 0
4695 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4696 #define PF0INT_OICR_CTL_HLP_ITR_INDX_S 11
4697 #define PF0INT_OICR_CTL_HLP_ITR_INDX_M MAKEMASK(0x3, 11)
4698 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_S 30
4699 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_M BIT(30)
4700 #define PF0INT_OICR_CTL_HLP_INTEVENT_S 31
4701 #define PF0INT_OICR_CTL_HLP_INTEVENT_M BIT(31)
4702 #define PF0INT_OICR_CTL_PSM 0x0016CC64 /* Reset Source: CORER */
4703 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_S 0
4704 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4705 #define PF0INT_OICR_CTL_PSM_ITR_INDX_S 11
4706 #define PF0INT_OICR_CTL_PSM_ITR_INDX_M MAKEMASK(0x3, 11)
4707 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_S 30
4708 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_M BIT(30)
4709 #define PF0INT_OICR_CTL_PSM_INTEVENT_S 31
4710 #define PF0INT_OICR_CTL_PSM_INTEVENT_M BIT(31)
4711 #define PF0INT_OICR_ENA_CPM 0x0016CC60 /* Reset Source: CORER */
4712 #define PF0INT_OICR_ENA_CPM_RSV0_S 0
4713 #define PF0INT_OICR_ENA_CPM_RSV0_M BIT(0)
4714 #define PF0INT_OICR_ENA_CPM_INT_ENA_S 1
4715 #define PF0INT_OICR_ENA_CPM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4716 #define PF0INT_OICR_ENA_HLP 0x0016CC4C /* Reset Source: CORER */
4717 #define PF0INT_OICR_ENA_HLP_RSV0_S 0
4718 #define PF0INT_OICR_ENA_HLP_RSV0_M BIT(0)
4719 #define PF0INT_OICR_ENA_HLP_INT_ENA_S 1
4720 #define PF0INT_OICR_ENA_HLP_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4721 #define PF0INT_OICR_ENA_PSM 0x0016CC58 /* Reset Source: CORER */
4722 #define PF0INT_OICR_ENA_PSM_RSV0_S 0
4723 #define PF0INT_OICR_ENA_PSM_RSV0_M BIT(0)
4724 #define PF0INT_OICR_ENA_PSM_INT_ENA_S 1
4725 #define PF0INT_OICR_ENA_PSM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4726 #define PF0INT_OICR_HLP 0x0016CC68 /* Reset Source: CORER */
4727 #define PF0INT_OICR_HLP_INTEVENT_S 0
4728 #define PF0INT_OICR_HLP_INTEVENT_M BIT(0)
4729 #define PF0INT_OICR_HLP_QUEUE_S 1
4730 #define PF0INT_OICR_HLP_QUEUE_M BIT(1)
4731 #define PF0INT_OICR_HLP_RSV1_S 2
4732 #define PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2)
4733 #define PF0INT_OICR_HLP_HH_COMP_S 10
4734 #define PF0INT_OICR_HLP_HH_COMP_M BIT(10)
4735 #define PF0INT_OICR_HLP_TSYN_TX_S 11
4736 #define PF0INT_OICR_HLP_TSYN_TX_M BIT(11)
4737 #define PF0INT_OICR_HLP_TSYN_EVNT_S 12
4738 #define PF0INT_OICR_HLP_TSYN_EVNT_M BIT(12)
4739 #define PF0INT_OICR_HLP_TSYN_TGT_S 13
4740 #define PF0INT_OICR_HLP_TSYN_TGT_M BIT(13)
4741 #define PF0INT_OICR_HLP_HLP_RDY_S 14
4742 #define PF0INT_OICR_HLP_HLP_RDY_M BIT(14)
4743 #define PF0INT_OICR_HLP_CPM_RDY_S 15
4744 #define PF0INT_OICR_HLP_CPM_RDY_M BIT(15)
4745 #define PF0INT_OICR_HLP_ECC_ERR_S 16
4746 #define PF0INT_OICR_HLP_ECC_ERR_M BIT(16)
4747 #define PF0INT_OICR_HLP_RSV2_S 17
4748 #define PF0INT_OICR_HLP_RSV2_M MAKEMASK(0x3, 17)
4749 #define PF0INT_OICR_HLP_MAL_DETECT_S 19
4750 #define PF0INT_OICR_HLP_MAL_DETECT_M BIT(19)
4751 #define PF0INT_OICR_HLP_GRST_S 20
4752 #define PF0INT_OICR_HLP_GRST_M BIT(20)
4753 #define PF0INT_OICR_HLP_PCI_EXCEPTION_S 21
4754 #define PF0INT_OICR_HLP_PCI_EXCEPTION_M BIT(21)
4755 #define PF0INT_OICR_HLP_GPIO_S 22
4756 #define PF0INT_OICR_HLP_GPIO_M BIT(22)
4757 #define PF0INT_OICR_HLP_RSV3_S 23
4758 #define PF0INT_OICR_HLP_RSV3_M BIT(23)
4759 #define PF0INT_OICR_HLP_STORM_DETECT_S 24
4760 #define PF0INT_OICR_HLP_STORM_DETECT_M BIT(24)
4761 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_S 25
4762 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_M BIT(25)
4763 #define PF0INT_OICR_HLP_HMC_ERR_S 26
4764 #define PF0INT_OICR_HLP_HMC_ERR_M BIT(26)
4765 #define PF0INT_OICR_HLP_PE_PUSH_S 27
4766 #define PF0INT_OICR_HLP_PE_PUSH_M BIT(27)
4767 #define PF0INT_OICR_HLP_PE_CRITERR_S 28
4768 #define PF0INT_OICR_HLP_PE_CRITERR_M BIT(28)
4769 #define PF0INT_OICR_HLP_VFLR_S 29
4770 #define PF0INT_OICR_HLP_VFLR_M BIT(29)
4771 #define PF0INT_OICR_HLP_XLR_HW_DONE_S 30
4772 #define PF0INT_OICR_HLP_XLR_HW_DONE_M BIT(30)
4773 #define PF0INT_OICR_HLP_SWINT_S 31
4774 #define PF0INT_OICR_HLP_SWINT_M BIT(31)
4775 #define PF0INT_OICR_PSM 0x0016CC44 /* Reset Source: CORER */
4776 #define PF0INT_OICR_PSM_INTEVENT_S 0
4777 #define PF0INT_OICR_PSM_INTEVENT_M BIT(0)
4778 #define PF0INT_OICR_PSM_QUEUE_S 1
4779 #define PF0INT_OICR_PSM_QUEUE_M BIT(1)
4780 #define PF0INT_OICR_PSM_RSV1_S 2
4781 #define PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2)
4782 #define PF0INT_OICR_PSM_HH_COMP_S 10
4783 #define PF0INT_OICR_PSM_HH_COMP_M BIT(10)
4784 #define PF0INT_OICR_PSM_TSYN_TX_S 11
4785 #define PF0INT_OICR_PSM_TSYN_TX_M BIT(11)
4786 #define PF0INT_OICR_PSM_TSYN_EVNT_S 12
4787 #define PF0INT_OICR_PSM_TSYN_EVNT_M BIT(12)
4788 #define PF0INT_OICR_PSM_TSYN_TGT_S 13
4789 #define PF0INT_OICR_PSM_TSYN_TGT_M BIT(13)
4790 #define PF0INT_OICR_PSM_HLP_RDY_S 14
4791 #define PF0INT_OICR_PSM_HLP_RDY_M BIT(14)
4792 #define PF0INT_OICR_PSM_CPM_RDY_S 15
4793 #define PF0INT_OICR_PSM_CPM_RDY_M BIT(15)
4794 #define PF0INT_OICR_PSM_ECC_ERR_S 16
4795 #define PF0INT_OICR_PSM_ECC_ERR_M BIT(16)
4796 #define PF0INT_OICR_PSM_RSV2_S 17
4797 #define PF0INT_OICR_PSM_RSV2_M MAKEMASK(0x3, 17)
4798 #define PF0INT_OICR_PSM_MAL_DETECT_S 19
4799 #define PF0INT_OICR_PSM_MAL_DETECT_M BIT(19)
4800 #define PF0INT_OICR_PSM_GRST_S 20
4801 #define PF0INT_OICR_PSM_GRST_M BIT(20)
4802 #define PF0INT_OICR_PSM_PCI_EXCEPTION_S 21
4803 #define PF0INT_OICR_PSM_PCI_EXCEPTION_M BIT(21)
4804 #define PF0INT_OICR_PSM_GPIO_S 22
4805 #define PF0INT_OICR_PSM_GPIO_M BIT(22)
4806 #define PF0INT_OICR_PSM_RSV3_S 23
4807 #define PF0INT_OICR_PSM_RSV3_M BIT(23)
4808 #define PF0INT_OICR_PSM_STORM_DETECT_S 24
4809 #define PF0INT_OICR_PSM_STORM_DETECT_M BIT(24)
4810 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_S 25
4811 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_M BIT(25)
4812 #define PF0INT_OICR_PSM_HMC_ERR_S 26
4813 #define PF0INT_OICR_PSM_HMC_ERR_M BIT(26)
4814 #define PF0INT_OICR_PSM_PE_PUSH_S 27
4815 #define PF0INT_OICR_PSM_PE_PUSH_M BIT(27)
4816 #define PF0INT_OICR_PSM_PE_CRITERR_S 28
4817 #define PF0INT_OICR_PSM_PE_CRITERR_M BIT(28)
4818 #define PF0INT_OICR_PSM_VFLR_S 29
4819 #define PF0INT_OICR_PSM_VFLR_M BIT(29)
4820 #define PF0INT_OICR_PSM_XLR_HW_DONE_S 30
4821 #define PF0INT_OICR_PSM_XLR_HW_DONE_M BIT(30)
4822 #define PF0INT_OICR_PSM_SWINT_S 31
4823 #define PF0INT_OICR_PSM_SWINT_M BIT(31)
4824 #define PF0INT_SB_CPM_CTL 0x0016B2CC /* Reset Source: CORER */
4825 #define PF0INT_SB_CPM_CTL_MSIX_INDX_S 0
4826 #define PF0INT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4827 #define PF0INT_SB_CPM_CTL_ITR_INDX_S 11
4828 #define PF0INT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4829 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_S 30
4830 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
4831 #define PF0INT_SB_CPM_CTL_INTEVENT_S 31
4832 #define PF0INT_SB_CPM_CTL_INTEVENT_M BIT(31)
4833 #define PF0INT_SB_HLP_CTL 0x0016B640 /* Reset Source: CORER */
4834 #define PF0INT_SB_HLP_CTL_MSIX_INDX_S 0
4835 #define PF0INT_SB_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4836 #define PF0INT_SB_HLP_CTL_ITR_INDX_S 11
4837 #define PF0INT_SB_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4838 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_S 30
4839 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_M BIT(30)
4840 #define PF0INT_SB_HLP_CTL_INTEVENT_S 31
4841 #define PF0INT_SB_HLP_CTL_INTEVENT_M BIT(31)
4842 #define PFINT_AEQCTL 0x0016CB00 /* Reset Source: CORER */
4843 #define PFINT_AEQCTL_MSIX_INDX_S 0
4844 #define PFINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4845 #define PFINT_AEQCTL_ITR_INDX_S 11
4846 #define PFINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4847 #define PFINT_AEQCTL_CAUSE_ENA_S 30
4848 #define PFINT_AEQCTL_CAUSE_ENA_M BIT(30)
4849 #define PFINT_AEQCTL_INTEVENT_S 31
4850 #define PFINT_AEQCTL_INTEVENT_M BIT(31)
4851 #define PFINT_ALLOC 0x001D2600 /* Reset Source: CORER */
4852 #define PFINT_ALLOC_FIRST_S 0
4853 #define PFINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
4854 #define PFINT_ALLOC_LAST_S 12
4855 #define PFINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
4856 #define PFINT_ALLOC_VALID_S 31
4857 #define PFINT_ALLOC_VALID_M BIT(31)
4858 #define PFINT_ALLOC_PCI 0x0009D800 /* Reset Source: PCIR */
4859 #define PFINT_ALLOC_PCI_FIRST_S 0
4860 #define PFINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
4861 #define PFINT_ALLOC_PCI_LAST_S 12
4862 #define PFINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
4863 #define PFINT_ALLOC_PCI_VALID_S 31
4864 #define PFINT_ALLOC_PCI_VALID_M BIT(31)
4865 #define PFINT_FW_CTL 0x0016C800 /* Reset Source: CORER */
4866 #define PFINT_FW_CTL_MSIX_INDX_S 0
4867 #define PFINT_FW_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4868 #define PFINT_FW_CTL_ITR_INDX_S 11
4869 #define PFINT_FW_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4870 #define PFINT_FW_CTL_CAUSE_ENA_S 30
4871 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
4872 #define PFINT_FW_CTL_INTEVENT_S 31
4873 #define PFINT_FW_CTL_INTEVENT_M BIT(31)
4874 #define PFINT_GPIO_ENA 0x00088080 /* Reset Source: CORER */
4875 #define PFINT_GPIO_ENA_GPIO0_ENA_S 0
4876 #define PFINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4877 #define PFINT_GPIO_ENA_GPIO1_ENA_S 1
4878 #define PFINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
4879 #define PFINT_GPIO_ENA_GPIO2_ENA_S 2
4880 #define PFINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
4881 #define PFINT_GPIO_ENA_GPIO3_ENA_S 3
4882 #define PFINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
4883 #define PFINT_GPIO_ENA_GPIO4_ENA_S 4
4884 #define PFINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
4885 #define PFINT_GPIO_ENA_GPIO5_ENA_S 5
4886 #define PFINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
4887 #define PFINT_GPIO_ENA_GPIO6_ENA_S 6
4888 #define PFINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
4889 #define PFINT_MBX_CTL 0x0016B280 /* Reset Source: CORER */
4890 #define PFINT_MBX_CTL_MSIX_INDX_S 0
4891 #define PFINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4892 #define PFINT_MBX_CTL_ITR_INDX_S 11
4893 #define PFINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4894 #define PFINT_MBX_CTL_CAUSE_ENA_S 30
4895 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
4896 #define PFINT_MBX_CTL_INTEVENT_S 31
4897 #define PFINT_MBX_CTL_INTEVENT_M BIT(31)
4898 #define PFINT_OICR 0x0016CA00 /* Reset Source: CORER */
4899 #define PFINT_OICR_INTEVENT_S 0
4900 #define PFINT_OICR_INTEVENT_M BIT(0)
4901 #define PFINT_OICR_QUEUE_S 1
4902 #define PFINT_OICR_QUEUE_M BIT(1)
4903 #define PFINT_OICR_RSV1_S 2
4904 #define PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2)
4905 #define PFINT_OICR_HH_COMP_S 10
4906 #define PFINT_OICR_HH_COMP_M BIT(10)
4907 #define PFINT_OICR_TSYN_TX_S 11
4908 #define PFINT_OICR_TSYN_TX_M BIT(11)
4909 #define PFINT_OICR_TSYN_EVNT_S 12
4910 #define PFINT_OICR_TSYN_EVNT_M BIT(12)
4911 #define PFINT_OICR_TSYN_TGT_S 13
4912 #define PFINT_OICR_TSYN_TGT_M BIT(13)
4913 #define PFINT_OICR_HLP_RDY_S 14
4914 #define PFINT_OICR_HLP_RDY_M BIT(14)
4915 #define PFINT_OICR_CPM_RDY_S 15
4916 #define PFINT_OICR_CPM_RDY_M BIT(15)
4917 #define PFINT_OICR_ECC_ERR_S 16
4918 #define PFINT_OICR_ECC_ERR_M BIT(16)
4919 #define PFINT_OICR_RSV2_S 17
4920 #define PFINT_OICR_RSV2_M MAKEMASK(0x3, 17)
4921 #define PFINT_OICR_MAL_DETECT_S 19
4922 #define PFINT_OICR_MAL_DETECT_M BIT(19)
4923 #define PFINT_OICR_GRST_S 20
4924 #define PFINT_OICR_GRST_M BIT(20)
4925 #define PFINT_OICR_PCI_EXCEPTION_S 21
4926 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
4927 #define PFINT_OICR_GPIO_S 22
4928 #define PFINT_OICR_GPIO_M BIT(22)
4929 #define PFINT_OICR_RSV3_S 23
4930 #define PFINT_OICR_RSV3_M BIT(23)
4931 #define PFINT_OICR_STORM_DETECT_S 24
4932 #define PFINT_OICR_STORM_DETECT_M BIT(24)
4933 #define PFINT_OICR_LINK_STAT_CHANGE_S 25
4934 #define PFINT_OICR_LINK_STAT_CHANGE_M BIT(25)
4935 #define PFINT_OICR_HMC_ERR_S 26
4936 #define PFINT_OICR_HMC_ERR_M BIT(26)
4937 #define PFINT_OICR_PE_PUSH_S 27
4938 #define PFINT_OICR_PE_PUSH_M BIT(27)
4939 #define PFINT_OICR_PE_CRITERR_S 28
4940 #define PFINT_OICR_PE_CRITERR_M BIT(28)
4941 #define PFINT_OICR_VFLR_S 29
4942 #define PFINT_OICR_VFLR_M BIT(29)
4943 #define PFINT_OICR_XLR_HW_DONE_S 30
4944 #define PFINT_OICR_XLR_HW_DONE_M BIT(30)
4945 #define PFINT_OICR_SWINT_S 31
4946 #define PFINT_OICR_SWINT_M BIT(31)
4947 #define PFINT_OICR_CTL 0x0016CA80 /* Reset Source: CORER */
4948 #define PFINT_OICR_CTL_MSIX_INDX_S 0
4949 #define PFINT_OICR_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4950 #define PFINT_OICR_CTL_ITR_INDX_S 11
4951 #define PFINT_OICR_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4952 #define PFINT_OICR_CTL_CAUSE_ENA_S 30
4953 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
4954 #define PFINT_OICR_CTL_INTEVENT_S 31
4955 #define PFINT_OICR_CTL_INTEVENT_M BIT(31)
4956 #define PFINT_OICR_ENA 0x0016C900 /* Reset Source: CORER */
4957 #define PFINT_OICR_ENA_RSV0_S 0
4958 #define PFINT_OICR_ENA_RSV0_M BIT(0)
4959 #define PFINT_OICR_ENA_INT_ENA_S 1
4960 #define PFINT_OICR_ENA_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4961 #define PFINT_SB_CTL 0x0016B600 /* Reset Source: CORER */
4962 #define PFINT_SB_CTL_MSIX_INDX_S 0
4963 #define PFINT_SB_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4964 #define PFINT_SB_CTL_ITR_INDX_S 11
4965 #define PFINT_SB_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4966 #define PFINT_SB_CTL_CAUSE_ENA_S 30
4967 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
4968 #define PFINT_SB_CTL_INTEVENT_S 31
4969 #define PFINT_SB_CTL_INTEVENT_M BIT(31)
4970 #define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */
4971 #define PFINT_TSYN_MSK_PHY_INDX_S 0
4972 #define PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0)
4973 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4974 #define QINT_RQCTL_MAX_INDEX 2047
4975 #define QINT_RQCTL_MSIX_INDX_S 0
4976 #define QINT_RQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4977 #define QINT_RQCTL_ITR_INDX_S 11
4978 #define QINT_RQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4979 #define QINT_RQCTL_CAUSE_ENA_S 30
4980 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
4981 #define QINT_RQCTL_INTEVENT_S 31
4982 #define QINT_RQCTL_INTEVENT_M BIT(31)
4983 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
4984 #define QINT_TQCTL_MAX_INDEX 16383
4985 #define QINT_TQCTL_MSIX_INDX_S 0
4986 #define QINT_TQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4987 #define QINT_TQCTL_ITR_INDX_S 11
4988 #define QINT_TQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4989 #define QINT_TQCTL_CAUSE_ENA_S 30
4990 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
4991 #define QINT_TQCTL_INTEVENT_S 31
4992 #define QINT_TQCTL_INTEVENT_M BIT(31)
4993 #define VPINT_AEQCTL(_VF) (0x0016B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
4994 #define VPINT_AEQCTL_MAX_INDEX 255
4995 #define VPINT_AEQCTL_MSIX_INDX_S 0
4996 #define VPINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4997 #define VPINT_AEQCTL_ITR_INDX_S 11
4998 #define VPINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4999 #define VPINT_AEQCTL_CAUSE_ENA_S 30
5000 #define VPINT_AEQCTL_CAUSE_ENA_M BIT(30)
5001 #define VPINT_AEQCTL_INTEVENT_S 31
5002 #define VPINT_AEQCTL_INTEVENT_M BIT(31)
5003 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5004 #define VPINT_ALLOC_MAX_INDEX 255
5005 #define VPINT_ALLOC_FIRST_S 0
5006 #define VPINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
5007 #define VPINT_ALLOC_LAST_S 12
5008 #define VPINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
5009 #define VPINT_ALLOC_VALID_S 31
5010 #define VPINT_ALLOC_VALID_M BIT(31)
5011 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
5012 #define VPINT_ALLOC_PCI_MAX_INDEX 255
5013 #define VPINT_ALLOC_PCI_FIRST_S 0
5014 #define VPINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
5015 #define VPINT_ALLOC_PCI_LAST_S 12
5016 #define VPINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
5017 #define VPINT_ALLOC_PCI_VALID_S 31
5018 #define VPINT_ALLOC_PCI_VALID_M BIT(31)
5019 #define VPINT_MBX_CPM_CTL(_VP128) (0x0016B000 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
5020 #define VPINT_MBX_CPM_CTL_MAX_INDEX 127
5021 #define VPINT_MBX_CPM_CTL_MSIX_INDX_S 0
5022 #define VPINT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5023 #define VPINT_MBX_CPM_CTL_ITR_INDX_S 11
5024 #define VPINT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5025 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_S 30
5026 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
5027 #define VPINT_MBX_CPM_CTL_INTEVENT_S 31
5028 #define VPINT_MBX_CPM_CTL_INTEVENT_M BIT(31)
5029 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
5030 #define VPINT_MBX_CTL_MAX_INDEX 767
5031 #define VPINT_MBX_CTL_MSIX_INDX_S 0
5032 #define VPINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5033 #define VPINT_MBX_CTL_ITR_INDX_S 11
5034 #define VPINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5035 #define VPINT_MBX_CTL_CAUSE_ENA_S 30
5036 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
5037 #define VPINT_MBX_CTL_INTEVENT_S 31
5038 #define VPINT_MBX_CTL_INTEVENT_M BIT(31)
5039 #define VPINT_MBX_HLP_CTL(_VP16) (0x0016B200 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5040 #define VPINT_MBX_HLP_CTL_MAX_INDEX 15
5041 #define VPINT_MBX_HLP_CTL_MSIX_INDX_S 0
5042 #define VPINT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5043 #define VPINT_MBX_HLP_CTL_ITR_INDX_S 11
5044 #define VPINT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5045 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_S 30
5046 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
5047 #define VPINT_MBX_HLP_CTL_INTEVENT_S 31
5048 #define VPINT_MBX_HLP_CTL_INTEVENT_M BIT(31)
5049 #define VPINT_MBX_PSM_CTL(_VP16) (0x0016B240 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5050 #define VPINT_MBX_PSM_CTL_MAX_INDEX 15
5051 #define VPINT_MBX_PSM_CTL_MSIX_INDX_S 0
5052 #define VPINT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5053 #define VPINT_MBX_PSM_CTL_ITR_INDX_S 11
5054 #define VPINT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5055 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_S 30
5056 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
5057 #define VPINT_MBX_PSM_CTL_INTEVENT_S 31
5058 #define VPINT_MBX_PSM_CTL_INTEVENT_M BIT(31)
5059 #define VPINT_SB_CPM_CTL(_VP128) (0x0016B400 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
5060 #define VPINT_SB_CPM_CTL_MAX_INDEX 127
5061 #define VPINT_SB_CPM_CTL_MSIX_INDX_S 0
5062 #define VPINT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5063 #define VPINT_SB_CPM_CTL_ITR_INDX_S 11
5064 #define VPINT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5065 #define VPINT_SB_CPM_CTL_CAUSE_ENA_S 30
5066 #define VPINT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
5067 #define VPINT_SB_CPM_CTL_INTEVENT_S 31
5068 #define VPINT_SB_CPM_CTL_INTEVENT_M BIT(31)
5069 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE(_i) (0x00049240 + ((_i) * 4)) /* _i=0...20 */ /* Reset Source: CORER */
5070 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_MAX_INDEX 20
5071 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_S 0
5072 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_M MAKEMASK(0xFF, 0)
5073 #define GL_TDPU_PSM_DEFAULT_RECIPE(_i) (0x00049294 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5074 #define GL_TDPU_PSM_DEFAULT_RECIPE_MAX_INDEX 3
5075 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_S 0
5076 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M BIT(0)
5077 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_S 1
5078 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_M BIT(1)
5079 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_S 2
5080 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_M BIT(2)
5081 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_S 3
5082 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_M BIT(3)
5083 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_S 4
5084 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_M BIT(4)
5085 #define GLLAN_PF_RECIPE(_i) (0x0029420C + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5086 #define GLLAN_PF_RECIPE_MAX_INDEX 7
5087 #define GLLAN_PF_RECIPE_RECIPE_S 0
5088 #define GLLAN_PF_RECIPE_RECIPE_M MAKEMASK(0x3, 0)
5089 #define GLLAN_RCTL_0 0x002941F8 /* Reset Source: CORER */
5090 #define GLLAN_RCTL_0_PXE_MODE_S 0
5091 #define GLLAN_RCTL_0_PXE_MODE_M BIT(0)
5092 #define GLLAN_RCTL_1 0x002941FC /* Reset Source: CORER */
5093 #define GLLAN_RCTL_1_RXMAX_EXPANSION_S 12
5094 #define GLLAN_RCTL_1_RXMAX_EXPANSION_M MAKEMASK(0xF, 12)
5095 #define GLLAN_RCTL_1_RXDRDCTL_S 17
5096 #define GLLAN_RCTL_1_RXDRDCTL_M BIT(17)
5097 #define GLLAN_RCTL_1_RXDESCRDROEN_S 18
5098 #define GLLAN_RCTL_1_RXDESCRDROEN_M BIT(18)
5099 #define GLLAN_RCTL_1_RXDATAWRROEN_S 19
5100 #define GLLAN_RCTL_1_RXDATAWRROEN_M BIT(19)
5101 #define GLLAN_TSOMSK_F 0x00049308 /* Reset Source: CORER */
5102 #define GLLAN_TSOMSK_F_TCPMSKF_S 0
5103 #define GLLAN_TSOMSK_F_TCPMSKF_M MAKEMASK(0xFFF, 0)
5104 #define GLLAN_TSOMSK_L 0x00049310 /* Reset Source: CORER */
5105 #define GLLAN_TSOMSK_L_TCPMSKL_S 0
5106 #define GLLAN_TSOMSK_L_TCPMSKL_M MAKEMASK(0xFFF, 0)
5107 #define GLLAN_TSOMSK_M 0x0004930C /* Reset Source: CORER */
5108 #define GLLAN_TSOMSK_M_TCPMSKM_S 0
5109 #define GLLAN_TSOMSK_M_TCPMSKM_M MAKEMASK(0xFFF, 0)
5110 #define PFLAN_CP_QALLOC 0x00075700 /* Reset Source: CORER */
5111 #define PFLAN_CP_QALLOC_FIRSTQ_S 0
5112 #define PFLAN_CP_QALLOC_FIRSTQ_M MAKEMASK(0x1FF, 0)
5113 #define PFLAN_CP_QALLOC_LASTQ_S 16
5114 #define PFLAN_CP_QALLOC_LASTQ_M MAKEMASK(0x1FF, 16)
5115 #define PFLAN_CP_QALLOC_VALID_S 31
5116 #define PFLAN_CP_QALLOC_VALID_M BIT(31)
5117 #define PFLAN_DB_QALLOC 0x00075680 /* Reset Source: CORER */
5118 #define PFLAN_DB_QALLOC_FIRSTQ_S 0
5119 #define PFLAN_DB_QALLOC_FIRSTQ_M MAKEMASK(0xFF, 0)
5120 #define PFLAN_DB_QALLOC_LASTQ_S 16
5121 #define PFLAN_DB_QALLOC_LASTQ_M MAKEMASK(0xFF, 16)
5122 #define PFLAN_DB_QALLOC_VALID_S 31
5123 #define PFLAN_DB_QALLOC_VALID_M BIT(31)
5124 #define PFLAN_RX_QALLOC 0x001D2500 /* Reset Source: CORER */
5125 #define PFLAN_RX_QALLOC_FIRSTQ_S 0
5126 #define PFLAN_RX_QALLOC_FIRSTQ_M MAKEMASK(0x7FF, 0)
5127 #define PFLAN_RX_QALLOC_LASTQ_S 16
5128 #define PFLAN_RX_QALLOC_LASTQ_M MAKEMASK(0x7FF, 16)
5129 #define PFLAN_RX_QALLOC_VALID_S 31
5130 #define PFLAN_RX_QALLOC_VALID_M BIT(31)
5131 #define PFLAN_TX_QALLOC 0x001D2580 /* Reset Source: CORER */
5132 #define PFLAN_TX_QALLOC_FIRSTQ_S 0
5133 #define PFLAN_TX_QALLOC_FIRSTQ_M MAKEMASK(0x3FFF, 0)
5134 #define PFLAN_TX_QALLOC_LASTQ_S 16
5135 #define PFLAN_TX_QALLOC_LASTQ_M MAKEMASK(0x3FFF, 16)
5136 #define PFLAN_TX_QALLOC_VALID_S 31
5137 #define PFLAN_TX_QALLOC_VALID_M BIT(31)
5138 #define PRT_TDPUL2TAGSEN 0x00040BA0 /* Reset Source: CORER */
5139 #define PRT_TDPUL2TAGSEN_ENABLE_S 0
5140 #define PRT_TDPUL2TAGSEN_ENABLE_M MAKEMASK(0xFF, 0)
5141 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_S 8
5142 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_M MAKEMASK(0xFF, 8)
5143 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */
5144 #define QRX_CONTEXT_MAX_INDEX 7
5145 #define QRX_CONTEXT_RXQ_CONTEXT_S 0
5146 #define QRX_CONTEXT_RXQ_CONTEXT_M MAKEMASK(0xFFFFFFFF, 0)
5147 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */
5148 #define QRX_CTRL_MAX_INDEX 2047
5149 #define QRX_CTRL_QENA_REQ_S 0
5150 #define QRX_CTRL_QENA_REQ_M BIT(0)
5151 #define QRX_CTRL_FAST_QDIS_S 1
5152 #define QRX_CTRL_FAST_QDIS_M BIT(1)
5153 #define QRX_CTRL_QENA_STAT_S 2
5154 #define QRX_CTRL_QENA_STAT_M BIT(2)
5155 #define QRX_CTRL_CDE_S 3
5156 #define QRX_CTRL_CDE_M BIT(3)
5157 #define QRX_CTRL_CDS_S 4
5158 #define QRX_CTRL_CDS_M BIT(4)
5159 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5160 #define QRX_ITR_MAX_INDEX 2047
5161 #define QRX_ITR_NO_EXPR_S 0
5162 #define QRX_ITR_NO_EXPR_M BIT(0)
5163 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5164 #define QRX_TAIL_MAX_INDEX 2047
5165 #define QRX_TAIL_TAIL_S 0
5166 #define QRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
5167 #define VPDSI_RX_QTABLE(_i, _VP16) (0x00074C00 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5168 #define VPDSI_RX_QTABLE_MAX_INDEX 15
5169 #define VPDSI_RX_QTABLE_PAGE_INDEX0_S 0
5170 #define VPDSI_RX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5171 #define VPDSI_RX_QTABLE_PAGE_INDEX1_S 8
5172 #define VPDSI_RX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5173 #define VPDSI_RX_QTABLE_PAGE_INDEX2_S 16
5174 #define VPDSI_RX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5175 #define VPDSI_RX_QTABLE_PAGE_INDEX3_S 24
5176 #define VPDSI_RX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5177 #define VPDSI_TX_QTABLE(_i, _VP16) (0x001D2000 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5178 #define VPDSI_TX_QTABLE_MAX_INDEX 15
5179 #define VPDSI_TX_QTABLE_PAGE_INDEX0_S 0
5180 #define VPDSI_TX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5181 #define VPDSI_TX_QTABLE_PAGE_INDEX1_S 8
5182 #define VPDSI_TX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5183 #define VPDSI_TX_QTABLE_PAGE_INDEX2_S 16
5184 #define VPDSI_TX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5185 #define VPDSI_TX_QTABLE_PAGE_INDEX3_S 24
5186 #define VPDSI_TX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5187 #define VPLAN_DB_QTABLE(_i, _VF) (0x00070000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...3, _VF=0...255 */ /* Reset Source: CORER */
5188 #define VPLAN_DB_QTABLE_MAX_INDEX 3
5189 #define VPLAN_DB_QTABLE_QINDEX_S 0
5190 #define VPLAN_DB_QTABLE_QINDEX_M MAKEMASK(0x1FF, 0)
5191 #define VPLAN_DSI_VF_MODE(_VP16) (0x002D2C00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5192 #define VPLAN_DSI_VF_MODE_MAX_INDEX 15
5193 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_S 0
5194 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M BIT(0)
5195 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5196 #define VPLAN_RX_QBASE_MAX_INDEX 255
5197 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0
5198 #define VPLAN_RX_QBASE_VFFIRSTQ_M MAKEMASK(0x7FF, 0)
5199 #define VPLAN_RX_QBASE_VFNUMQ_S 16
5200 #define VPLAN_RX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5201 #define VPLAN_RX_QBASE_VFQTABLE_ENA_S 31
5202 #define VPLAN_RX_QBASE_VFQTABLE_ENA_M BIT(31)
5203 #define VPLAN_RX_QTABLE(_i, _VF) (0x00060000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5204 #define VPLAN_RX_QTABLE_MAX_INDEX 15
5205 #define VPLAN_RX_QTABLE_QINDEX_S 0
5206 #define VPLAN_RX_QTABLE_QINDEX_M MAKEMASK(0xFFF, 0)
5207 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5208 #define VPLAN_RXQ_MAPENA_MAX_INDEX 255
5209 #define VPLAN_RXQ_MAPENA_RX_ENA_S 0
5210 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
5211 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5212 #define VPLAN_TX_QBASE_MAX_INDEX 255
5213 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0
5214 #define VPLAN_TX_QBASE_VFFIRSTQ_M MAKEMASK(0x3FFF, 0)
5215 #define VPLAN_TX_QBASE_VFNUMQ_S 16
5216 #define VPLAN_TX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5217 #define VPLAN_TX_QBASE_VFQTABLE_ENA_S 31
5218 #define VPLAN_TX_QBASE_VFQTABLE_ENA_M BIT(31)
5219 #define VPLAN_TX_QTABLE(_i, _VF) (0x001C0000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5220 #define VPLAN_TX_QTABLE_MAX_INDEX 15
5221 #define VPLAN_TX_QTABLE_QINDEX_S 0
5222 #define VPLAN_TX_QTABLE_QINDEX_M MAKEMASK(0x7FFF, 0)
5223 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5224 #define VPLAN_TXQ_MAPENA_MAX_INDEX 255
5225 #define VPLAN_TXQ_MAPENA_TX_ENA_S 0
5226 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
5227 #define VSILAN_QBASE(_VSI) (0x0044C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
5228 #define VSILAN_QBASE_MAX_INDEX 767
5229 #define VSILAN_QBASE_VSIBASE_S 0
5230 #define VSILAN_QBASE_VSIBASE_M MAKEMASK(0x7FF, 0)
5231 #define VSILAN_QBASE_VSIQTABLE_ENA_S 11
5232 #define VSILAN_QBASE_VSIQTABLE_ENA_M BIT(11)
5233 #define VSILAN_QTABLE(_i, _VSI) (0x00440000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...7, _VSI=0...767 */ /* Reset Source: PFR */
5234 #define VSILAN_QTABLE_MAX_INDEX 7
5235 #define VSILAN_QTABLE_QINDEX_0_S 0
5236 #define VSILAN_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0)
5237 #define VSILAN_QTABLE_QINDEX_1_S 16
5238 #define VSILAN_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16)
5239 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */
5240 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0
5241 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
5242 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */
5243 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
5244 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
5245 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
5246 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
5247 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
5248 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
5249 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
5250 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
5251 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
5252 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
5253 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5254 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
5255 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
5256 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
5257 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
5258 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
5259 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5260 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
5261 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
5262 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5263 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */
5264 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0
5265 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)
5266 #define PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */
5267 #define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0
5268 #define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)
5269 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */
5270 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0
5271 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5272 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5273 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
5274 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0
5275 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
5276 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5277 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
5278 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
5279 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
5280 #define PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */
5281 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
5282 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5283 #define PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */
5284 #define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0
5285 #define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)
5286 #define PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */
5287 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0
5288 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0)
5289 #define PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5290 #define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 7
5291 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5292 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5293 #define PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5294 #define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 7
5295 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5296 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5297 #define PRTMAC_RX_CNT_MRKR 0x001E48E0 /* Reset Source: GLOBR */
5298 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S 0
5299 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5300 #define PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */
5301 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S 0
5302 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0)
5303 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16
5304 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)
5305 #define PRTMAC_TX_CNT_MRKR 0x001E48C0 /* Reset Source: GLOBR */
5306 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S 0
5307 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5308 #define PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */
5309 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S 0
5310 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M MAKEMASK(0xFFFF, 0)
5311 #define GL_MDCK_CFG1_TX_PQM 0x002D2DF4 /* Reset Source: CORER */
5312 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_S 0
5313 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_M MAKEMASK(0xFF, 0)
5314 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_S 8
5315 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_M MAKEMASK(0x3F, 8)
5316 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_S 16
5317 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_M MAKEMASK(0x3F, 16)
5318 #define GL_MDCK_EN_TX_PQM 0x002D2DFC /* Reset Source: CORER */
5319 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_S 0
5320 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M BIT(0)
5321 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_S 1
5322 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_M BIT(1)
5323 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_S 3
5324 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_M BIT(3)
5325 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_S 4
5326 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_M BIT(4)
5327 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_S 5
5328 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_M BIT(5)
5329 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_S 6
5330 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_M BIT(6)
5331 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_S 7
5332 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_M BIT(7)
5333 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_S 8
5334 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_M BIT(8)
5335 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_S 9
5336 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_M BIT(9)
5337 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_S 10
5338 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_M BIT(10)
5339 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_S 11
5340 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_M BIT(11)
5341 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_S 12
5342 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_M BIT(12)
5343 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_S 13
5344 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_M BIT(13)
5345 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_S 14
5346 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_M BIT(14)
5347 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S 15
5348 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15)
5349 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S 16
5350 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16)
5351 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S 17
5352 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)
5353 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18
5354 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)
5355 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
5356 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
5357 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
5358 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
5359 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21
5360 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)
5361 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22
5362 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)
5363 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S 23
5364 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23)
5365 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S 24
5366 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)
5367 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25
5368 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)
5369 #define GL_MDCK_EN_TX_PQM_RSVD_S 26
5370 #define GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
5371 #define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
5372 #define GL_MDCK_RX_DESC_ADDR_S 0
5373 #define GL_MDCK_RX_DESC_ADDR_M BIT(0)
5374 #define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
5375 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
5376 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
5377 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
5378 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
5379 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
5380 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
5381 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
5382 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
5383 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
5384 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
5385 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
5386 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
5387 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
5388 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
5389 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
5390 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
5391 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
5392 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
5393 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
5394 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
5395 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
5396 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
5397 #define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
5398 #define GL_MDET_RX_QNUM_S 0
5399 #define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
5400 #define GL_MDET_RX_VF_NUM_S 15
5401 #define GL_MDET_RX_VF_NUM_M MAKEMASK(0xFF, 15)
5402 #define GL_MDET_RX_PF_NUM_S 23
5403 #define GL_MDET_RX_PF_NUM_M MAKEMASK(0x7, 23)
5404 #define GL_MDET_RX_MAL_TYPE_S 26
5405 #define GL_MDET_RX_MAL_TYPE_M MAKEMASK(0x1F, 26)
5406 #define GL_MDET_RX_VALID_S 31
5407 #define GL_MDET_RX_VALID_M BIT(31)
5408 #define GL_MDET_TX_PQM 0x002D2E00 /* Reset Source: CORER */
5409 #define GL_MDET_TX_PQM_PF_NUM_S 0
5410 #define GL_MDET_TX_PQM_PF_NUM_M MAKEMASK(0x7, 0)
5411 #define GL_MDET_TX_PQM_VF_NUM_S 4
5412 #define GL_MDET_TX_PQM_VF_NUM_M MAKEMASK(0xFF, 4)
5413 #define GL_MDET_TX_PQM_QNUM_S 12
5414 #define GL_MDET_TX_PQM_QNUM_M MAKEMASK(0x3FFF, 12)
5415 #define GL_MDET_TX_PQM_MAL_TYPE_S 26
5416 #define GL_MDET_TX_PQM_MAL_TYPE_M MAKEMASK(0x1F, 26)
5417 #define GL_MDET_TX_PQM_VALID_S 31
5418 #define GL_MDET_TX_PQM_VALID_M BIT(31)
5419 #define GL_MDET_TX_TCLAN 0x000FC068 /* Reset Source: CORER */
5420 #define GL_MDET_TX_TCLAN_QNUM_S 0
5421 #define GL_MDET_TX_TCLAN_QNUM_M MAKEMASK(0x7FFF, 0)
5422 #define GL_MDET_TX_TCLAN_VF_NUM_S 15
5423 #define GL_MDET_TX_TCLAN_VF_NUM_M MAKEMASK(0xFF, 15)
5424 #define GL_MDET_TX_TCLAN_PF_NUM_S 23
5425 #define GL_MDET_TX_TCLAN_PF_NUM_M MAKEMASK(0x7, 23)
5426 #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26
5427 #define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
5428 #define GL_MDET_TX_TCLAN_VALID_S 31
5429 #define GL_MDET_TX_TCLAN_VALID_M BIT(31)
5430 #define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
5431 #define GL_MDET_TX_TDPU_QNUM_S 0
5432 #define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
5433 #define GL_MDET_TX_TDPU_VF_NUM_S 15
5434 #define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
5435 #define GL_MDET_TX_TDPU_PF_NUM_S 23
5436 #define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
5437 #define GL_MDET_TX_TDPU_MAL_TYPE_S 26
5438 #define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
5439 #define GL_MDET_TX_TDPU_VALID_S 31
5440 #define GL_MDET_TX_TDPU_VALID_M BIT(31)
5441 #define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
5442 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
5443 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
5444 #define PF_MDET_RX 0x00294280 /* Reset Source: CORER */
5445 #define PF_MDET_RX_VALID_S 0
5446 #define PF_MDET_RX_VALID_M BIT(0)
5447 #define PF_MDET_TX_PQM 0x002D2C80 /* Reset Source: CORER */
5448 #define PF_MDET_TX_PQM_VALID_S 0
5449 #define PF_MDET_TX_PQM_VALID_M BIT(0)
5450 #define PF_MDET_TX_TCLAN 0x000FC000 /* Reset Source: CORER */
5451 #define PF_MDET_TX_TCLAN_VALID_S 0
5452 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
5453 #define PF_MDET_TX_TDPU 0x00040800 /* Reset Source: CORER */
5454 #define PF_MDET_TX_TDPU_VALID_S 0
5455 #define PF_MDET_TX_TDPU_VALID_M BIT(0)
5456 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5457 #define VP_MDET_RX_MAX_INDEX 255
5458 #define VP_MDET_RX_VALID_S 0
5459 #define VP_MDET_RX_VALID_M BIT(0)
5460 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5461 #define VP_MDET_TX_PQM_MAX_INDEX 255
5462 #define VP_MDET_TX_PQM_VALID_S 0
5463 #define VP_MDET_TX_PQM_VALID_M BIT(0)
5464 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5465 #define VP_MDET_TX_TCLAN_MAX_INDEX 255
5466 #define VP_MDET_TX_TCLAN_VALID_S 0
5467 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
5468 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5469 #define VP_MDET_TX_TDPU_MAX_INDEX 255
5470 #define VP_MDET_TX_TDPU_VALID_S 0
5471 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
5472 #define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */
5473 #define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9
5474 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
5475 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
5476 #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
5477 #define GL_FWRESETCNT_FWRESETCNT_S 0
5478 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
5479 #define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
5480 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0
5481 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
5482 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1
5483 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1)
5484 #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */
5485 #define GL_MNG_FWSM_FW_LOADING_M BIT(30)
5486 #define GL_MNG_FWSM_FW_MODES_S 0
5487 #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0)
5488 #define GL_MNG_FWSM_RSV0_S 3
5489 #define GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3)
5490 #define GL_MNG_FWSM_EEP_RELOAD_IND_S 10
5491 #define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10)
5492 #define GL_MNG_FWSM_RSV1_S 11
5493 #define GL_MNG_FWSM_RSV1_M MAKEMASK(0xF, 11)
5494 #define GL_MNG_FWSM_RSV2_S 15
5495 #define GL_MNG_FWSM_RSV2_M BIT(15)
5496 #define GL_MNG_FWSM_PCIR_AL_FAILURE_S 16
5497 #define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16)
5498 #define GL_MNG_FWSM_POR_AL_FAILURE_S 17
5499 #define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17)
5500 #define GL_MNG_FWSM_RSV3_S 18
5501 #define GL_MNG_FWSM_RSV3_M BIT(18)
5502 #define GL_MNG_FWSM_EXT_ERR_IND_S 19
5503 #define GL_MNG_FWSM_EXT_ERR_IND_M MAKEMASK(0x3F, 19)
5504 #define GL_MNG_FWSM_RSV4_S 25
5505 #define GL_MNG_FWSM_RSV4_M BIT(25)
5506 #define GL_MNG_FWSM_RESERVED_11_S 26
5507 #define GL_MNG_FWSM_RESERVED_11_M MAKEMASK(0xF, 26)
5508 #define GL_MNG_FWSM_RSV5_S 30
5509 #define GL_MNG_FWSM_RSV5_M MAKEMASK(0x3, 30)
5510 #define GL_MNG_HWARB_CTRL 0x000B6130 /* Reset Source: POR */
5511 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S 0
5512 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0)
5513 #define GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5514 #define GL_MNG_SHA_EXTEND_MAX_INDEX 7
5515 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S 0
5516 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M MAKEMASK(0xFFFFFFFF, 0)
5517 #define GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5518 #define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 7
5519 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0
5520 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0)
5521 #define GL_MNG_SHA_EXTEND_STATUS 0x00083148 /* Reset Source: EMPR */
5522 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_S 0
5523 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_M MAKEMASK(0x7, 0)
5524 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_S 30
5525 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_M BIT(30)
5526 #define GL_MNG_SHA_EXTEND_STATUS_DONE_S 31
5527 #define GL_MNG_SHA_EXTEND_STATUS_DONE_M BIT(31)
5528 #define GL_SWT_PRT2MDEF(_i) (0x00216018 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: POR */
5529 #define GL_SWT_PRT2MDEF_MAX_INDEX 31
5530 #define GL_SWT_PRT2MDEF_MDEFIDX_S 0
5531 #define GL_SWT_PRT2MDEF_MDEFIDX_M MAKEMASK(0x7, 0)
5532 #define GL_SWT_PRT2MDEF_MDEFENA_S 31
5533 #define GL_SWT_PRT2MDEF_MDEFENA_M BIT(31)
5534 #define PRT_MNG_MANC 0x00214720 /* Reset Source: POR */
5535 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_S 0
5536 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M BIT(0)
5537 #define PRT_MNG_MANC_NCSI_DISCARD_S 1
5538 #define PRT_MNG_MANC_NCSI_DISCARD_M BIT(1)
5539 #define PRT_MNG_MANC_RCV_TCO_EN_S 17
5540 #define PRT_MNG_MANC_RCV_TCO_EN_M BIT(17)
5541 #define PRT_MNG_MANC_RCV_ALL_S 19
5542 #define PRT_MNG_MANC_RCV_ALL_M BIT(19)
5543 #define PRT_MNG_MANC_FIXED_NET_TYPE_S 25
5544 #define PRT_MNG_MANC_FIXED_NET_TYPE_M BIT(25)
5545 #define PRT_MNG_MANC_NET_TYPE_S 26
5546 #define PRT_MNG_MANC_NET_TYPE_M BIT(26)
5547 #define PRT_MNG_MANC_EN_BMC2OS_S 28
5548 #define PRT_MNG_MANC_EN_BMC2OS_M BIT(28)
5549 #define PRT_MNG_MANC_EN_BMC2NET_S 29
5550 #define PRT_MNG_MANC_EN_BMC2NET_M BIT(29)
5551 #define PRT_MNG_MAVTV(_i) (0x00214780 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5552 #define PRT_MNG_MAVTV_MAX_INDEX 7
5553 #define PRT_MNG_MAVTV_VID_S 0
5554 #define PRT_MNG_MAVTV_VID_M MAKEMASK(0xFFF, 0)
5555 #define PRT_MNG_MDEF(_i) (0x00214880 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5556 #define PRT_MNG_MDEF_MAX_INDEX 7
5557 #define PRT_MNG_MDEF_MAC_EXACT_AND_S 0
5558 #define PRT_MNG_MDEF_MAC_EXACT_AND_M MAKEMASK(0xF, 0)
5559 #define PRT_MNG_MDEF_BROADCAST_AND_S 4
5560 #define PRT_MNG_MDEF_BROADCAST_AND_M BIT(4)
5561 #define PRT_MNG_MDEF_VLAN_AND_S 5
5562 #define PRT_MNG_MDEF_VLAN_AND_M MAKEMASK(0xFF, 5)
5563 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_S 13
5564 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_M MAKEMASK(0xF, 13)
5565 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_S 17
5566 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_M MAKEMASK(0xF, 17)
5567 #define PRT_MNG_MDEF_MAC_EXACT_OR_S 21
5568 #define PRT_MNG_MDEF_MAC_EXACT_OR_M MAKEMASK(0xF, 21)
5569 #define PRT_MNG_MDEF_BROADCAST_OR_S 25
5570 #define PRT_MNG_MDEF_BROADCAST_OR_M BIT(25)
5571 #define PRT_MNG_MDEF_MULTICAST_AND_S 26
5572 #define PRT_MNG_MDEF_MULTICAST_AND_M BIT(26)
5573 #define PRT_MNG_MDEF_ARP_REQUEST_OR_S 27
5574 #define PRT_MNG_MDEF_ARP_REQUEST_OR_M BIT(27)
5575 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_S 28
5576 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_M BIT(28)
5577 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_S 29
5578 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_M BIT(29)
5579 #define PRT_MNG_MDEF_PORT_0X298_OR_S 30
5580 #define PRT_MNG_MDEF_PORT_0X298_OR_M BIT(30)
5581 #define PRT_MNG_MDEF_PORT_0X26F_OR_S 31
5582 #define PRT_MNG_MDEF_PORT_0X26F_OR_M BIT(31)
5583 #define PRT_MNG_MDEF_EXT(_i) (0x00214A00 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5584 #define PRT_MNG_MDEF_EXT_MAX_INDEX 7
5585 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_S 0
5586 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_M MAKEMASK(0xF, 0)
5587 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_S 4
5588 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_M MAKEMASK(0xF, 4)
5589 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_S 8
5590 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_M MAKEMASK(0xFFFF, 8)
5591 #define PRT_MNG_MDEF_EXT_FLEX_TCO_S 24
5592 #define PRT_MNG_MDEF_EXT_FLEX_TCO_M BIT(24)
5593 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_S 25
5594 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_M BIT(25)
5595 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_S 26
5596 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_M BIT(26)
5597 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_S 27
5598 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_M BIT(27)
5599 #define PRT_MNG_MDEF_EXT_ICMP_OR_S 28
5600 #define PRT_MNG_MDEF_EXT_ICMP_OR_M BIT(28)
5601 #define PRT_MNG_MDEF_EXT_MLD_S 29
5602 #define PRT_MNG_MDEF_EXT_MLD_M BIT(29)
5603 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_S 30
5604 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_M BIT(30)
5605 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_S 31
5606 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_M BIT(31)
5607 #define PRT_MNG_MDEFVSI(_i) (0x00214980 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5608 #define PRT_MNG_MDEFVSI_MAX_INDEX 3
5609 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_S 0
5610 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_M MAKEMASK(0xFFFF, 0)
5611 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_S 16
5612 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_M MAKEMASK(0xFFFF, 16)
5613 #define PRT_MNG_METF(_i) (0x00214120 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5614 #define PRT_MNG_METF_MAX_INDEX 3
5615 #define PRT_MNG_METF_ETYPE_S 0
5616 #define PRT_MNG_METF_ETYPE_M MAKEMASK(0xFFFF, 0)
5617 #define PRT_MNG_METF_POLARITY_S 30
5618 #define PRT_MNG_METF_POLARITY_M BIT(30)
5619 #define PRT_MNG_MFUTP(_i) (0x00214320 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5620 #define PRT_MNG_MFUTP_MAX_INDEX 15
5621 #define PRT_MNG_MFUTP_MFUTP_N_S 0
5622 #define PRT_MNG_MFUTP_MFUTP_N_M MAKEMASK(0xFFFF, 0)
5623 #define PRT_MNG_MFUTP_UDP_S 16
5624 #define PRT_MNG_MFUTP_UDP_M BIT(16)
5625 #define PRT_MNG_MFUTP_TCP_S 17
5626 #define PRT_MNG_MFUTP_TCP_M BIT(17)
5627 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_S 18
5628 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_M BIT(18)
5629 #define PRT_MNG_MIPAF4(_i) (0x002141A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5630 #define PRT_MNG_MIPAF4_MAX_INDEX 3
5631 #define PRT_MNG_MIPAF4_MIPAF_S 0
5632 #define PRT_MNG_MIPAF4_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5633 #define PRT_MNG_MIPAF6(_i) (0x00214520 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5634 #define PRT_MNG_MIPAF6_MAX_INDEX 15
5635 #define PRT_MNG_MIPAF6_MIPAF_S 0
5636 #define PRT_MNG_MIPAF6_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5637 #define PRT_MNG_MMAH(_i) (0x00214220 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5638 #define PRT_MNG_MMAH_MAX_INDEX 3
5639 #define PRT_MNG_MMAH_MMAH_S 0
5640 #define PRT_MNG_MMAH_MMAH_M MAKEMASK(0xFFFF, 0)
5641 #define PRT_MNG_MMAL(_i) (0x002142A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5642 #define PRT_MNG_MMAL_MAX_INDEX 3
5643 #define PRT_MNG_MMAL_MMAL_S 0
5644 #define PRT_MNG_MMAL_MMAL_M MAKEMASK(0xFFFFFFFF, 0)
5645 #define PRT_MNG_MNGONLY 0x00214740 /* Reset Source: POR */
5646 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_S 0
5647 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_M MAKEMASK(0xFF, 0)
5648 #define PRT_MNG_MSFM 0x00214760 /* Reset Source: POR */
5649 #define PRT_MNG_MSFM_PORT_26F_UDP_S 0
5650 #define PRT_MNG_MSFM_PORT_26F_UDP_M BIT(0)
5651 #define PRT_MNG_MSFM_PORT_26F_TCP_S 1
5652 #define PRT_MNG_MSFM_PORT_26F_TCP_M BIT(1)
5653 #define PRT_MNG_MSFM_PORT_298_UDP_S 2
5654 #define PRT_MNG_MSFM_PORT_298_UDP_M BIT(2)
5655 #define PRT_MNG_MSFM_PORT_298_TCP_S 3
5656 #define PRT_MNG_MSFM_PORT_298_TCP_M BIT(3)
5657 #define PRT_MNG_MSFM_IPV6_0_MASK_S 4
5658 #define PRT_MNG_MSFM_IPV6_0_MASK_M BIT(4)
5659 #define PRT_MNG_MSFM_IPV6_1_MASK_S 5
5660 #define PRT_MNG_MSFM_IPV6_1_MASK_M BIT(5)
5661 #define PRT_MNG_MSFM_IPV6_2_MASK_S 6
5662 #define PRT_MNG_MSFM_IPV6_2_MASK_M BIT(6)
5663 #define PRT_MNG_MSFM_IPV6_3_MASK_S 7
5664 #define PRT_MNG_MSFM_IPV6_3_MASK_M BIT(7)
5665 #define MSIX_PBA_PAGE(_i) (0x02E08000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5666 #define MSIX_PBA_PAGE_MAX_INDEX 63
5667 #define MSIX_PBA_PAGE_PENBIT_S 0
5668 #define MSIX_PBA_PAGE_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5669 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5670 #define MSIX_PBA1_MAX_INDEX 63
5671 #define MSIX_PBA1_PENBIT_S 0
5672 #define MSIX_PBA1_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5673 #define MSIX_TADD_PAGE(_i) (0x02E00000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5674 #define MSIX_TADD_PAGE_MAX_INDEX 2047
5675 #define MSIX_TADD_PAGE_MSIXTADD10_S 0
5676 #define MSIX_TADD_PAGE_MSIXTADD10_M MAKEMASK(0x3, 0)
5677 #define MSIX_TADD_PAGE_MSIXTADD_S 2
5678 #define MSIX_TADD_PAGE_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5679 #define MSIX_TADD1(_i) (0x00000000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5680 #define MSIX_TADD1_MAX_INDEX 2047
5681 #define MSIX_TADD1_MSIXTADD10_S 0
5682 #define MSIX_TADD1_MSIXTADD10_M MAKEMASK(0x3, 0)
5683 #define MSIX_TADD1_MSIXTADD_S 2
5684 #define MSIX_TADD1_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5685 #define MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5686 #define MSIX_TMSG_MAX_INDEX 2047
5687 #define MSIX_TMSG_MSIXTMSG_S 0
5688 #define MSIX_TMSG_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5689 #define MSIX_TMSG_PAGE(_i) (0x02E00008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5690 #define MSIX_TMSG_PAGE_MAX_INDEX 2047
5691 #define MSIX_TMSG_PAGE_MSIXTMSG_S 0
5692 #define MSIX_TMSG_PAGE_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5693 #define MSIX_TUADD_PAGE(_i) (0x02E00004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5694 #define MSIX_TUADD_PAGE_MAX_INDEX 2047
5695 #define MSIX_TUADD_PAGE_MSIXTUADD_S 0
5696 #define MSIX_TUADD_PAGE_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5697 #define MSIX_TUADD1(_i) (0x00000004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5698 #define MSIX_TUADD1_MAX_INDEX 2047
5699 #define MSIX_TUADD1_MSIXTUADD_S 0
5700 #define MSIX_TUADD1_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5701 #define MSIX_TVCTRL_PAGE(_i) (0x02E0000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5702 #define MSIX_TVCTRL_PAGE_MAX_INDEX 2047
5703 #define MSIX_TVCTRL_PAGE_MASK_S 0
5704 #define MSIX_TVCTRL_PAGE_MASK_M BIT(0)
5705 #define MSIX_TVCTRL1(_i) (0x0000000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5706 #define MSIX_TVCTRL1_MAX_INDEX 2047
5707 #define MSIX_TVCTRL1_MASK_S 0
5708 #define MSIX_TVCTRL1_MASK_M BIT(0)
5709 #define GLNVM_AL_DONE_HLP 0x000824C4 /* Reset Source: POR */
5710 #define GLNVM_AL_DONE_HLP_HLP_CORER_S 0
5711 #define GLNVM_AL_DONE_HLP_HLP_CORER_M BIT(0)
5712 #define GLNVM_AL_DONE_HLP_HLP_FULLR_S 1
5713 #define GLNVM_AL_DONE_HLP_HLP_FULLR_M BIT(1)
5714 #define GLNVM_ALTIMERS 0x000B6140 /* Reset Source: POR */
5715 #define GLNVM_ALTIMERS_PCI_ALTIMER_S 0
5716 #define GLNVM_ALTIMERS_PCI_ALTIMER_M MAKEMASK(0xFFF, 0)
5717 #define GLNVM_ALTIMERS_GEN_ALTIMER_S 12
5718 #define GLNVM_ALTIMERS_GEN_ALTIMER_M MAKEMASK(0xFFFFF, 12)
5719 #define GLNVM_FLA 0x000B6108 /* Reset Source: POR */
5720 #define GLNVM_FLA_LOCKED_S 6
5721 #define GLNVM_FLA_LOCKED_M BIT(6)
5722 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */
5723 #define GLNVM_GENS_NVM_PRES_S 0
5724 #define GLNVM_GENS_NVM_PRES_M BIT(0)
5725 #define GLNVM_GENS_SR_SIZE_S 5
5726 #define GLNVM_GENS_SR_SIZE_M MAKEMASK(0x7, 5)
5727 #define GLNVM_GENS_BANK1VAL_S 8
5728 #define GLNVM_GENS_BANK1VAL_M BIT(8)
5729 #define GLNVM_GENS_ALT_PRST_S 23
5730 #define GLNVM_GENS_ALT_PRST_M BIT(23)
5731 #define GLNVM_GENS_FL_AUTO_RD_S 25
5732 #define GLNVM_GENS_FL_AUTO_RD_M BIT(25)
5733 #define GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset Source: POR */
5734 #define GLNVM_PROTCSR_MAX_INDEX 59
5735 #define GLNVM_PROTCSR_ADDR_BLOCK_S 0
5736 #define GLNVM_PROTCSR_ADDR_BLOCK_M MAKEMASK(0xFFFFFF, 0)
5737 #define GLNVM_ULD 0x000B6008 /* Reset Source: POR */
5738 #define GLNVM_ULD_PCIER_DONE_S 0
5739 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
5740 #define GLNVM_ULD_PCIER_DONE_1_S 1
5741 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
5742 #define GLNVM_ULD_CORER_DONE_S 3
5743 #define GLNVM_ULD_CORER_DONE_M BIT(3)
5744 #define GLNVM_ULD_GLOBR_DONE_S 4
5745 #define GLNVM_ULD_GLOBR_DONE_M BIT(4)
5746 #define GLNVM_ULD_POR_DONE_S 5
5747 #define GLNVM_ULD_POR_DONE_M BIT(5)
5748 #define GLNVM_ULD_POR_DONE_1_S 8
5749 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
5750 #define GLNVM_ULD_PCIER_DONE_2_S 9
5751 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
5752 #define GLNVM_ULD_PE_DONE_S 10
5753 #define GLNVM_ULD_PE_DONE_M BIT(10)
5754 #define GLNVM_ULD_HLP_CORE_DONE_S 11
5755 #define GLNVM_ULD_HLP_CORE_DONE_M BIT(11)
5756 #define GLNVM_ULD_HLP_FULL_DONE_S 12
5757 #define GLNVM_ULD_HLP_FULL_DONE_M BIT(12)
5758 #define GLNVM_ULT 0x000B6154 /* Reset Source: POR */
5759 #define GLNVM_ULT_CONF_PCIR_AE_S 0
5760 #define GLNVM_ULT_CONF_PCIR_AE_M BIT(0)
5761 #define GLNVM_ULT_CONF_PCIRTL_AE_S 1
5762 #define GLNVM_ULT_CONF_PCIRTL_AE_M BIT(1)
5763 #define GLNVM_ULT_RESERVED_1_S 2
5764 #define GLNVM_ULT_RESERVED_1_M BIT(2)
5765 #define GLNVM_ULT_CONF_CORE_AE_S 3
5766 #define GLNVM_ULT_CONF_CORE_AE_M BIT(3)
5767 #define GLNVM_ULT_CONF_GLOBAL_AE_S 4
5768 #define GLNVM_ULT_CONF_GLOBAL_AE_M BIT(4)
5769 #define GLNVM_ULT_CONF_POR_AE_S 5
5770 #define GLNVM_ULT_CONF_POR_AE_M BIT(5)
5771 #define GLNVM_ULT_RESERVED_2_S 6
5772 #define GLNVM_ULT_RESERVED_2_M BIT(6)
5773 #define GLNVM_ULT_RESERVED_3_S 7
5774 #define GLNVM_ULT_RESERVED_3_M BIT(7)
5775 #define GLNVM_ULT_RESERVED_5_S 8
5776 #define GLNVM_ULT_RESERVED_5_M BIT(8)
5777 #define GLNVM_ULT_CONF_PCIALT_AE_S 9
5778 #define GLNVM_ULT_CONF_PCIALT_AE_M BIT(9)
5779 #define GLNVM_ULT_CONF_PE_AE_S 10
5780 #define GLNVM_ULT_CONF_PE_AE_M BIT(10)
5781 #define GLNVM_ULT_RESERVED_4_S 11
5782 #define GLNVM_ULT_RESERVED_4_M MAKEMASK(0x1FFFFF, 11)
5783 #define GL_COTF_MARKER_STATUS 0x00200200 /* Reset Source: CORER */
5784 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_S 0
5785 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFF, 0)
5786 #define GL_COTF_MARKER_TRIG_RCU_PRS(_i) (0x002001D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5787 #define GL_COTF_MARKER_TRIG_RCU_PRS_MAX_INDEX 7
5788 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_S 0
5789 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(0)
5790 #define GL_PRS_MARKER_ERROR 0x00200204 /* Reset Source: CORER */
5791 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_S 0
5792 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M BIT(0)
5793 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_S 1
5794 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_M BIT(1)
5795 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_S 2
5796 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_M BIT(2)
5797 #define GL_PRS_RX_PIPE_INIT0(_i) (0x0020000C + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5798 #define GL_PRS_RX_PIPE_INIT0_MAX_INDEX 6
5799 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_S 0
5800 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5801 #define GL_PRS_RX_PIPE_INIT1 0x00200028 /* Reset Source: CORER */
5802 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_S 0
5803 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5804 #define GL_PRS_RX_PIPE_INIT2 0x0020002C /* Reset Source: CORER */
5805 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_S 0
5806 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5807 #define GL_PRS_RX_SIZE_CTRL 0x00200004 /* Reset Source: CORER */
5808 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_S 0
5809 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5810 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_S 15
5811 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
5812 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_S 16
5813 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5814 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_S 31
5815 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
5816 #define GL_PRS_TX_PIPE_INIT0(_i) (0x00202018 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5817 #define GL_PRS_TX_PIPE_INIT0_MAX_INDEX 6
5818 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_S 0
5819 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5820 #define GL_PRS_TX_PIPE_INIT1 0x00202034 /* Reset Source: CORER */
5821 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_S 0
5822 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5823 #define GL_PRS_TX_PIPE_INIT2 0x00202038 /* Reset Source: CORER */
5824 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_S 0
5825 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5826 #define GL_PRS_TX_SIZE_CTRL 0x00202014 /* Reset Source: CORER */
5827 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_S 0
5828 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5829 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_S 15
5830 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
5831 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_S 16
5832 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5833 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_S 31
5834 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
5835 #define GL_QH_MARKER_STATUS 0x002001FC /* Reset Source: CORER */
5836 #define GL_QH_MARKER_STATUS_MRKR_BUSY_S 0
5837 #define GL_QH_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xF, 0)
5838 #define GL_QH_MARKER_TRIG_RCU_PRS(_i) (0x002001C4 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5839 #define GL_QH_MARKER_TRIG_RCU_PRS_MAX_INDEX 3
5840 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_S 0
5841 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_M MAKEMASK(0x3FFFF, 0)
5842 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_S 18
5843 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_M MAKEMASK(0xFF, 18)
5844 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_S 26
5845 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 26)
5846 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_S 31
5847 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(31)
5848 #define GL_RPRS_ANA_CSR_CTRL 0x00200708 /* Reset Source: CORER */
5849 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5850 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5851 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1
5852 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
5853 #define GL_TPRS_ANA_CSR_CTRL 0x00202100 /* Reset Source: CORER */
5854 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5855 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5856 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1
5857 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
5858 #define GL_TPRS_MNG_PM_THR 0x00202004 /* Reset Source: CORER */
5859 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_S 0
5860 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_M MAKEMASK(0x3FFF, 0)
5861 #define GL_TPRS_PM_CNT(_i) (0x00202008 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5862 #define GL_TPRS_PM_CNT_MAX_INDEX 1
5863 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_S 0
5864 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_M MAKEMASK(0x3FFF, 0)
5865 #define GL_TPRS_PM_THR 0x00202000 /* Reset Source: CORER */
5866 #define GL_TPRS_PM_THR_PM_THR_S 0
5867 #define GL_TPRS_PM_THR_PM_THR_M MAKEMASK(0x3FFF, 0)
5868 #define GL_XLR_MARKER_LOG_RCU_PRS(_i) (0x00200208 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
5869 #define GL_XLR_MARKER_LOG_RCU_PRS_MAX_INDEX 63
5870 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_S 0
5871 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_M MAKEMASK(0xFFFFFFFF, 0)
5872 #define GL_XLR_MARKER_STATUS(_i) (0x002001F4 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5873 #define GL_XLR_MARKER_STATUS_MAX_INDEX 1
5874 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_S 0
5875 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFFFFFFFF, 0)
5876 #define GL_XLR_MARKER_TRIG_PE 0x005008C0 /* Reset Source: CORER */
5877 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_S 0
5878 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5879 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_S 10
5880 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5881 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_S 12
5882 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12)
5883 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S 16
5884 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16)
5885 #define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */
5886 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0
5887 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5888 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
5889 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5890 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12
5891 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)
5892 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16
5893 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16)
5894 #define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */
5895 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0
5896 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)
5897 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16
5898 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 16)
5899 #define GLPCI_BYTCTH_NP_C 0x000BFDA8 /* Reset Source: PCIR */
5900 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_S 0
5901 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5902 #define GLPCI_BYTCTH_P 0x0009E970 /* Reset Source: PCIR */
5903 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_S 0
5904 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5905 #define GLPCI_BYTCTL_NP_C 0x000BFDAC /* Reset Source: PCIR */
5906 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_S 0
5907 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5908 #define GLPCI_BYTCTL_P 0x0009E994 /* Reset Source: PCIR */
5909 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_S 0
5910 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5911 #define GLPCI_CAPCTRL 0x0009DE88 /* Reset Source: PCIR */
5912 #define GLPCI_CAPCTRL_VPD_EN_S 0
5913 #define GLPCI_CAPCTRL_VPD_EN_M BIT(0)
5914 #define GLPCI_CAPSUP 0x0009DE8C /* Reset Source: PCIR */
5915 #define GLPCI_CAPSUP_PCIE_VER_S 0
5916 #define GLPCI_CAPSUP_PCIE_VER_M BIT(0)
5917 #define GLPCI_CAPSUP_RESERVED_2_S 1
5918 #define GLPCI_CAPSUP_RESERVED_2_M BIT(1)
5919 #define GLPCI_CAPSUP_LTR_EN_S 2
5920 #define GLPCI_CAPSUP_LTR_EN_M BIT(2)
5921 #define GLPCI_CAPSUP_TPH_EN_S 3
5922 #define GLPCI_CAPSUP_TPH_EN_M BIT(3)
5923 #define GLPCI_CAPSUP_ARI_EN_S 4
5924 #define GLPCI_CAPSUP_ARI_EN_M BIT(4)
5925 #define GLPCI_CAPSUP_IOV_EN_S 5
5926 #define GLPCI_CAPSUP_IOV_EN_M BIT(5)
5927 #define GLPCI_CAPSUP_ACS_EN_S 6
5928 #define GLPCI_CAPSUP_ACS_EN_M BIT(6)
5929 #define GLPCI_CAPSUP_SEC_EN_S 7
5930 #define GLPCI_CAPSUP_SEC_EN_M BIT(7)
5931 #define GLPCI_CAPSUP_PASID_EN_S 8
5932 #define GLPCI_CAPSUP_PASID_EN_M BIT(8)
5933 #define GLPCI_CAPSUP_DLFE_EN_S 9
5934 #define GLPCI_CAPSUP_DLFE_EN_M BIT(9)
5935 #define GLPCI_CAPSUP_GEN4_EXT_EN_S 10
5936 #define GLPCI_CAPSUP_GEN4_EXT_EN_M BIT(10)
5937 #define GLPCI_CAPSUP_GEN4_MARG_EN_S 11
5938 #define GLPCI_CAPSUP_GEN4_MARG_EN_M BIT(11)
5939 #define GLPCI_CAPSUP_ECRC_GEN_EN_S 16
5940 #define GLPCI_CAPSUP_ECRC_GEN_EN_M BIT(16)
5941 #define GLPCI_CAPSUP_ECRC_CHK_EN_S 17
5942 #define GLPCI_CAPSUP_ECRC_CHK_EN_M BIT(17)
5943 #define GLPCI_CAPSUP_IDO_EN_S 18
5944 #define GLPCI_CAPSUP_IDO_EN_M BIT(18)
5945 #define GLPCI_CAPSUP_MSI_MASK_S 19
5946 #define GLPCI_CAPSUP_MSI_MASK_M BIT(19)
5947 #define GLPCI_CAPSUP_CSR_CONF_EN_S 20
5948 #define GLPCI_CAPSUP_CSR_CONF_EN_M BIT(20)
5949 #define GLPCI_CAPSUP_WAKUP_EN_S 21
5950 #define GLPCI_CAPSUP_WAKUP_EN_M BIT(21)
5951 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_S 30
5952 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_M BIT(30)
5953 #define GLPCI_CAPSUP_LOAD_DEV_ID_S 31
5954 #define GLPCI_CAPSUP_LOAD_DEV_ID_M BIT(31)
5955 #define GLPCI_CNF 0x0009DEA0 /* Reset Source: POR */
5956 #define GLPCI_CNF_FLEX10_S 1
5957 #define GLPCI_CNF_FLEX10_M BIT(1)
5958 #define GLPCI_CNF_WAKE_PIN_EN_S 2
5959 #define GLPCI_CNF_WAKE_PIN_EN_M BIT(2)
5960 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_S 3
5961 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_M BIT(3)
5962 #define GLPCI_CNF2 0x000BE004 /* Reset Source: PCIR */
5963 #define GLPCI_CNF2_RO_DIS_S 0
5964 #define GLPCI_CNF2_RO_DIS_M BIT(0)
5965 #define GLPCI_CNF2_CACHELINE_SIZE_S 1
5966 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
5967 #define GLPCI_DREVID 0x0009E9AC /* Reset Source: PCIR */
5968 #define GLPCI_DREVID_DEFAULT_REVID_S 0
5969 #define GLPCI_DREVID_DEFAULT_REVID_M MAKEMASK(0xFF, 0)
5970 #define GLPCI_GSCL_1_NP_C 0x000BFDA4 /* Reset Source: PCIR */
5971 #define GLPCI_GSCL_1_NP_C_RT_MODE_S 8
5972 #define GLPCI_GSCL_1_NP_C_RT_MODE_M BIT(8)
5973 #define GLPCI_GSCL_1_NP_C_RT_EVENT_S 9
5974 #define GLPCI_GSCL_1_NP_C_RT_EVENT_M MAKEMASK(0x1F, 9)
5975 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_S 14
5976 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_M BIT(14)
5977 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_S 15
5978 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_M MAKEMASK(0x1F, 15)
5979 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_S 29
5980 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_M BIT(29)
5981 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_S 30
5982 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_M BIT(30)
5983 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_S 31
5984 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_M BIT(31)
5985 #define GLPCI_GSCL_1_P 0x0009E9B4 /* Reset Source: PCIR */
5986 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_S 0
5987 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M BIT(0)
5988 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_S 1
5989 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_M BIT(1)
5990 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_S 2
5991 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_M BIT(2)
5992 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_S 3
5993 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_M BIT(3)
5994 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_S 4
5995 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_M BIT(4)
5996 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_S 5
5997 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_M BIT(5)
5998 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_S 6
5999 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_M BIT(6)
6000 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_S 7
6001 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_M BIT(7)
6002 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_S 14
6003 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_M BIT(14)
6004 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_S 28
6005 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_M BIT(28)
6006 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_S 29
6007 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_M BIT(29)
6008 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_S 30
6009 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_M BIT(30)
6010 #define GLPCI_GSCL_1_P_GIO_COUNT_START_S 31
6011 #define GLPCI_GSCL_1_P_GIO_COUNT_START_M BIT(31)
6012 #define GLPCI_GSCL_2 0x0009E998 /* Reset Source: PCIR */
6013 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_S 0
6014 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_M MAKEMASK(0xFF, 0)
6015 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_S 8
6016 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_M MAKEMASK(0xFF, 8)
6017 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_S 16
6018 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_M MAKEMASK(0xFF, 16)
6019 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_S 24
6020 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_M MAKEMASK(0xFF, 24)
6021 #define GLPCI_GSCL_5_8(_i) (0x0009E954 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
6022 #define GLPCI_GSCL_5_8_MAX_INDEX 3
6023 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_S 0
6024 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_M MAKEMASK(0xFFFF, 0)
6025 #define GLPCI_GSCL_5_8_LBC_TIMER_N_S 16
6026 #define GLPCI_GSCL_5_8_LBC_TIMER_N_M MAKEMASK(0xFFFF, 16)
6027 #define GLPCI_GSCN_0_3(_i) (0x0009E99C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
6028 #define GLPCI_GSCN_0_3_MAX_INDEX 3
6029 #define GLPCI_GSCN_0_3_EVENT_COUNTER_S 0
6030 #define GLPCI_GSCN_0_3_EVENT_COUNTER_M MAKEMASK(0xFFFFFFFF, 0)
6031 #define GLPCI_LATCT_NP_C 0x000BFDA0 /* Reset Source: PCIR */
6032 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_S 0
6033 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_M MAKEMASK(0xFFFFFFFF, 0)
6034 #define GLPCI_LBARCTRL 0x0009DE74 /* Reset Source: POR */
6035 #define GLPCI_LBARCTRL_PREFBAR_S 0
6036 #define GLPCI_LBARCTRL_PREFBAR_M BIT(0)
6037 #define GLPCI_LBARCTRL_BAR32_S 1
6038 #define GLPCI_LBARCTRL_BAR32_M BIT(1)
6039 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_S 2
6040 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_M BIT(2)
6041 #define GLPCI_LBARCTRL_FLASH_EXPOSE_S 3
6042 #define GLPCI_LBARCTRL_FLASH_EXPOSE_M BIT(3)
6043 #define GLPCI_LBARCTRL_PE_DB_SIZE_S 4
6044 #define GLPCI_LBARCTRL_PE_DB_SIZE_M MAKEMASK(0x3, 4)
6045 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_S 9
6046 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_M BIT(9)
6047 #define GLPCI_LBARCTRL_EXROM_SIZE_S 11
6048 #define GLPCI_LBARCTRL_EXROM_SIZE_M MAKEMASK(0x7, 11)
6049 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_S 14
6050 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_M MAKEMASK(0x3, 14)
6051 #define GLPCI_LINKCAP 0x0009DE90 /* Reset Source: PCIR */
6052 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_S 0
6053 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_M MAKEMASK(0x3F, 0)
6054 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_S 9
6055 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_M MAKEMASK(0xF, 9)
6056 #define GLPCI_NPQ_CFG 0x000BFD80 /* Reset Source: PCIR */
6057 #define GLPCI_NPQ_CFG_EXTEND_TO_S 0
6058 #define GLPCI_NPQ_CFG_EXTEND_TO_M BIT(0)
6059 #define GLPCI_NPQ_CFG_SMALL_TO_S 1
6060 #define GLPCI_NPQ_CFG_SMALL_TO_M BIT(1)
6061 #define GLPCI_NPQ_CFG_WEIGHT_AVG_S 2
6062 #define GLPCI_NPQ_CFG_WEIGHT_AVG_M MAKEMASK(0xF, 2)
6063 #define GLPCI_NPQ_CFG_NPQ_SPARE_S 6
6064 #define GLPCI_NPQ_CFG_NPQ_SPARE_M MAKEMASK(0x3FF, 6)
6065 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_S 16
6066 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_M MAKEMASK(0xF, 16)
6067 #define GLPCI_PKTCT_NP_C 0x000BFD9C /* Reset Source: PCIR */
6068 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_S 0
6069 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6070 #define GLPCI_PKTCT_P 0x0009E9B0 /* Reset Source: PCIR */
6071 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_S 0
6072 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6073 #define GLPCI_PMSUP 0x0009DE94 /* Reset Source: PCIR */
6074 #define GLPCI_PMSUP_RESERVED_0_S 0
6075 #define GLPCI_PMSUP_RESERVED_0_M MAKEMASK(0x3, 0)
6076 #define GLPCI_PMSUP_RESERVED_1_S 2
6077 #define GLPCI_PMSUP_RESERVED_1_M MAKEMASK(0x7, 2)
6078 #define GLPCI_PMSUP_RESERVED_2_S 5
6079 #define GLPCI_PMSUP_RESERVED_2_M MAKEMASK(0x7, 5)
6080 #define GLPCI_PMSUP_L0S_ACC_LAT_S 8
6081 #define GLPCI_PMSUP_L0S_ACC_LAT_M MAKEMASK(0x7, 8)
6082 #define GLPCI_PMSUP_L1_ACC_LAT_S 11
6083 #define GLPCI_PMSUP_L1_ACC_LAT_M MAKEMASK(0x7, 11)
6084 #define GLPCI_PMSUP_RESERVED_3_S 14
6085 #define GLPCI_PMSUP_RESERVED_3_M BIT(14)
6086 #define GLPCI_PMSUP_OBFF_SUP_S 15
6087 #define GLPCI_PMSUP_OBFF_SUP_M MAKEMASK(0x3, 15)
6088 #define GLPCI_PUSH_PE_IF_TO_STATUS 0x0009DF44 /* Reset Source: PCIR */
6089 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_S 0
6090 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0)
6091 #define GLPCI_PWRDATA 0x0009DE7C /* Reset Source: PCIR */
6092 #define GLPCI_PWRDATA_D0_POWER_S 0
6093 #define GLPCI_PWRDATA_D0_POWER_M MAKEMASK(0xFF, 0)
6094 #define GLPCI_PWRDATA_COMM_POWER_S 8
6095 #define GLPCI_PWRDATA_COMM_POWER_M MAKEMASK(0xFF, 8)
6096 #define GLPCI_PWRDATA_D3_POWER_S 16
6097 #define GLPCI_PWRDATA_D3_POWER_M MAKEMASK(0xFF, 16)
6098 #define GLPCI_PWRDATA_DATA_SCALE_S 24
6099 #define GLPCI_PWRDATA_DATA_SCALE_M MAKEMASK(0x3, 24)
6100 #define GLPCI_REVID 0x0009DE98 /* Reset Source: PCIR */
6101 #define GLPCI_REVID_NVM_REVID_S 0
6102 #define GLPCI_REVID_NVM_REVID_M MAKEMASK(0xFF, 0)
6103 #define GLPCI_SERH 0x0009DE84 /* Reset Source: PCIR */
6104 #define GLPCI_SERH_SER_NUM_H_S 0
6105 #define GLPCI_SERH_SER_NUM_H_M MAKEMASK(0xFFFF, 0)
6106 #define GLPCI_SERL 0x0009DE80 /* Reset Source: PCIR */
6107 #define GLPCI_SERL_SER_NUM_L_S 0
6108 #define GLPCI_SERL_SER_NUM_L_M MAKEMASK(0xFFFFFFFF, 0)
6109 #define GLPCI_SUBVENID 0x0009DEE8 /* Reset Source: PCIR */
6110 #define GLPCI_SUBVENID_SUB_VEN_ID_S 0
6111 #define GLPCI_SUBVENID_SUB_VEN_ID_M MAKEMASK(0xFFFF, 0)
6112 #define GLPCI_UPADD 0x000BE0D4 /* Reset Source: PCIR */
6113 #define GLPCI_UPADD_ADDRESS_S 1
6114 #define GLPCI_UPADD_ADDRESS_M MAKEMASK(0x7FFFFFFF, 1)
6115 #define GLPCI_VENDORID 0x0009DEC8 /* Reset Source: PCIR */
6116 #define GLPCI_VENDORID_VENDORID_S 0
6117 #define GLPCI_VENDORID_VENDORID_M MAKEMASK(0xFFFF, 0)
6118 #define GLPCI_VFSUP 0x0009DE9C /* Reset Source: PCIR */
6119 #define GLPCI_VFSUP_VF_PREFETCH_S 0
6120 #define GLPCI_VFSUP_VF_PREFETCH_M BIT(0)
6121 #define GLPCI_VFSUP_VR_BAR_TYPE_S 1
6122 #define GLPCI_VFSUP_VR_BAR_TYPE_M BIT(1)
6123 #define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90 /* Reset Source: PCIR */
6124 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_S 0
6125 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_M MAKEMASK(0xFFFF, 0)
6126 #define PF_FUNC_RID 0x0009E880 /* Reset Source: PCIR */
6127 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0
6128 #define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, 0)
6129 #define PF_FUNC_RID_DEVICE_NUMBER_S 3
6130 #define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, 3)
6131 #define PF_FUNC_RID_BUS_NUMBER_S 8
6132 #define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, 8)
6133 #define PF_PCI_CIAA 0x0009E580 /* Reset Source: FLR */
6134 #define PF_PCI_CIAA_ADDRESS_S 0
6135 #define PF_PCI_CIAA_ADDRESS_M MAKEMASK(0xFFF, 0)
6136 #define PF_PCI_CIAA_VF_NUM_S 12
6137 #define PF_PCI_CIAA_VF_NUM_M MAKEMASK(0xFF, 12)
6138 #define PF_PCI_CIAD 0x0009E500 /* Reset Source: FLR */
6139 #define PF_PCI_CIAD_DATA_S 0
6140 #define PF_PCI_CIAD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
6141 #define PFPCI_CLASS 0x0009DB00 /* Reset Source: PCIR */
6142 #define PFPCI_CLASS_STORAGE_CLASS_S 0
6143 #define PFPCI_CLASS_STORAGE_CLASS_M BIT(0)
6144 #define PFPCI_CLASS_PF_IS_LAN_S 2
6145 #define PFPCI_CLASS_PF_IS_LAN_M BIT(2)
6146 #define PFPCI_CNF 0x0009DF00 /* Reset Source: PCIR */
6147 #define PFPCI_CNF_MSI_EN_S 2
6148 #define PFPCI_CNF_MSI_EN_M BIT(2)
6149 #define PFPCI_CNF_EXROM_DIS_S 3
6150 #define PFPCI_CNF_EXROM_DIS_M BIT(3)
6151 #define PFPCI_CNF_IO_BAR_S 4
6152 #define PFPCI_CNF_IO_BAR_M BIT(4)
6153 #define PFPCI_CNF_INT_PIN_S 5
6154 #define PFPCI_CNF_INT_PIN_M MAKEMASK(0x3, 5)
6155 #define PFPCI_DEVID 0x0009DE00 /* Reset Source: PCIR */
6156 #define PFPCI_DEVID_PF_DEV_ID_S 0
6157 #define PFPCI_DEVID_PF_DEV_ID_M MAKEMASK(0xFFFF, 0)
6158 #define PFPCI_DEVID_VF_DEV_ID_S 16
6159 #define PFPCI_DEVID_VF_DEV_ID_M MAKEMASK(0xFFFF, 16)
6160 #define PFPCI_FACTPS 0x0009E900 /* Reset Source: FLR */
6161 #define PFPCI_FACTPS_FUNC_POWER_STATE_S 0
6162 #define PFPCI_FACTPS_FUNC_POWER_STATE_M MAKEMASK(0x3, 0)
6163 #define PFPCI_FACTPS_FUNC_AUX_EN_S 3
6164 #define PFPCI_FACTPS_FUNC_AUX_EN_M BIT(3)
6165 #define PFPCI_FUNC 0x0009D980 /* Reset Source: POR */
6166 #define PFPCI_FUNC_FUNC_DIS_S 0
6167 #define PFPCI_FUNC_FUNC_DIS_M BIT(0)
6168 #define PFPCI_FUNC_ALLOW_FUNC_DIS_S 1
6169 #define PFPCI_FUNC_ALLOW_FUNC_DIS_M BIT(1)
6170 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_S 2
6171 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_M BIT(2)
6172 #define PFPCI_PF_FLUSH_DONE 0x0009E400 /* Reset Source: PCIR */
6173 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_S 0
6174 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6175 #define PFPCI_PM 0x0009DA80 /* Reset Source: POR */
6176 #define PFPCI_PM_PME_EN_S 0
6177 #define PFPCI_PM_PME_EN_M BIT(0)
6178 #define PFPCI_STATUS1 0x0009DA00 /* Reset Source: POR */
6179 #define PFPCI_STATUS1_FUNC_VALID_S 0
6180 #define PFPCI_STATUS1_FUNC_VALID_M BIT(0)
6181 #define PFPCI_SUBSYSID 0x0009D880 /* Reset Source: PCIR */
6182 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_S 0
6183 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_M MAKEMASK(0xFFFF, 0)
6184 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_S 16
6185 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_M MAKEMASK(0xFFFF, 16)
6186 #define PFPCI_VF_FLUSH_DONE(_VF) (0x0009E000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
6187 #define PFPCI_VF_FLUSH_DONE_MAX_INDEX 255
6188 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_S 0
6189 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6190 #define PFPCI_VM_FLUSH_DONE 0x0009E480 /* Reset Source: PCIR */
6191 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_S 0
6192 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6193 #define PFPCI_VMINDEX 0x0009E600 /* Reset Source: PCIR */
6194 #define PFPCI_VMINDEX_VMINDEX_S 0
6195 #define PFPCI_VMINDEX_VMINDEX_M MAKEMASK(0x3FF, 0)
6196 #define PFPCI_VMPEND 0x0009E800 /* Reset Source: PCIR */
6197 #define PFPCI_VMPEND_PENDING_S 0
6198 #define PFPCI_VMPEND_PENDING_M BIT(0)
6199 #define PQ_FIFO_STATUS 0x0009DF40 /* Reset Source: PCIR */
6200 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_S 0
6201 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_M MAKEMASK(0x7FFFFFFF, 0)
6202 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_S 31
6203 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_M BIT(31)
6204 #define GLPE_CPUSTATUS0 0x0050BA5C /* Reset Source: CORER */
6205 #define GLPE_CPUSTATUS0_PECPUSTATUS0_S 0
6206 #define GLPE_CPUSTATUS0_PECPUSTATUS0_M MAKEMASK(0xFFFFFFFF, 0)
6207 #define GLPE_CPUSTATUS1 0x0050BA60 /* Reset Source: CORER */
6208 #define GLPE_CPUSTATUS1_PECPUSTATUS1_S 0
6209 #define GLPE_CPUSTATUS1_PECPUSTATUS1_M MAKEMASK(0xFFFFFFFF, 0)
6210 #define GLPE_CPUSTATUS2 0x0050BA64 /* Reset Source: CORER */
6211 #define GLPE_CPUSTATUS2_PECPUSTATUS2_S 0
6212 #define GLPE_CPUSTATUS2_PECPUSTATUS2_M MAKEMASK(0xFFFFFFFF, 0)
6213 #define GLPE_MDQ_BASE(_i) (0x00536000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6214 #define GLPE_MDQ_BASE_MAX_INDEX 511
6215 #define GLPE_MDQ_BASE_MDOC_INDEX_S 0
6216 #define GLPE_MDQ_BASE_MDOC_INDEX_M MAKEMASK(0xFFFFFFF, 0)
6217 #define GLPE_MDQ_PTR(_i) (0x00537000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6218 #define GLPE_MDQ_PTR_MAX_INDEX 511
6219 #define GLPE_MDQ_PTR_MDQ_HEAD_S 0
6220 #define GLPE_MDQ_PTR_MDQ_HEAD_M MAKEMASK(0x3FFF, 0)
6221 #define GLPE_MDQ_PTR_MDQ_TAIL_S 16
6222 #define GLPE_MDQ_PTR_MDQ_TAIL_M MAKEMASK(0x3FFF, 16)
6223 #define GLPE_MDQ_SIZE(_i) (0x00536800 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6224 #define GLPE_MDQ_SIZE_MAX_INDEX 511
6225 #define GLPE_MDQ_SIZE_MDQ_SIZE_S 0
6226 #define GLPE_MDQ_SIZE_MDQ_SIZE_M MAKEMASK(0x3FFF, 0)
6227 #define GLPE_PEPM_CTRL 0x0050C000 /* Reset Source: PERST */
6228 #define GLPE_PEPM_CTRL_PEPM_ENABLE_S 0
6229 #define GLPE_PEPM_CTRL_PEPM_ENABLE_M BIT(0)
6230 #define GLPE_PEPM_CTRL_PEPM_HALT_S 8
6231 #define GLPE_PEPM_CTRL_PEPM_HALT_M BIT(8)
6232 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S 16
6233 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M MAKEMASK(0xFF, 16)
6234 #define GLPE_PEPM_DEALLOC 0x0050C004 /* Reset Source: PERST */
6235 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_S 0
6236 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_M MAKEMASK(0x3FFF, 0)
6237 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_S 14
6238 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_M MAKEMASK(0x1F, 14)
6239 #define GLPE_PEPM_DEALLOC_PQID_S 19
6240 #define GLPE_PEPM_DEALLOC_PQID_M MAKEMASK(0x1FF, 19)
6241 #define GLPE_PEPM_DEALLOC_PORT_S 28
6242 #define GLPE_PEPM_DEALLOC_PORT_M MAKEMASK(0x7, 28)
6243 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_S 31
6244 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_M BIT(31)
6245 #define GLPE_PEPM_PSQ_COUNT 0x0050C020 /* Reset Source: PERST */
6246 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_S 0
6247 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0xFFFF, 0)
6248 #define GLPE_PEPM_THRESH(_i) (0x0050C840 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6249 #define GLPE_PEPM_THRESH_MAX_INDEX 511
6250 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_S 0
6251 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_M MAKEMASK(0x1F, 0)
6252 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_S 16
6253 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_M MAKEMASK(0x3FFF, 16)
6254 #define GLPE_PFAEQEDROPCNT(_i) (0x00503240 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6255 #define GLPE_PFAEQEDROPCNT_MAX_INDEX 7
6256 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_S 0
6257 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6258 #define GLPE_PFCEQEDROPCNT(_i) (0x00503220 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6259 #define GLPE_PFCEQEDROPCNT_MAX_INDEX 7
6260 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_S 0
6261 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6262 #define GLPE_PFCQEDROPCNT(_i) (0x00503200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6263 #define GLPE_PFCQEDROPCNT_MAX_INDEX 7
6264 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_S 0
6265 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6266 #define GLPE_PFFLMOOISCALLOCERR(_i) (0x0050B960 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6267 #define GLPE_PFFLMOOISCALLOCERR_MAX_INDEX 7
6268 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6269 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6270 #define GLPE_PFFLMQ1ALLOCERR(_i) (0x0050B920 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6271 #define GLPE_PFFLMQ1ALLOCERR_MAX_INDEX 7
6272 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6273 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6274 #define GLPE_PFFLMRRFALLOCERR(_i) (0x0050B940 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6275 #define GLPE_PFFLMRRFALLOCERR_MAX_INDEX 7
6276 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_S 0
6277 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6278 #define GLPE_PFFLMXMITALLOCERR(_i) (0x0050B900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6279 #define GLPE_PFFLMXMITALLOCERR_MAX_INDEX 7
6280 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_S 0
6281 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6282 #define GLPE_PFTCPNOW50USCNT(_i) (0x0050B8C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6283 #define GLPE_PFTCPNOW50USCNT_MAX_INDEX 7
6284 #define GLPE_PFTCPNOW50USCNT_CNT_S 0
6285 #define GLPE_PFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6286 #define GLPE_PUSH_PEPM 0x0053241C /* Reset Source: CORER */
6287 #define GLPE_PUSH_PEPM_MDQ_CREDITS_S 0
6288 #define GLPE_PUSH_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
6289 #define GLPE_VFAEQEDROPCNT(_i) (0x00503100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6290 #define GLPE_VFAEQEDROPCNT_MAX_INDEX 31
6291 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_S 0
6292 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6293 #define GLPE_VFCEQEDROPCNT(_i) (0x00503080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6294 #define GLPE_VFCEQEDROPCNT_MAX_INDEX 31
6295 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_S 0
6296 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6297 #define GLPE_VFCQEDROPCNT(_i) (0x00503000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6298 #define GLPE_VFCQEDROPCNT_MAX_INDEX 31
6299 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_S 0
6300 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6301 #define GLPE_VFFLMOOISCALLOCERR(_i) (0x0050B580 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6302 #define GLPE_VFFLMOOISCALLOCERR_MAX_INDEX 31
6303 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6304 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6305 #define GLPE_VFFLMQ1ALLOCERR(_i) (0x0050B480 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6306 #define GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
6307 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6308 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6309 #define GLPE_VFFLMRRFALLOCERR(_i) (0x0050B500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6310 #define GLPE_VFFLMRRFALLOCERR_MAX_INDEX 31
6311 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_S 0
6312 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6313 #define GLPE_VFFLMXMITALLOCERR(_i) (0x0050B400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6314 #define GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
6315 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_S 0
6316 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6317 #define GLPE_VFTCPNOW50USCNT(_i) (0x0050B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: PE_CORER */
6318 #define GLPE_VFTCPNOW50USCNT_MAX_INDEX 31
6319 #define GLPE_VFTCPNOW50USCNT_CNT_S 0
6320 #define GLPE_VFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6321 #define PFPE_AEQALLOC 0x00502D00 /* Reset Source: PFR */
6322 #define PFPE_AEQALLOC_AECOUNT_S 0
6323 #define PFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6324 #define PFPE_CCQPHIGH 0x0050A100 /* Reset Source: PFR */
6325 #define PFPE_CCQPHIGH_PECCQPHIGH_S 0
6326 #define PFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6327 #define PFPE_CCQPLOW 0x0050A080 /* Reset Source: PFR */
6328 #define PFPE_CCQPLOW_PECCQPLOW_S 0
6329 #define PFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6330 #define PFPE_CCQPSTATUS 0x0050A000 /* Reset Source: PFR */
6331 #define PFPE_CCQPSTATUS_CCQP_DONE_S 0
6332 #define PFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6333 #define PFPE_CCQPSTATUS_HMC_PROFILE_S 4
6334 #define PFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6335 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_S 16
6336 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6337 #define PFPE_CCQPSTATUS_CCQP_ERR_S 31
6338 #define PFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
6339 #define PFPE_CQACK 0x00502C80 /* Reset Source: PFR */
6340 #define PFPE_CQACK_PECQID_S 0
6341 #define PFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6342 #define PFPE_CQARM 0x00502C00 /* Reset Source: PFR */
6343 #define PFPE_CQARM_PECQID_S 0
6344 #define PFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6345 #define PFPE_CQPDB 0x00500800 /* Reset Source: PFR */
6346 #define PFPE_CQPDB_WQHEAD_S 0
6347 #define PFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6348 #define PFPE_CQPERRCODES 0x0050A200 /* Reset Source: PFR */
6349 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6350 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6351 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16
6352 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6353 #define PFPE_CQPTAIL 0x00500880 /* Reset Source: PFR */
6354 #define PFPE_CQPTAIL_WQTAIL_S 0
6355 #define PFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6356 #define PFPE_CQPTAIL_CQP_OP_ERR_S 31
6357 #define PFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
6358 #define PFPE_IPCONFIG0 0x0050A180 /* Reset Source: PFR */
6359 #define PFPE_IPCONFIG0_PEIPID_S 0
6360 #define PFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6361 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_S 16
6362 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
6363 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17
6364 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
6365 #define PFPE_MRTEIDXMASK 0x0050A300 /* Reset Source: PFR */
6366 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
6367 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
6368 #define PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */
6369 #define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6370 #define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6371 #define PFPE_TCPNOWTIMER 0x0050A280 /* Reset Source: PFR */
6372 #define PFPE_TCPNOWTIMER_TCP_NOW_S 0
6373 #define PFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6374 #define PFPE_WQEALLOC 0x00504400 /* Reset Source: PFR */
6375 #define PFPE_WQEALLOC_PEQPID_S 0
6376 #define PFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6377 #define PFPE_WQEALLOC_WQE_DESC_INDEX_S 20
6378 #define PFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6379 #define PRT_PEPM_COUNT(_i) (0x0050C040 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6380 #define PRT_PEPM_COUNT_MAX_INDEX 511
6381 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_S 0
6382 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0x1F, 0)
6383 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_S 16
6384 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_M MAKEMASK(0x3FFF, 16)
6385 #define VFPE_AEQALLOC(_VF) (0x00502800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6386 #define VFPE_AEQALLOC_MAX_INDEX 255
6387 #define VFPE_AEQALLOC_AECOUNT_S 0
6388 #define VFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6389 #define VFPE_CCQPHIGH(_VF) (0x00508800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6390 #define VFPE_CCQPHIGH_MAX_INDEX 255
6391 #define VFPE_CCQPHIGH_PECCQPHIGH_S 0
6392 #define VFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6393 #define VFPE_CCQPLOW(_VF) (0x00508400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6394 #define VFPE_CCQPLOW_MAX_INDEX 255
6395 #define VFPE_CCQPLOW_PECCQPLOW_S 0
6396 #define VFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6397 #define VFPE_CCQPSTATUS(_VF) (0x00508000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6398 #define VFPE_CCQPSTATUS_MAX_INDEX 255
6399 #define VFPE_CCQPSTATUS_CCQP_DONE_S 0
6400 #define VFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6401 #define VFPE_CCQPSTATUS_HMC_PROFILE_S 4
6402 #define VFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6403 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_S 16
6404 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6405 #define VFPE_CCQPSTATUS_CCQP_ERR_S 31
6406 #define VFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
6407 #define VFPE_CQACK(_VF) (0x00502400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6408 #define VFPE_CQACK_MAX_INDEX 255
6409 #define VFPE_CQACK_PECQID_S 0
6410 #define VFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6411 #define VFPE_CQARM(_VF) (0x00502000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6412 #define VFPE_CQARM_MAX_INDEX 255
6413 #define VFPE_CQARM_PECQID_S 0
6414 #define VFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6415 #define VFPE_CQPDB(_VF) (0x00500000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6416 #define VFPE_CQPDB_MAX_INDEX 255
6417 #define VFPE_CQPDB_WQHEAD_S 0
6418 #define VFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6419 #define VFPE_CQPERRCODES(_VF) (0x00509000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6420 #define VFPE_CQPERRCODES_MAX_INDEX 255
6421 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6422 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6423 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16
6424 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6425 #define VFPE_CQPTAIL(_VF) (0x00500400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6426 #define VFPE_CQPTAIL_MAX_INDEX 255
6427 #define VFPE_CQPTAIL_WQTAIL_S 0
6428 #define VFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6429 #define VFPE_CQPTAIL_CQP_OP_ERR_S 31
6430 #define VFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
6431 #define VFPE_IPCONFIG0(_VF) (0x00508C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6432 #define VFPE_IPCONFIG0_MAX_INDEX 255
6433 #define VFPE_IPCONFIG0_PEIPID_S 0
6434 #define VFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6435 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_S 16
6436 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
6437 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17
6438 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
6439 #define VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6440 #define VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 255
6441 #define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6442 #define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6443 #define VFPE_TCPNOWTIMER(_VF) (0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6444 #define VFPE_TCPNOWTIMER_MAX_INDEX 255
6445 #define VFPE_TCPNOWTIMER_TCP_NOW_S 0
6446 #define VFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6447 #define VFPE_WQEALLOC(_VF) (0x00504000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6448 #define VFPE_WQEALLOC_MAX_INDEX 255
6449 #define VFPE_WQEALLOC_PEQPID_S 0
6450 #define VFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6451 #define VFPE_WQEALLOC_WQE_DESC_INDEX_S 20
6452 #define VFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6453 #define GLPES_PFIP4RXDISCARD(_i) (0x00541400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6454 #define GLPES_PFIP4RXDISCARD_MAX_INDEX 127
6455 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_S 0
6456 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6457 #define GLPES_PFIP4RXFRAGSHI(_i) (0x00541C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6458 #define GLPES_PFIP4RXFRAGSHI_MAX_INDEX 127
6459 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S 0
6460 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6461 #define GLPES_PFIP4RXFRAGSLO(_i) (0x00541C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6462 #define GLPES_PFIP4RXFRAGSLO_MAX_INDEX 127
6463 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S 0
6464 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6465 #define GLPES_PFIP4RXMCOCTSHI(_i) (0x00542404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6466 #define GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 127
6467 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S 0
6468 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6469 #define GLPES_PFIP4RXMCOCTSLO(_i) (0x00542400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6470 #define GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 127
6471 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S 0
6472 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6473 #define GLPES_PFIP4RXMCPKTSHI(_i) (0x00542C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6474 #define GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 127
6475 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S 0
6476 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6477 #define GLPES_PFIP4RXMCPKTSLO(_i) (0x00542C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6478 #define GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 127
6479 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S 0
6480 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6481 #define GLPES_PFIP4RXOCTSHI(_i) (0x00540404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6482 #define GLPES_PFIP4RXOCTSHI_MAX_INDEX 127
6483 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S 0
6484 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6485 #define GLPES_PFIP4RXOCTSLO(_i) (0x00540400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6486 #define GLPES_PFIP4RXOCTSLO_MAX_INDEX 127
6487 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S 0
6488 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6489 #define GLPES_PFIP4RXPKTSHI(_i) (0x00540C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6490 #define GLPES_PFIP4RXPKTSHI_MAX_INDEX 127
6491 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S 0
6492 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6493 #define GLPES_PFIP4RXPKTSLO(_i) (0x00540C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6494 #define GLPES_PFIP4RXPKTSLO_MAX_INDEX 127
6495 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S 0
6496 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6497 #define GLPES_PFIP4RXTRUNC(_i) (0x00541800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6498 #define GLPES_PFIP4RXTRUNC_MAX_INDEX 127
6499 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_S 0
6500 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6501 #define GLPES_PFIP4TXFRAGSHI(_i) (0x00547404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6502 #define GLPES_PFIP4TXFRAGSHI_MAX_INDEX 127
6503 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S 0
6504 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6505 #define GLPES_PFIP4TXFRAGSLO(_i) (0x00547400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6506 #define GLPES_PFIP4TXFRAGSLO_MAX_INDEX 127
6507 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S 0
6508 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6509 #define GLPES_PFIP4TXMCOCTSHI(_i) (0x00547C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6510 #define GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 127
6511 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S 0
6512 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6513 #define GLPES_PFIP4TXMCOCTSLO(_i) (0x00547C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6514 #define GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 127
6515 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S 0
6516 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6517 #define GLPES_PFIP4TXMCPKTSHI(_i) (0x00548404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6518 #define GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 127
6519 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S 0
6520 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6521 #define GLPES_PFIP4TXMCPKTSLO(_i) (0x00548400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6522 #define GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 127
6523 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S 0
6524 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6525 #define GLPES_PFIP4TXNOROUTE(_i) (0x0054B400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6526 #define GLPES_PFIP4TXNOROUTE_MAX_INDEX 127
6527 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_S 0
6528 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6529 #define GLPES_PFIP4TXOCTSHI(_i) (0x00546404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6530 #define GLPES_PFIP4TXOCTSHI_MAX_INDEX 127
6531 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S 0
6532 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6533 #define GLPES_PFIP4TXOCTSLO(_i) (0x00546400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6534 #define GLPES_PFIP4TXOCTSLO_MAX_INDEX 127
6535 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S 0
6536 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6537 #define GLPES_PFIP4TXPKTSHI(_i) (0x00546C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6538 #define GLPES_PFIP4TXPKTSHI_MAX_INDEX 127
6539 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S 0
6540 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6541 #define GLPES_PFIP4TXPKTSLO(_i) (0x00546C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6542 #define GLPES_PFIP4TXPKTSLO_MAX_INDEX 127
6543 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S 0
6544 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6545 #define GLPES_PFIP6RXDISCARD(_i) (0x00544400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6546 #define GLPES_PFIP6RXDISCARD_MAX_INDEX 127
6547 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_S 0
6548 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6549 #define GLPES_PFIP6RXFRAGSHI(_i) (0x00544C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6550 #define GLPES_PFIP6RXFRAGSHI_MAX_INDEX 127
6551 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S 0
6552 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6553 #define GLPES_PFIP6RXFRAGSLO(_i) (0x00544C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6554 #define GLPES_PFIP6RXFRAGSLO_MAX_INDEX 127
6555 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S 0
6556 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6557 #define GLPES_PFIP6RXMCOCTSHI(_i) (0x00545404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6558 #define GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 127
6559 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S 0
6560 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6561 #define GLPES_PFIP6RXMCOCTSLO(_i) (0x00545400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6562 #define GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 127
6563 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S 0
6564 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6565 #define GLPES_PFIP6RXMCPKTSHI(_i) (0x00545C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6566 #define GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 127
6567 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S 0
6568 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6569 #define GLPES_PFIP6RXMCPKTSLO(_i) (0x00545C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6570 #define GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 127
6571 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S 0
6572 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6573 #define GLPES_PFIP6RXOCTSHI(_i) (0x00543404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6574 #define GLPES_PFIP6RXOCTSHI_MAX_INDEX 127
6575 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S 0
6576 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6577 #define GLPES_PFIP6RXOCTSLO(_i) (0x00543400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6578 #define GLPES_PFIP6RXOCTSLO_MAX_INDEX 127
6579 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S 0
6580 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6581 #define GLPES_PFIP6RXPKTSHI(_i) (0x00543C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6582 #define GLPES_PFIP6RXPKTSHI_MAX_INDEX 127
6583 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S 0
6584 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6585 #define GLPES_PFIP6RXPKTSLO(_i) (0x00543C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6586 #define GLPES_PFIP6RXPKTSLO_MAX_INDEX 127
6587 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S 0
6588 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6589 #define GLPES_PFIP6RXTRUNC(_i) (0x00544800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6590 #define GLPES_PFIP6RXTRUNC_MAX_INDEX 127
6591 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_S 0
6592 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6593 #define GLPES_PFIP6TXFRAGSHI(_i) (0x00549C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6594 #define GLPES_PFIP6TXFRAGSHI_MAX_INDEX 127
6595 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S 0
6596 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6597 #define GLPES_PFIP6TXFRAGSLO(_i) (0x00549C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6598 #define GLPES_PFIP6TXFRAGSLO_MAX_INDEX 127
6599 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S 0
6600 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6601 #define GLPES_PFIP6TXMCOCTSHI(_i) (0x0054A404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6602 #define GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 127
6603 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S 0
6604 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6605 #define GLPES_PFIP6TXMCOCTSLO(_i) (0x0054A400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6606 #define GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 127
6607 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S 0
6608 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6609 #define GLPES_PFIP6TXMCPKTSHI(_i) (0x0054AC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6610 #define GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 127
6611 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S 0
6612 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6613 #define GLPES_PFIP6TXMCPKTSLO(_i) (0x0054AC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6614 #define GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 127
6615 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S 0
6616 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6617 #define GLPES_PFIP6TXNOROUTE(_i) (0x0054B800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6618 #define GLPES_PFIP6TXNOROUTE_MAX_INDEX 127
6619 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_S 0
6620 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6621 #define GLPES_PFIP6TXOCTSHI(_i) (0x00548C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6622 #define GLPES_PFIP6TXOCTSHI_MAX_INDEX 127
6623 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S 0
6624 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6625 #define GLPES_PFIP6TXOCTSLO(_i) (0x00548C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6626 #define GLPES_PFIP6TXOCTSLO_MAX_INDEX 127
6627 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S 0
6628 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6629 #define GLPES_PFIP6TXPKTSHI(_i) (0x00549404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6630 #define GLPES_PFIP6TXPKTSHI_MAX_INDEX 127
6631 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S 0
6632 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6633 #define GLPES_PFIP6TXPKTSLO(_i) (0x00549400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6634 #define GLPES_PFIP6TXPKTSLO_MAX_INDEX 127
6635 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S 0
6636 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6637 #define GLPES_PFRDMARXRDSHI(_i) (0x0054EC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6638 #define GLPES_PFRDMARXRDSHI_MAX_INDEX 127
6639 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S 0
6640 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6641 #define GLPES_PFRDMARXRDSLO(_i) (0x0054EC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6642 #define GLPES_PFRDMARXRDSLO_MAX_INDEX 127
6643 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S 0
6644 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6645 #define GLPES_PFRDMARXSNDSHI(_i) (0x0054F404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6646 #define GLPES_PFRDMARXSNDSHI_MAX_INDEX 127
6647 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S 0
6648 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6649 #define GLPES_PFRDMARXSNDSLO(_i) (0x0054F400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6650 #define GLPES_PFRDMARXSNDSLO_MAX_INDEX 127
6651 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S 0
6652 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6653 #define GLPES_PFRDMARXWRSHI(_i) (0x0054E404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6654 #define GLPES_PFRDMARXWRSHI_MAX_INDEX 127
6655 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S 0
6656 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6657 #define GLPES_PFRDMARXWRSLO(_i) (0x0054E400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6658 #define GLPES_PFRDMARXWRSLO_MAX_INDEX 127
6659 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S 0
6660 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6661 #define GLPES_PFRDMATXRDSHI(_i) (0x00550404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6662 #define GLPES_PFRDMATXRDSHI_MAX_INDEX 127
6663 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S 0
6664 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6665 #define GLPES_PFRDMATXRDSLO(_i) (0x00550400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6666 #define GLPES_PFRDMATXRDSLO_MAX_INDEX 127
6667 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S 0
6668 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6669 #define GLPES_PFRDMATXSNDSHI(_i) (0x00550C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6670 #define GLPES_PFRDMATXSNDSHI_MAX_INDEX 127
6671 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S 0
6672 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6673 #define GLPES_PFRDMATXSNDSLO(_i) (0x00550C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6674 #define GLPES_PFRDMATXSNDSLO_MAX_INDEX 127
6675 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S 0
6676 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6677 #define GLPES_PFRDMATXWRSHI(_i) (0x0054FC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6678 #define GLPES_PFRDMATXWRSHI_MAX_INDEX 127
6679 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S 0
6680 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6681 #define GLPES_PFRDMATXWRSLO(_i) (0x0054FC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6682 #define GLPES_PFRDMATXWRSLO_MAX_INDEX 127
6683 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S 0
6684 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6685 #define GLPES_PFRDMAVBNDHI(_i) (0x00551404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6686 #define GLPES_PFRDMAVBNDHI_MAX_INDEX 127
6687 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S 0
6688 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M MAKEMASK(0xFFFF, 0)
6689 #define GLPES_PFRDMAVBNDLO(_i) (0x00551400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6690 #define GLPES_PFRDMAVBNDLO_MAX_INDEX 127
6691 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S 0
6692 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M MAKEMASK(0xFFFFFFFF, 0)
6693 #define GLPES_PFRDMAVINVHI(_i) (0x00551C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6694 #define GLPES_PFRDMAVINVHI_MAX_INDEX 127
6695 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_S 0
6696 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_M MAKEMASK(0xFFFF, 0)
6697 #define GLPES_PFRDMAVINVLO(_i) (0x00551C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6698 #define GLPES_PFRDMAVINVLO_MAX_INDEX 127
6699 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_S 0
6700 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_M MAKEMASK(0xFFFFFFFF, 0)
6701 #define GLPES_PFRXVLANERR(_i) (0x00540000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6702 #define GLPES_PFRXVLANERR_MAX_INDEX 127
6703 #define GLPES_PFRXVLANERR_RXVLANERR_S 0
6704 #define GLPES_PFRXVLANERR_RXVLANERR_M MAKEMASK(0xFFFFFF, 0)
6705 #define GLPES_PFTCPRTXSEG(_i) (0x00552400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6706 #define GLPES_PFTCPRTXSEG_MAX_INDEX 127
6707 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_S 0
6708 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_M MAKEMASK(0xFFFFFFFF, 0)
6709 #define GLPES_PFTCPRXOPTERR(_i) (0x0054C400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6710 #define GLPES_PFTCPRXOPTERR_MAX_INDEX 127
6711 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_S 0
6712 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_M MAKEMASK(0xFFFFFF, 0)
6713 #define GLPES_PFTCPRXPROTOERR(_i) (0x0054C800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6714 #define GLPES_PFTCPRXPROTOERR_MAX_INDEX 127
6715 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_S 0
6716 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_M MAKEMASK(0xFFFFFF, 0)
6717 #define GLPES_PFTCPRXSEGSHI(_i) (0x0054BC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6718 #define GLPES_PFTCPRXSEGSHI_MAX_INDEX 127
6719 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S 0
6720 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M MAKEMASK(0xFFFF, 0)
6721 #define GLPES_PFTCPRXSEGSLO(_i) (0x0054BC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6722 #define GLPES_PFTCPRXSEGSLO_MAX_INDEX 127
6723 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S 0
6724 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6725 #define GLPES_PFTCPTXSEGHI(_i) (0x0054CC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6726 #define GLPES_PFTCPTXSEGHI_MAX_INDEX 127
6727 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_S 0
6728 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_M MAKEMASK(0xFFFF, 0)
6729 #define GLPES_PFTCPTXSEGLO(_i) (0x0054CC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6730 #define GLPES_PFTCPTXSEGLO_MAX_INDEX 127
6731 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_S 0
6732 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_M MAKEMASK(0xFFFFFFFF, 0)
6733 #define GLPES_PFUDPRXPKTSHI(_i) (0x0054D404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6734 #define GLPES_PFUDPRXPKTSHI_MAX_INDEX 127
6735 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S 0
6736 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M MAKEMASK(0xFFFF, 0)
6737 #define GLPES_PFUDPRXPKTSLO(_i) (0x0054D400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6738 #define GLPES_PFUDPRXPKTSLO_MAX_INDEX 127
6739 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S 0
6740 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6741 #define GLPES_PFUDPTXPKTSHI(_i) (0x0054DC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6742 #define GLPES_PFUDPTXPKTSHI_MAX_INDEX 127
6743 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S 0
6744 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M MAKEMASK(0xFFFF, 0)
6745 #define GLPES_PFUDPTXPKTSLO(_i) (0x0054DC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6746 #define GLPES_PFUDPTXPKTSLO_MAX_INDEX 127
6747 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S 0
6748 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6749 #define GLPES_RDMARXMULTFPDUSHI 0x0055E00C /* Reset Source: CORER */
6750 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0
6751 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M MAKEMASK(0xFFFFFF, 0)
6752 #define GLPES_RDMARXMULTFPDUSLO 0x0055E008 /* Reset Source: CORER */
6753 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0
6754 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M MAKEMASK(0xFFFFFFFF, 0)
6755 #define GLPES_RDMARXOOODDPHI 0x0055E014 /* Reset Source: CORER */
6756 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S 0
6757 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M MAKEMASK(0xFFFFFF, 0)
6758 #define GLPES_RDMARXOOODDPLO 0x0055E010 /* Reset Source: CORER */
6759 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S 0
6760 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0)
6761 #define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */
6762 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0
6763 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0)
6764 #define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */
6765 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0
6766 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)
6767 #define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */
6768 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
6769 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6770 #define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */
6771 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
6772 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6773 #define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */
6774 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0
6775 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6776 #define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */
6777 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0
6778 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6779 #define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */
6780 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0
6781 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_M MAKEMASK(0xFFFFFF, 0)
6782 #define GLPES_TCPRXPUREACKSLO 0x0055E018 /* Reset Source: CORER */
6783 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S 0
6784 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M MAKEMASK(0xFFFFFFFF, 0)
6785 #define GLPES_TCPRXTHREEHOLEHI 0x0055E034 /* Reset Source: CORER */
6786 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0
6787 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6788 #define GLPES_TCPRXTHREEHOLELO 0x0055E030 /* Reset Source: CORER */
6789 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0
6790 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6791 #define GLPES_TCPRXTWOHOLEHI 0x0055E02C /* Reset Source: CORER */
6792 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S 0
6793 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6794 #define GLPES_TCPRXTWOHOLELO 0x0055E028 /* Reset Source: CORER */
6795 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S 0
6796 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6797 #define GLPES_TCPTXRETRANSFASTHI 0x0055E044 /* Reset Source: CORER */
6798 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0
6799 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6800 #define GLPES_TCPTXRETRANSFASTLO 0x0055E040 /* Reset Source: CORER */
6801 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0
6802 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6803 #define GLPES_TCPTXTOUTSFASTHI 0x0055E04C /* Reset Source: CORER */
6804 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0
6805 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6806 #define GLPES_TCPTXTOUTSFASTLO 0x0055E048 /* Reset Source: CORER */
6807 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0
6808 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6809 #define GLPES_TCPTXTOUTSHI 0x0055E054 /* Reset Source: CORER */
6810 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S 0
6811 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M MAKEMASK(0xFFFFFF, 0)
6812 #define GLPES_TCPTXTOUTSLO 0x0055E050 /* Reset Source: CORER */
6813 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S 0
6814 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6815 #define GL_PWR_MODE_CTL 0x000B820C /* Reset Source: POR */
6816 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_S 0
6817 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M BIT(0)
6818 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_S 1
6819 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_M BIT(1)
6820 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_S 2
6821 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_M BIT(2)
6822 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_S 3
6823 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_M MAKEMASK(0x3, 3)
6824 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
6825 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M MAKEMASK(0x3, 30)
6826 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT 0x000B825C /* Reset Source: POR */
6827 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6828 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6829 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6830 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6831 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6832 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6833 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6834 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6835 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6836 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6837 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6838 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6839 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6840 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6841 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT 0x000B8218 /* Reset Source: POR */
6842 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6843 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6844 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6845 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6846 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6847 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6848 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6849 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6850 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6851 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6852 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6853 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6854 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6855 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6856 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT 0x000B8260 /* Reset Source: POR */
6857 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6858 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6859 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6860 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6861 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6862 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6863 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6864 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6865 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6866 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6867 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6868 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6869 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6870 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6871 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK 0x000B8200 /* Reset Source: POR */
6872 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_S 0
6873 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6874 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_S 3
6875 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6876 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_S 6
6877 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6878 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_S 9
6879 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6880 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_S 12
6881 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6882 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK 0x000B81F0 /* Reset Source: POR */
6883 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_S 0
6884 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6885 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_S 3
6886 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6887 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_S 6
6888 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6889 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_S 9
6890 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6891 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_S 12
6892 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6893 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM 0x000B81FC /* Reset Source: POR */
6894 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_S 0
6895 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6896 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_S 3
6897 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6898 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_S 6
6899 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6900 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_S 9
6901 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6902 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_S 12
6903 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6904 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL 0x000B81F8 /* Reset Source: POR */
6905 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_S 0
6906 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6907 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_S 3
6908 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6909 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_S 6
6910 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6911 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_S 9
6912 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6913 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_S 12
6914 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6915 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA 0x000B8208 /* Reset Source: POR */
6916 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_S 0
6917 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6918 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_S 3
6919 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6920 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_S 6
6921 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6922 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_S 9
6923 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6924 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_S 12
6925 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6926 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK 0x000B81F4 /* Reset Source: POR */
6927 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_S 0
6928 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6929 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_S 3
6930 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6931 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_S 6
6932 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6933 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_S 9
6934 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6935 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_S 12
6936 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6937 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK 0x000B8244 /* Reset Source: POR */
6938 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_S 0
6939 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6940 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_S 3
6941 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6942 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_S 6
6943 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6944 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_S 9
6945 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6946 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_S 12
6947 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6948 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK 0x000B8220 /* Reset Source: POR */
6949 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_S 0
6950 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6951 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_S 3
6952 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6953 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_S 6
6954 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6955 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_S 9
6956 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6957 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_S 12
6958 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6959 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM 0x000B8240 /* Reset Source: POR */
6960 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_S 0
6961 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6962 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_S 3
6963 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6964 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_S 6
6965 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6966 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_S 9
6967 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6968 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_S 12
6969 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6970 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL 0x000B823C /* Reset Source: POR */
6971 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_S 0
6972 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6973 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_S 3
6974 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6975 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_S 6
6976 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6977 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_S 9
6978 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6979 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_S 12
6980 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6981 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA 0x000B8248 /* Reset Source: POR */
6982 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_S 0
6983 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6984 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_S 3
6985 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6986 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_S 6
6987 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6988 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_S 9
6989 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6990 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_S 12
6991 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6992 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK 0x000B8238 /* Reset Source: POR */
6993 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_S 0
6994 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6995 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_S 3
6996 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6997 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_S 6
6998 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6999 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_S 9
7000 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7001 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_S 12
7002 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7003 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK 0x000B8230 /* Reset Source: POR */
7004 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_S 0
7005 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7006 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_S 3
7007 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7008 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_S 6
7009 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7010 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_S 9
7011 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7012 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_S 12
7013 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7014 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK 0x000B821C /* Reset Source: POR */
7015 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_S 0
7016 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7017 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_S 3
7018 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7019 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_S 6
7020 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7021 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_S 9
7022 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7023 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_S 12
7024 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7025 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM 0x000B822C /* Reset Source: POR */
7026 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_S 0
7027 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7028 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_S 3
7029 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7030 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_S 6
7031 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7032 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_S 9
7033 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7034 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_S 12
7035 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7036 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL 0x000B8228 /* Reset Source: POR */
7037 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_S 0
7038 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7039 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_S 3
7040 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7041 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_S 6
7042 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7043 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_S 9
7044 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7045 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_S 12
7046 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7047 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA 0x000B8234 /* Reset Source: POR */
7048 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_S 0
7049 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7050 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_S 3
7051 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7052 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_S 6
7053 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7054 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_S 9
7055 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7056 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_S 12
7057 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7058 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK 0x000B8224 /* Reset Source: POR */
7059 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_S 0
7060 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7061 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_S 3
7062 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7063 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_S 6
7064 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7065 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_S 9
7066 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7067 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_S 12
7068 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7069 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL 0x000B81EC /* Reset Source: POR */
7070 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_S 0
7071 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7072 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_S 3
7073 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7074 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_S 6
7075 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7076 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_S 9
7077 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7078 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_S 12
7079 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7080 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL 0x000B824C /* Reset Source: POR */
7081 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_S 0
7082 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7083 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_S 3
7084 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7085 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_S 6
7086 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7087 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_S 9
7088 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7089 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_S 12
7090 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7091 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL 0x000B8250 /* Reset Source: POR */
7092 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_S 0
7093 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7094 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_S 3
7095 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7096 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_S 6
7097 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7098 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_S 9
7099 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7100 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_S 12
7101 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7102 #define GL_S5_PWR_MODE_EXIT_CTL 0x000B8270 /* Reset Source: POR */
7103 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_S 0
7104 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0)
7105 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_S 1
7106 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_M BIT(1)
7107 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_S 3
7108 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_M BIT(3)
7109 #define GLGEN_PME_TO 0x000B81BC /* Reset Source: POR */
7110 #define GLGEN_PME_TO_PME_TO_FOR_PE_S 0
7111 #define GLGEN_PME_TO_PME_TO_FOR_PE_M BIT(0)
7112 #define PRTPM_EEE_STAT 0x001E4320 /* Reset Source: GLOBR */
7113 #define PRTPM_EEE_STAT_EEE_NEG_S 29
7114 #define PRTPM_EEE_STAT_EEE_NEG_M BIT(29)
7115 #define PRTPM_EEE_STAT_RX_LPI_STATUS_S 30
7116 #define PRTPM_EEE_STAT_RX_LPI_STATUS_M BIT(30)
7117 #define PRTPM_EEE_STAT_TX_LPI_STATUS_S 31
7118 #define PRTPM_EEE_STAT_TX_LPI_STATUS_M BIT(31)
7119 #define PRTPM_EEEC 0x001E4380 /* Reset Source: GLOBR */
7120 #define PRTPM_EEEC_TW_WAKE_MIN_S 16
7121 #define PRTPM_EEEC_TW_WAKE_MIN_M MAKEMASK(0x3F, 16)
7122 #define PRTPM_EEEC_TX_LU_LPI_DLY_S 24
7123 #define PRTPM_EEEC_TX_LU_LPI_DLY_M MAKEMASK(0x3, 24)
7124 #define PRTPM_EEEC_TEEE_DLY_S 26
7125 #define PRTPM_EEEC_TEEE_DLY_M MAKEMASK(0x3F, 26)
7126 #define PRTPM_EEEFWD 0x001E4400 /* Reset Source: GLOBR */
7127 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_S 31
7128 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_M BIT(31)
7129 #define PRTPM_EEER 0x001E4360 /* Reset Source: GLOBR */
7130 #define PRTPM_EEER_TW_SYSTEM_S 0
7131 #define PRTPM_EEER_TW_SYSTEM_M MAKEMASK(0xFFFF, 0)
7132 #define PRTPM_EEER_TX_LPI_EN_S 16
7133 #define PRTPM_EEER_TX_LPI_EN_M BIT(16)
7134 #define PRTPM_EEETXC 0x001E43E0 /* Reset Source: GLOBR */
7135 #define PRTPM_EEETXC_TW_PHY_S 0
7136 #define PRTPM_EEETXC_TW_PHY_M MAKEMASK(0xFFFF, 0)
7137 #define PRTPM_RLPIC 0x001E43A0 /* Reset Source: GLOBR */
7138 #define PRTPM_RLPIC_ERLPIC_S 0
7139 #define PRTPM_RLPIC_ERLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7140 #define PRTPM_TLPIC 0x001E43C0 /* Reset Source: GLOBR */
7141 #define PRTPM_TLPIC_ETLPIC_S 0
7142 #define PRTPM_TLPIC_ETLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7143 #define GLRPB_DHW(_i) (0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7144 #define GLRPB_DHW_MAX_INDEX 15
7145 #define GLRPB_DHW_DHW_TCN_S 0
7146 #define GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0)
7147 #define GLRPB_DLW(_i) (0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7148 #define GLRPB_DLW_MAX_INDEX 15
7149 #define GLRPB_DLW_DLW_TCN_S 0
7150 #define GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0)
7151 #define GLRPB_DPS(_i) (0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7152 #define GLRPB_DPS_MAX_INDEX 15
7153 #define GLRPB_DPS_DPS_TCN_S 0
7154 #define GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0)
7155 #define GLRPB_DSI_EN 0x000AC324 /* Reset Source: CORER */
7156 #define GLRPB_DSI_EN_DSI_EN_S 0
7157 #define GLRPB_DSI_EN_DSI_EN_M BIT(0)
7158 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_S 1
7159 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_M BIT(1)
7160 #define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7161 #define GLRPB_SHW_MAX_INDEX 7
7162 #define GLRPB_SHW_SHW_S 0
7163 #define GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7164 #define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7165 #define GLRPB_SLW_MAX_INDEX 7
7166 #define GLRPB_SLW_SLW_S 0
7167 #define GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7168 #define GLRPB_SPS(_i) (0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7169 #define GLRPB_SPS_MAX_INDEX 7
7170 #define GLRPB_SPS_SPS_TCN_S 0
7171 #define GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0)
7172 #define GLRPB_TC_CFG(_i) (0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7173 #define GLRPB_TC_CFG_MAX_INDEX 31
7174 #define GLRPB_TC_CFG_D_POOL_S 0
7175 #define GLRPB_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0)
7176 #define GLRPB_TC_CFG_S_POOL_S 16
7177 #define GLRPB_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16)
7178 #define GLRPB_TCHW(_i) (0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7179 #define GLRPB_TCHW_MAX_INDEX 31
7180 #define GLRPB_TCHW_TCHW_S 0
7181 #define GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7182 #define GLRPB_TCLW(_i) (0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7183 #define GLRPB_TCLW_MAX_INDEX 31
7184 #define GLRPB_TCLW_TCLW_S 0
7185 #define GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7186 #define GLQF_APBVT(_i) (0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
7187 #define GLQF_APBVT_MAX_INDEX 2047
7188 #define GLQF_APBVT_APBVT_S 0
7189 #define GLQF_APBVT_APBVT_M MAKEMASK(0xFFFFFFFF, 0)
7190 #define GLQF_FD_CLSN_0 0x00460028 /* Reset Source: CORER */
7191 #define GLQF_FD_CLSN_0_HITSBCNT_S 0
7192 #define GLQF_FD_CLSN_0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7193 #define GLQF_FD_CLSN1 0x00460030 /* Reset Source: CORER */
7194 #define GLQF_FD_CLSN1_HITLBCNT_S 0
7195 #define GLQF_FD_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7196 #define GLQF_FD_CNT 0x00460018 /* Reset Source: CORER */
7197 #define GLQF_FD_CNT_FD_GCNT_S 0
7198 #define GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7199 #define GLQF_FD_CNT_FD_BCNT_S 16
7200 #define GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7201 #define GLQF_FD_CTL 0x00460000 /* Reset Source: CORER */
7202 #define GLQF_FD_CTL_FDLONG_S 0
7203 #define GLQF_FD_CTL_FDLONG_M MAKEMASK(0xF, 0)
7204 #define GLQF_FD_CTL_HASH_REPORT_S 4
7205 #define GLQF_FD_CTL_HASH_REPORT_M BIT(4)
7206 #define GLQF_FD_CTL_FLT_ADDR_REPORT_S 5
7207 #define GLQF_FD_CTL_FLT_ADDR_REPORT_M BIT(5)
7208 #define GLQF_FD_SIZE 0x00460010 /* Reset Source: CORER */
7209 #define GLQF_FD_SIZE_FD_GSIZE_S 0
7210 #define GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7211 #define GLQF_FD_SIZE_FD_BSIZE_S 16
7212 #define GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7213 #define GLQF_FDCNT_0 0x00460020 /* Reset Source: CORER */
7214 #define GLQF_FDCNT_0_BUCKETCNT_S 0
7215 #define GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0)
7216 #define GLQF_FDCNT_0_CNT_NOT_VLD_S 31
7217 #define GLQF_FDCNT_0_CNT_NOT_VLD_M BIT(31)
7218 #define GLQF_FDEVICTENA(_i) (0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
7219 #define GLQF_FDEVICTENA_MAX_INDEX 3
7220 #define GLQF_FDEVICTENA_FDEVICTENA_S 0
7221 #define GLQF_FDEVICTENA_FDEVICTENA_M MAKEMASK(0xFFFFFFFF, 0)
7222 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7223 #define GLQF_FDINSET_MAX_INDEX 127
7224 #define GLQF_FDINSET_FV_WORD_INDX0_S 0
7225 #define GLQF_FDINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7226 #define GLQF_FDINSET_FV_WORD_VAL0_S 7
7227 #define GLQF_FDINSET_FV_WORD_VAL0_M BIT(7)
7228 #define GLQF_FDINSET_FV_WORD_INDX1_S 8
7229 #define GLQF_FDINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7230 #define GLQF_FDINSET_FV_WORD_VAL1_S 15
7231 #define GLQF_FDINSET_FV_WORD_VAL1_M BIT(15)
7232 #define GLQF_FDINSET_FV_WORD_INDX2_S 16
7233 #define GLQF_FDINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7234 #define GLQF_FDINSET_FV_WORD_VAL2_S 23
7235 #define GLQF_FDINSET_FV_WORD_VAL2_M BIT(23)
7236 #define GLQF_FDINSET_FV_WORD_INDX3_S 24
7237 #define GLQF_FDINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7238 #define GLQF_FDINSET_FV_WORD_VAL3_S 31
7239 #define GLQF_FDINSET_FV_WORD_VAL3_M BIT(31)
7240 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7241 #define GLQF_FDMASK_MAX_INDEX 31
7242 #define GLQF_FDMASK_MSK_INDEX_S 0
7243 #define GLQF_FDMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7244 #define GLQF_FDMASK_MASK_S 16
7245 #define GLQF_FDMASK_MASK_M MAKEMASK(0xFFFF, 16)
7246 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7247 #define GLQF_FDMASK_SEL_MAX_INDEX 127
7248 #define GLQF_FDMASK_SEL_MASK_SEL_S 0
7249 #define GLQF_FDMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7250 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7251 #define GLQF_FDSWAP_MAX_INDEX 127
7252 #define GLQF_FDSWAP_FV_WORD_INDX0_S 0
7253 #define GLQF_FDSWAP_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7254 #define GLQF_FDSWAP_FV_WORD_VAL0_S 7
7255 #define GLQF_FDSWAP_FV_WORD_VAL0_M BIT(7)
7256 #define GLQF_FDSWAP_FV_WORD_INDX1_S 8
7257 #define GLQF_FDSWAP_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7258 #define GLQF_FDSWAP_FV_WORD_VAL1_S 15
7259 #define GLQF_FDSWAP_FV_WORD_VAL1_M BIT(15)
7260 #define GLQF_FDSWAP_FV_WORD_INDX2_S 16
7261 #define GLQF_FDSWAP_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7262 #define GLQF_FDSWAP_FV_WORD_VAL2_S 23
7263 #define GLQF_FDSWAP_FV_WORD_VAL2_M BIT(23)
7264 #define GLQF_FDSWAP_FV_WORD_INDX3_S 24
7265 #define GLQF_FDSWAP_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7266 #define GLQF_FDSWAP_FV_WORD_VAL3_S 31
7267 #define GLQF_FDSWAP_FV_WORD_VAL3_M BIT(31)
7268 #define GLQF_HINSET(_i, _j) (0x0040E000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7269 #define GLQF_HINSET_MAX_INDEX 127
7270 #define GLQF_HINSET_FV_WORD_INDX0_S 0
7271 #define GLQF_HINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7272 #define GLQF_HINSET_FV_WORD_VAL0_S 7
7273 #define GLQF_HINSET_FV_WORD_VAL0_M BIT(7)
7274 #define GLQF_HINSET_FV_WORD_INDX1_S 8
7275 #define GLQF_HINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7276 #define GLQF_HINSET_FV_WORD_VAL1_S 15
7277 #define GLQF_HINSET_FV_WORD_VAL1_M BIT(15)
7278 #define GLQF_HINSET_FV_WORD_INDX2_S 16
7279 #define GLQF_HINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7280 #define GLQF_HINSET_FV_WORD_VAL2_S 23
7281 #define GLQF_HINSET_FV_WORD_VAL2_M BIT(23)
7282 #define GLQF_HINSET_FV_WORD_INDX3_S 24
7283 #define GLQF_HINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7284 #define GLQF_HINSET_FV_WORD_VAL3_S 31
7285 #define GLQF_HINSET_FV_WORD_VAL3_M BIT(31)
7286 #define GLQF_HKEY(_i) (0x00456000 + ((_i) * 4)) /* _i=0...12 */ /* Reset Source: CORER */
7287 #define GLQF_HKEY_MAX_INDEX 12
7288 #define GLQF_HKEY_KEY_0_S 0
7289 #define GLQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
7290 #define GLQF_HKEY_KEY_1_S 8
7291 #define GLQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
7292 #define GLQF_HKEY_KEY_2_S 16
7293 #define GLQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
7294 #define GLQF_HKEY_KEY_3_S 24
7295 #define GLQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
7296 #define GLQF_HLUT(_i, _j) (0x00438000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...15 */ /* Reset Source: CORER */
7297 #define GLQF_HLUT_MAX_INDEX 127
7298 #define GLQF_HLUT_LUT0_S 0
7299 #define GLQF_HLUT_LUT0_M MAKEMASK(0x3F, 0)
7300 #define GLQF_HLUT_LUT1_S 8
7301 #define GLQF_HLUT_LUT1_M MAKEMASK(0x3F, 8)
7302 #define GLQF_HLUT_LUT2_S 16
7303 #define GLQF_HLUT_LUT2_M MAKEMASK(0x3F, 16)
7304 #define GLQF_HLUT_LUT3_S 24
7305 #define GLQF_HLUT_LUT3_M MAKEMASK(0x3F, 24)
7306 #define GLQF_HLUT_SIZE(_i) (0x00455400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7307 #define GLQF_HLUT_SIZE_MAX_INDEX 15
7308 #define GLQF_HLUT_SIZE_HSIZE_S 0
7309 #define GLQF_HLUT_SIZE_HSIZE_M BIT(0)
7310 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7311 #define GLQF_HMASK_MAX_INDEX 31
7312 #define GLQF_HMASK_MSK_INDEX_S 0
7313 #define GLQF_HMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7314 #define GLQF_HMASK_MASK_S 16
7315 #define GLQF_HMASK_MASK_M MAKEMASK(0xFFFF, 16)
7316 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7317 #define GLQF_HMASK_SEL_MAX_INDEX 127
7318 #define GLQF_HMASK_SEL_MASK_SEL_S 0
7319 #define GLQF_HMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7320 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7321 #define GLQF_HSYMM_MAX_INDEX 127
7322 #define GLQF_HSYMM_FV_SYMM_INDX0_S 0
7323 #define GLQF_HSYMM_FV_SYMM_INDX0_M MAKEMASK(0x1F, 0)
7324 #define GLQF_HSYMM_SYMM0_ENA_S 7
7325 #define GLQF_HSYMM_SYMM0_ENA_M BIT(7)
7326 #define GLQF_HSYMM_FV_SYMM_INDX1_S 8
7327 #define GLQF_HSYMM_FV_SYMM_INDX1_M MAKEMASK(0x1F, 8)
7328 #define GLQF_HSYMM_SYMM1_ENA_S 15
7329 #define GLQF_HSYMM_SYMM1_ENA_M BIT(15)
7330 #define GLQF_HSYMM_FV_SYMM_INDX2_S 16
7331 #define GLQF_HSYMM_FV_SYMM_INDX2_M MAKEMASK(0x1F, 16)
7332 #define GLQF_HSYMM_SYMM2_ENA_S 23
7333 #define GLQF_HSYMM_SYMM2_ENA_M BIT(23)
7334 #define GLQF_HSYMM_FV_SYMM_INDX3_S 24
7335 #define GLQF_HSYMM_FV_SYMM_INDX3_M MAKEMASK(0x1F, 24)
7336 #define GLQF_HSYMM_SYMM3_ENA_S 31
7337 #define GLQF_HSYMM_SYMM3_ENA_M BIT(31)
7338 #define GLQF_PE_APBVT_CNT 0x00455500 /* Reset Source: CORER */
7339 #define GLQF_PE_APBVT_CNT_APBVT_LAN_S 0
7340 #define GLQF_PE_APBVT_CNT_APBVT_LAN_M MAKEMASK(0xFFFFFFFF, 0)
7341 #define GLQF_PE_CMD 0x00471080 /* Reset Source: CORER */
7342 #define GLQF_PE_CMD_ADDREM_STS_S 0
7343 #define GLQF_PE_CMD_ADDREM_STS_M MAKEMASK(0xFFFFFF, 0)
7344 #define GLQF_PE_CMD_ADDREM_ID_S 28
7345 #define GLQF_PE_CMD_ADDREM_ID_M MAKEMASK(0xF, 28)
7346 #define GLQF_PE_CTL 0x004710C0 /* Reset Source: CORER */
7347 #define GLQF_PE_CTL_PELONG_S 0
7348 #define GLQF_PE_CTL_PELONG_M MAKEMASK(0xF, 0)
7349 #define GLQF_PE_CTL2(_i) (0x00455200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7350 #define GLQF_PE_CTL2_MAX_INDEX 31
7351 #define GLQF_PE_CTL2_TO_QH_S 0
7352 #define GLQF_PE_CTL2_TO_QH_M MAKEMASK(0x3, 0)
7353 #define GLQF_PE_CTL2_APBVT_ENA_S 2
7354 #define GLQF_PE_CTL2_APBVT_ENA_M BIT(2)
7355 #define GLQF_PE_FVE 0x0020E514 /* Reset Source: CORER */
7356 #define GLQF_PE_FVE_W_ENA_S 0
7357 #define GLQF_PE_FVE_W_ENA_M MAKEMASK(0xFFFFFF, 0)
7358 #define GLQF_PE_OSR_STS 0x00471040 /* Reset Source: CORER */
7359 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_S 0
7360 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_M MAKEMASK(0x3FF, 0)
7361 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_S 16
7362 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_M MAKEMASK(0x3FF, 16)
7363 #define GLQF_PEINSET(_i, _j) (0x00415000 + ((_i) * 4 + (_j) * 128)) /* _i=0...31, _j=0...5 */ /* Reset Source: CORER */
7364 #define GLQF_PEINSET_MAX_INDEX 31
7365 #define GLQF_PEINSET_FV_WORD_INDX0_S 0
7366 #define GLQF_PEINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7367 #define GLQF_PEINSET_FV_WORD_VAL0_S 7
7368 #define GLQF_PEINSET_FV_WORD_VAL0_M BIT(7)
7369 #define GLQF_PEINSET_FV_WORD_INDX1_S 8
7370 #define GLQF_PEINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7371 #define GLQF_PEINSET_FV_WORD_VAL1_S 15
7372 #define GLQF_PEINSET_FV_WORD_VAL1_M BIT(15)
7373 #define GLQF_PEINSET_FV_WORD_INDX2_S 16
7374 #define GLQF_PEINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7375 #define GLQF_PEINSET_FV_WORD_VAL2_S 23
7376 #define GLQF_PEINSET_FV_WORD_VAL2_M BIT(23)
7377 #define GLQF_PEINSET_FV_WORD_INDX3_S 24
7378 #define GLQF_PEINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7379 #define GLQF_PEINSET_FV_WORD_VAL3_S 31
7380 #define GLQF_PEINSET_FV_WORD_VAL3_M BIT(31)
7381 #define GLQF_PEMASK(_i) (0x00415400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7382 #define GLQF_PEMASK_MAX_INDEX 15
7383 #define GLQF_PEMASK_MSK_INDEX_S 0
7384 #define GLQF_PEMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7385 #define GLQF_PEMASK_MASK_S 16
7386 #define GLQF_PEMASK_MASK_M MAKEMASK(0xFFFF, 16)
7387 #define GLQF_PEMASK_SEL(_i) (0x00415500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7388 #define GLQF_PEMASK_SEL_MAX_INDEX 31
7389 #define GLQF_PEMASK_SEL_MASK_SEL_S 0
7390 #define GLQF_PEMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFF, 0)
7391 #define GLQF_PETABLE_CLR(_i) (0x000AA078 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
7392 #define GLQF_PETABLE_CLR_MAX_INDEX 1
7393 #define GLQF_PETABLE_CLR_VM_VF_NUM_S 0
7394 #define GLQF_PETABLE_CLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
7395 #define GLQF_PETABLE_CLR_VM_VF_TYPE_S 10
7396 #define GLQF_PETABLE_CLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
7397 #define GLQF_PETABLE_CLR_PF_NUM_S 12
7398 #define GLQF_PETABLE_CLR_PF_NUM_M MAKEMASK(0x7, 12)
7399 #define GLQF_PETABLE_CLR_PE_BUSY_S 16
7400 #define GLQF_PETABLE_CLR_PE_BUSY_M BIT(16)
7401 #define GLQF_PETABLE_CLR_PE_CLEAR_S 17
7402 #define GLQF_PETABLE_CLR_PE_CLEAR_M BIT(17)
7403 #define GLQF_PROF2TC(_i, _j) (0x0044D000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...3 */ /* Reset Source: CORER */
7404 #define GLQF_PROF2TC_MAX_INDEX 127
7405 #define GLQF_PROF2TC_OVERRIDE_ENA_0_S 0
7406 #define GLQF_PROF2TC_OVERRIDE_ENA_0_M BIT(0)
7407 #define GLQF_PROF2TC_REGION_0_S 1
7408 #define GLQF_PROF2TC_REGION_0_M MAKEMASK(0x7, 1)
7409 #define GLQF_PROF2TC_OVERRIDE_ENA_1_S 4
7410 #define GLQF_PROF2TC_OVERRIDE_ENA_1_M BIT(4)
7411 #define GLQF_PROF2TC_REGION_1_S 5
7412 #define GLQF_PROF2TC_REGION_1_M MAKEMASK(0x7, 5)
7413 #define GLQF_PROF2TC_OVERRIDE_ENA_2_S 8
7414 #define GLQF_PROF2TC_OVERRIDE_ENA_2_M BIT(8)
7415 #define GLQF_PROF2TC_REGION_2_S 9
7416 #define GLQF_PROF2TC_REGION_2_M MAKEMASK(0x7, 9)
7417 #define GLQF_PROF2TC_OVERRIDE_ENA_3_S 12
7418 #define GLQF_PROF2TC_OVERRIDE_ENA_3_M BIT(12)
7419 #define GLQF_PROF2TC_REGION_3_S 13
7420 #define GLQF_PROF2TC_REGION_3_M MAKEMASK(0x7, 13)
7421 #define GLQF_PROF2TC_OVERRIDE_ENA_4_S 16
7422 #define GLQF_PROF2TC_OVERRIDE_ENA_4_M BIT(16)
7423 #define GLQF_PROF2TC_REGION_4_S 17
7424 #define GLQF_PROF2TC_REGION_4_M MAKEMASK(0x7, 17)
7425 #define GLQF_PROF2TC_OVERRIDE_ENA_5_S 20
7426 #define GLQF_PROF2TC_OVERRIDE_ENA_5_M BIT(20)
7427 #define GLQF_PROF2TC_REGION_5_S 21
7428 #define GLQF_PROF2TC_REGION_5_M MAKEMASK(0x7, 21)
7429 #define GLQF_PROF2TC_OVERRIDE_ENA_6_S 24
7430 #define GLQF_PROF2TC_OVERRIDE_ENA_6_M BIT(24)
7431 #define GLQF_PROF2TC_REGION_6_S 25
7432 #define GLQF_PROF2TC_REGION_6_M MAKEMASK(0x7, 25)
7433 #define GLQF_PROF2TC_OVERRIDE_ENA_7_S 28
7434 #define GLQF_PROF2TC_OVERRIDE_ENA_7_M BIT(28)
7435 #define GLQF_PROF2TC_REGION_7_S 29
7436 #define GLQF_PROF2TC_REGION_7_M MAKEMASK(0x7, 29)
7437 #define PFQF_FD_CNT 0x00460180 /* Reset Source: CORER */
7438 #define PFQF_FD_CNT_FD_GCNT_S 0
7439 #define PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7440 #define PFQF_FD_CNT_FD_BCNT_S 16
7441 #define PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7442 #define PFQF_FD_ENA 0x0043A000 /* Reset Source: CORER */
7443 #define PFQF_FD_ENA_FD_ENA_S 0
7444 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
7445 #define PFQF_FD_SIZE 0x00460100 /* Reset Source: CORER */
7446 #define PFQF_FD_SIZE_FD_GSIZE_S 0
7447 #define PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7448 #define PFQF_FD_SIZE_FD_BSIZE_S 16
7449 #define PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7450 #define PFQF_FD_SUBTRACT 0x00460200 /* Reset Source: CORER */
7451 #define PFQF_FD_SUBTRACT_FD_GCNT_S 0
7452 #define PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7453 #define PFQF_FD_SUBTRACT_FD_BCNT_S 16
7454 #define PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7455 #define PFQF_HLUT(_i) (0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */
7456 #define PFQF_HLUT_MAX_INDEX 511
7457 #define PFQF_HLUT_LUT0_S 0
7458 #define PFQF_HLUT_LUT0_M MAKEMASK(0xFF, 0)
7459 #define PFQF_HLUT_LUT1_S 8
7460 #define PFQF_HLUT_LUT1_M MAKEMASK(0xFF, 8)
7461 #define PFQF_HLUT_LUT2_S 16
7462 #define PFQF_HLUT_LUT2_M MAKEMASK(0xFF, 16)
7463 #define PFQF_HLUT_LUT3_S 24
7464 #define PFQF_HLUT_LUT3_M MAKEMASK(0xFF, 24)
7465 #define PFQF_HLUT_SIZE 0x00455480 /* Reset Source: CORER */
7466 #define PFQF_HLUT_SIZE_HSIZE_S 0
7467 #define PFQF_HLUT_SIZE_HSIZE_M MAKEMASK(0x3, 0)
7468 #define PFQF_PE_CLSN0 0x00470480 /* Reset Source: CORER */
7469 #define PFQF_PE_CLSN0_HITSBCNT_S 0
7470 #define PFQF_PE_CLSN0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7471 #define PFQF_PE_CLSN1 0x00470500 /* Reset Source: CORER */
7472 #define PFQF_PE_CLSN1_HITLBCNT_S 0
7473 #define PFQF_PE_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7474 #define PFQF_PE_CTL1 0x00470000 /* Reset Source: CORER */
7475 #define PFQF_PE_CTL1_PEHSIZE_S 0
7476 #define PFQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7477 #define PFQF_PE_CTL2 0x00470040 /* Reset Source: CORER */
7478 #define PFQF_PE_CTL2_PEDSIZE_S 0
7479 #define PFQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7480 #define PFQF_PE_FILTERING_ENA 0x0043A080 /* Reset Source: CORER */
7481 #define PFQF_PE_FILTERING_ENA_PE_ENA_S 0
7482 #define PFQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7483 #define PFQF_PE_FLHD 0x00470100 /* Reset Source: CORER */
7484 #define PFQF_PE_FLHD_FLHD_S 0
7485 #define PFQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7486 #define PFQF_PE_ST_CTL 0x00470400 /* Reset Source: CORER */
7487 #define PFQF_PE_ST_CTL_PF_CNT_EN_S 0
7488 #define PFQF_PE_ST_CTL_PF_CNT_EN_M BIT(0)
7489 #define PFQF_PE_ST_CTL_VFS_CNT_EN_S 1
7490 #define PFQF_PE_ST_CTL_VFS_CNT_EN_M BIT(1)
7491 #define PFQF_PE_ST_CTL_VF_CNT_EN_S 2
7492 #define PFQF_PE_ST_CTL_VF_CNT_EN_M BIT(2)
7493 #define PFQF_PE_ST_CTL_VF_NUM_S 16
7494 #define PFQF_PE_ST_CTL_VF_NUM_M MAKEMASK(0xFF, 16)
7495 #define PFQF_PE_TC_CTL 0x00452080 /* Reset Source: CORER */
7496 #define PFQF_PE_TC_CTL_TC_EN_PF_S 0
7497 #define PFQF_PE_TC_CTL_TC_EN_PF_M MAKEMASK(0xFF, 0)
7498 #define PFQF_PE_TC_CTL_TC_EN_VF_S 16
7499 #define PFQF_PE_TC_CTL_TC_EN_VF_M MAKEMASK(0xFF, 16)
7500 #define PFQF_PECNT_0 0x00470200 /* Reset Source: CORER */
7501 #define PFQF_PECNT_0_BUCKETCNT_S 0
7502 #define PFQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7503 #define PFQF_PECNT_1 0x00470300 /* Reset Source: CORER */
7504 #define PFQF_PECNT_1_FLTCNT_S 0
7505 #define PFQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7506 #define VPQF_PE_CTL1(_VF) (0x00474000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7507 #define VPQF_PE_CTL1_MAX_INDEX 255
7508 #define VPQF_PE_CTL1_PEHSIZE_S 0
7509 #define VPQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7510 #define VPQF_PE_CTL2(_VF) (0x00474800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7511 #define VPQF_PE_CTL2_MAX_INDEX 255
7512 #define VPQF_PE_CTL2_PEDSIZE_S 0
7513 #define VPQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7514 #define VPQF_PE_FILTERING_ENA(_VF) (0x00455800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7515 #define VPQF_PE_FILTERING_ENA_MAX_INDEX 255
7516 #define VPQF_PE_FILTERING_ENA_PE_ENA_S 0
7517 #define VPQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7518 #define VPQF_PE_FLHD(_VF) (0x00472000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7519 #define VPQF_PE_FLHD_MAX_INDEX 255
7520 #define VPQF_PE_FLHD_FLHD_S 0
7521 #define VPQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7522 #define VPQF_PECNT_0(_VF) (0x00472800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7523 #define VPQF_PECNT_0_MAX_INDEX 255
7524 #define VPQF_PECNT_0_BUCKETCNT_S 0
7525 #define VPQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7526 #define VPQF_PECNT_1(_VF) (0x00473000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7527 #define VPQF_PECNT_1_MAX_INDEX 255
7528 #define VPQF_PECNT_1_FLTCNT_S 0
7529 #define VPQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7530 #define GLDCB_RMPMC 0x001223C8 /* Reset Source: CORER */
7531 #define GLDCB_RMPMC_RSPM_S 0
7532 #define GLDCB_RMPMC_RSPM_M MAKEMASK(0x3F, 0)
7533 #define GLDCB_RMPMC_MIQ_NODROP_MODE_S 6
7534 #define GLDCB_RMPMC_MIQ_NODROP_MODE_M MAKEMASK(0x1F, 6)
7535 #define GLDCB_RMPMC_RPM_DIS_S 31
7536 #define GLDCB_RMPMC_RPM_DIS_M BIT(31)
7537 #define GLDCB_RMPMS 0x001223CC /* Reset Source: CORER */
7538 #define GLDCB_RMPMS_RMPM_S 0
7539 #define GLDCB_RMPMS_RMPM_M MAKEMASK(0xFFFF, 0)
7540 #define GLDCB_RPCC 0x00122260 /* Reset Source: CORER */
7541 #define GLDCB_RPCC_EN_S 0
7542 #define GLDCB_RPCC_EN_M BIT(0)
7543 #define GLDCB_RPCC_SCL_FACT_S 4
7544 #define GLDCB_RPCC_SCL_FACT_M MAKEMASK(0x1F, 4)
7545 #define GLDCB_RPCC_THRSH_S 16
7546 #define GLDCB_RPCC_THRSH_M MAKEMASK(0xFFF, 16)
7547 #define GLDCB_RSPMC 0x001223C4 /* Reset Source: CORER */
7548 #define GLDCB_RSPMC_RSPM_S 0
7549 #define GLDCB_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
7550 #define GLDCB_RSPMC_RPM_MODE_S 8
7551 #define GLDCB_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
7552 #define GLDCB_RSPMC_PRR_MAX_EXP_S 10
7553 #define GLDCB_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
7554 #define GLDCB_RSPMC_PFCTIMER_S 14
7555 #define GLDCB_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
7556 #define GLDCB_RSPMC_RPM_DIS_S 31
7557 #define GLDCB_RSPMC_RPM_DIS_M BIT(31)
7558 #define GLDCB_RSPMS 0x001223C0 /* Reset Source: CORER */
7559 #define GLDCB_RSPMS_RSPM_S 0
7560 #define GLDCB_RSPMS_RSPM_M MAKEMASK(0x3FFFF, 0)
7561 #define GLDCB_RTCTI 0x001223D0 /* Reset Source: CORER */
7562 #define GLDCB_RTCTI_PFCTIMEOUT_TC_S 0
7563 #define GLDCB_RTCTI_PFCTIMEOUT_TC_M MAKEMASK(0xFFFFFFFF, 0)
7564 #define GLDCB_RTCTQ(_i) (0x001222C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7565 #define GLDCB_RTCTQ_MAX_INDEX 31
7566 #define GLDCB_RTCTQ_RXQNUM_S 0
7567 #define GLDCB_RTCTQ_RXQNUM_M MAKEMASK(0x7FF, 0)
7568 #define GLDCB_RTCTQ_IS_PF_Q_S 16
7569 #define GLDCB_RTCTQ_IS_PF_Q_M BIT(16)
7570 #define GLDCB_RTCTS(_i) (0x00122340 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7571 #define GLDCB_RTCTS_MAX_INDEX 31
7572 #define GLDCB_RTCTS_PFCTIMER_S 0
7573 #define GLDCB_RTCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
7574 #define GLRCB_CFG_COTF_CNT(_i) (0x001223D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7575 #define GLRCB_CFG_COTF_CNT_MAX_INDEX 7
7576 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_S 0
7577 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_M MAKEMASK(0x3F, 0)
7578 #define GLRCB_CFG_COTF_ST 0x001223F4 /* Reset Source: CORER */
7579 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_S 0
7580 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_M MAKEMASK(0xFF, 0)
7581 #define GLRPRS_PMCFG_DHW(_i) (0x00200388 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7582 #define GLRPRS_PMCFG_DHW_MAX_INDEX 15
7583 #define GLRPRS_PMCFG_DHW_DHW_S 0
7584 #define GLRPRS_PMCFG_DHW_DHW_M MAKEMASK(0xFFFFF, 0)
7585 #define GLRPRS_PMCFG_DLW(_i) (0x002003C8 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7586 #define GLRPRS_PMCFG_DLW_MAX_INDEX 15
7587 #define GLRPRS_PMCFG_DLW_DLW_S 0
7588 #define GLRPRS_PMCFG_DLW_DLW_M MAKEMASK(0xFFFFF, 0)
7589 #define GLRPRS_PMCFG_DPS(_i) (0x00200308 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7590 #define GLRPRS_PMCFG_DPS_MAX_INDEX 15
7591 #define GLRPRS_PMCFG_DPS_DPS_S 0
7592 #define GLRPRS_PMCFG_DPS_DPS_M MAKEMASK(0xFFFFF, 0)
7593 #define GLRPRS_PMCFG_SHW(_i) (0x00200448 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7594 #define GLRPRS_PMCFG_SHW_MAX_INDEX 7
7595 #define GLRPRS_PMCFG_SHW_SHW_S 0
7596 #define GLRPRS_PMCFG_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7597 #define GLRPRS_PMCFG_SLW(_i) (0x00200468 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7598 #define GLRPRS_PMCFG_SLW_MAX_INDEX 7
7599 #define GLRPRS_PMCFG_SLW_SLW_S 0
7600 #define GLRPRS_PMCFG_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7601 #define GLRPRS_PMCFG_SPS(_i) (0x00200408 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7602 #define GLRPRS_PMCFG_SPS_MAX_INDEX 7
7603 #define GLRPRS_PMCFG_SPS_SPS_S 0
7604 #define GLRPRS_PMCFG_SPS_SPS_M MAKEMASK(0xFFFFF, 0)
7605 #define GLRPRS_PMCFG_TC_CFG(_i) (0x00200488 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7606 #define GLRPRS_PMCFG_TC_CFG_MAX_INDEX 31
7607 #define GLRPRS_PMCFG_TC_CFG_D_POOL_S 0
7608 #define GLRPRS_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7609 #define GLRPRS_PMCFG_TC_CFG_S_POOL_S 16
7610 #define GLRPRS_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7611 #define GLRPRS_PMCFG_TCHW(_i) (0x00200588 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7612 #define GLRPRS_PMCFG_TCHW_MAX_INDEX 31
7613 #define GLRPRS_PMCFG_TCHW_TCHW_S 0
7614 #define GLRPRS_PMCFG_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7615 #define GLRPRS_PMCFG_TCLW(_i) (0x00200608 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7616 #define GLRPRS_PMCFG_TCLW_MAX_INDEX 31
7617 #define GLRPRS_PMCFG_TCLW_TCLW_S 0
7618 #define GLRPRS_PMCFG_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7619 #define GLSWT_PMCFG_TC_CFG(_i) (0x00204900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7620 #define GLSWT_PMCFG_TC_CFG_MAX_INDEX 31
7621 #define GLSWT_PMCFG_TC_CFG_D_POOL_S 0
7622 #define GLSWT_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7623 #define GLSWT_PMCFG_TC_CFG_S_POOL_S 16
7624 #define GLSWT_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7625 #define PRTDCB_RLANPMS 0x00122280 /* Reset Source: CORER */
7626 #define PRTDCB_RLANPMS_LANRPPM_S 0
7627 #define PRTDCB_RLANPMS_LANRPPM_M MAKEMASK(0x3FFFF, 0)
7628 #define PRTDCB_RPPMC 0x00122240 /* Reset Source: CORER */
7629 #define PRTDCB_RPPMC_LANRPPM_S 0
7630 #define PRTDCB_RPPMC_LANRPPM_M MAKEMASK(0xFF, 0)
7631 #define PRTDCB_RPPMC_RDMARPPM_S 8
7632 #define PRTDCB_RPPMC_RDMARPPM_M MAKEMASK(0xFF, 8)
7633 #define PRTDCB_RRDMAPMS 0x00122120 /* Reset Source: CORER */
7634 #define PRTDCB_RRDMAPMS_RDMARPPM_S 0
7635 #define PRTDCB_RRDMAPMS_RDMARPPM_M MAKEMASK(0x3FFFF, 0)
7636 #define GL_STAT_SWR_BPCH(_i) (0x00347804 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7637 #define GL_STAT_SWR_BPCH_MAX_INDEX 127
7638 #define GL_STAT_SWR_BPCH_VLBPCH_S 0
7639 #define GL_STAT_SWR_BPCH_VLBPCH_M MAKEMASK(0xFF, 0)
7640 #define GL_STAT_SWR_BPCL(_i) (0x00347800 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7641 #define GL_STAT_SWR_BPCL_MAX_INDEX 127
7642 #define GL_STAT_SWR_BPCL_VLBPCL_S 0
7643 #define GL_STAT_SWR_BPCL_VLBPCL_M MAKEMASK(0xFFFFFFFF, 0)
7644 #define GL_STAT_SWR_GORCH(_i) (0x00342004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7645 #define GL_STAT_SWR_GORCH_MAX_INDEX 127
7646 #define GL_STAT_SWR_GORCH_VLBCH_S 0
7647 #define GL_STAT_SWR_GORCH_VLBCH_M MAKEMASK(0xFF, 0)
7648 #define GL_STAT_SWR_GORCL(_i) (0x00342000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7649 #define GL_STAT_SWR_GORCL_MAX_INDEX 127
7650 #define GL_STAT_SWR_GORCL_VLBCL_S 0
7651 #define GL_STAT_SWR_GORCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7652 #define GL_STAT_SWR_GOTCH(_i) (0x00304004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7653 #define GL_STAT_SWR_GOTCH_MAX_INDEX 127
7654 #define GL_STAT_SWR_GOTCH_VLBCH_S 0
7655 #define GL_STAT_SWR_GOTCH_VLBCH_M MAKEMASK(0xFF, 0)
7656 #define GL_STAT_SWR_GOTCL(_i) (0x00304000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7657 #define GL_STAT_SWR_GOTCL_MAX_INDEX 127
7658 #define GL_STAT_SWR_GOTCL_VLBCL_S 0
7659 #define GL_STAT_SWR_GOTCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7660 #define GL_STAT_SWR_MPCH(_i) (0x00347404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7661 #define GL_STAT_SWR_MPCH_MAX_INDEX 127
7662 #define GL_STAT_SWR_MPCH_VLMPCH_S 0
7663 #define GL_STAT_SWR_MPCH_VLMPCH_M MAKEMASK(0xFF, 0)
7664 #define GL_STAT_SWR_MPCL(_i) (0x00347400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7665 #define GL_STAT_SWR_MPCL_MAX_INDEX 127
7666 #define GL_STAT_SWR_MPCL_VLMPCL_S 0
7667 #define GL_STAT_SWR_MPCL_VLMPCL_M MAKEMASK(0xFFFFFFFF, 0)
7668 #define GL_STAT_SWR_UPCH(_i) (0x00347004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7669 #define GL_STAT_SWR_UPCH_MAX_INDEX 127
7670 #define GL_STAT_SWR_UPCH_VLUPCH_S 0
7671 #define GL_STAT_SWR_UPCH_VLUPCH_M MAKEMASK(0xFF, 0)
7672 #define GL_STAT_SWR_UPCL(_i) (0x00347000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7673 #define GL_STAT_SWR_UPCL_MAX_INDEX 127
7674 #define GL_STAT_SWR_UPCL_VLUPCL_S 0
7675 #define GL_STAT_SWR_UPCL_VLUPCL_M MAKEMASK(0xFFFFFFFF, 0)
7676 #define GLPRT_AORCL(_i) (0x003812C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7677 #define GLPRT_AORCL_MAX_INDEX 7
7678 #define GLPRT_AORCL_AORCL_S 0
7679 #define GLPRT_AORCL_AORCL_M MAKEMASK(0xFFFFFFFF, 0)
7680 #define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7681 #define GLPRT_BPRCH_MAX_INDEX 7
7682 #define GLPRT_BPRCH_UPRCH_S 0
7683 #define GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0)
7684 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7685 #define GLPRT_BPRCL_MAX_INDEX 7
7686 #define GLPRT_BPRCL_UPRCH_S 0
7687 #define GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7688 #define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7689 #define GLPRT_BPTCH_MAX_INDEX 7
7690 #define GLPRT_BPTCH_UPRCH_S 0
7691 #define GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0)
7692 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7693 #define GLPRT_BPTCL_MAX_INDEX 7
7694 #define GLPRT_BPTCL_UPRCH_S 0
7695 #define GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7696 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7697 #define GLPRT_CRCERRS_MAX_INDEX 7
7698 #define GLPRT_CRCERRS_CRCERRS_S 0
7699 #define GLPRT_CRCERRS_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7700 #define GLPRT_CRCERRS_H(_i) (0x00380104 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7701 #define GLPRT_CRCERRS_H_MAX_INDEX 7
7702 #define GLPRT_CRCERRS_H_CRCERRS_S 0
7703 #define GLPRT_CRCERRS_H_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7704 #define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7705 #define GLPRT_GORCH_MAX_INDEX 7
7706 #define GLPRT_GORCH_GORCH_S 0
7707 #define GLPRT_GORCH_GORCH_M MAKEMASK(0xFF, 0)
7708 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7709 #define GLPRT_GORCL_MAX_INDEX 7
7710 #define GLPRT_GORCL_GORCL_S 0
7711 #define GLPRT_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
7712 #define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7713 #define GLPRT_GOTCH_MAX_INDEX 7
7714 #define GLPRT_GOTCH_GOTCH_S 0
7715 #define GLPRT_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
7716 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7717 #define GLPRT_GOTCL_MAX_INDEX 7
7718 #define GLPRT_GOTCL_GOTCL_S 0
7719 #define GLPRT_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
7720 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7721 #define GLPRT_ILLERRC_MAX_INDEX 7
7722 #define GLPRT_ILLERRC_ILLERRC_S 0
7723 #define GLPRT_ILLERRC_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7724 #define GLPRT_ILLERRC_H(_i) (0x003801C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7725 #define GLPRT_ILLERRC_H_MAX_INDEX 7
7726 #define GLPRT_ILLERRC_H_ILLERRC_S 0
7727 #define GLPRT_ILLERRC_H_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7728 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7729 #define GLPRT_LXOFFRXC_MAX_INDEX 7
7730 #define GLPRT_LXOFFRXC_LXOFFRXCNT_S 0
7731 #define GLPRT_LXOFFRXC_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7732 #define GLPRT_LXOFFRXC_H(_i) (0x003802C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7733 #define GLPRT_LXOFFRXC_H_MAX_INDEX 7
7734 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_S 0
7735 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7736 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7737 #define GLPRT_LXOFFTXC_MAX_INDEX 7
7738 #define GLPRT_LXOFFTXC_LXOFFTXC_S 0
7739 #define GLPRT_LXOFFTXC_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7740 #define GLPRT_LXOFFTXC_H(_i) (0x00381184 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7741 #define GLPRT_LXOFFTXC_H_MAX_INDEX 7
7742 #define GLPRT_LXOFFTXC_H_LXOFFTXC_S 0
7743 #define GLPRT_LXOFFTXC_H_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7744 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7745 #define GLPRT_LXONRXC_MAX_INDEX 7
7746 #define GLPRT_LXONRXC_LXONRXCNT_S 0
7747 #define GLPRT_LXONRXC_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7748 #define GLPRT_LXONRXC_H(_i) (0x00380284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7749 #define GLPRT_LXONRXC_H_MAX_INDEX 7
7750 #define GLPRT_LXONRXC_H_LXONRXCNT_S 0
7751 #define GLPRT_LXONRXC_H_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7752 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7753 #define GLPRT_LXONTXC_MAX_INDEX 7
7754 #define GLPRT_LXONTXC_LXONTXC_S 0
7755 #define GLPRT_LXONTXC_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7756 #define GLPRT_LXONTXC_H(_i) (0x00381144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7757 #define GLPRT_LXONTXC_H_MAX_INDEX 7
7758 #define GLPRT_LXONTXC_H_LXONTXC_S 0
7759 #define GLPRT_LXONTXC_H_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7760 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7761 #define GLPRT_MLFC_MAX_INDEX 7
7762 #define GLPRT_MLFC_MLFC_S 0
7763 #define GLPRT_MLFC_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7764 #define GLPRT_MLFC_H(_i) (0x00380044 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7765 #define GLPRT_MLFC_H_MAX_INDEX 7
7766 #define GLPRT_MLFC_H_MLFC_S 0
7767 #define GLPRT_MLFC_H_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7768 #define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7769 #define GLPRT_MPRCH_MAX_INDEX 7
7770 #define GLPRT_MPRCH_MPRCH_S 0
7771 #define GLPRT_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
7772 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7773 #define GLPRT_MPRCL_MAX_INDEX 7
7774 #define GLPRT_MPRCL_MPRCL_S 0
7775 #define GLPRT_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
7776 #define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7777 #define GLPRT_MPTCH_MAX_INDEX 7
7778 #define GLPRT_MPTCH_MPTCH_S 0
7779 #define GLPRT_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
7780 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7781 #define GLPRT_MPTCL_MAX_INDEX 7
7782 #define GLPRT_MPTCL_MPTCL_S 0
7783 #define GLPRT_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
7784 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7785 #define GLPRT_MRFC_MAX_INDEX 7
7786 #define GLPRT_MRFC_MRFC_S 0
7787 #define GLPRT_MRFC_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7788 #define GLPRT_MRFC_H(_i) (0x00380084 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7789 #define GLPRT_MRFC_H_MAX_INDEX 7
7790 #define GLPRT_MRFC_H_MRFC_S 0
7791 #define GLPRT_MRFC_H_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7792 #define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7793 #define GLPRT_PRC1023H_MAX_INDEX 7
7794 #define GLPRT_PRC1023H_PRC1023H_S 0
7795 #define GLPRT_PRC1023H_PRC1023H_M MAKEMASK(0xFF, 0)
7796 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7797 #define GLPRT_PRC1023L_MAX_INDEX 7
7798 #define GLPRT_PRC1023L_PRC1023L_S 0
7799 #define GLPRT_PRC1023L_PRC1023L_M MAKEMASK(0xFFFFFFFF, 0)
7800 #define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7801 #define GLPRT_PRC127H_MAX_INDEX 7
7802 #define GLPRT_PRC127H_PRC127H_S 0
7803 #define GLPRT_PRC127H_PRC127H_M MAKEMASK(0xFF, 0)
7804 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7805 #define GLPRT_PRC127L_MAX_INDEX 7
7806 #define GLPRT_PRC127L_PRC127L_S 0
7807 #define GLPRT_PRC127L_PRC127L_M MAKEMASK(0xFFFFFFFF, 0)
7808 #define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7809 #define GLPRT_PRC1522H_MAX_INDEX 7
7810 #define GLPRT_PRC1522H_PRC1522H_S 0
7811 #define GLPRT_PRC1522H_PRC1522H_M MAKEMASK(0xFF, 0)
7812 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7813 #define GLPRT_PRC1522L_MAX_INDEX 7
7814 #define GLPRT_PRC1522L_PRC1522L_S 0
7815 #define GLPRT_PRC1522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7816 #define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7817 #define GLPRT_PRC255H_MAX_INDEX 7
7818 #define GLPRT_PRC255H_PRTPRC255H_S 0
7819 #define GLPRT_PRC255H_PRTPRC255H_M MAKEMASK(0xFF, 0)
7820 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7821 #define GLPRT_PRC255L_MAX_INDEX 7
7822 #define GLPRT_PRC255L_PRC255L_S 0
7823 #define GLPRT_PRC255L_PRC255L_M MAKEMASK(0xFFFFFFFF, 0)
7824 #define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7825 #define GLPRT_PRC511H_MAX_INDEX 7
7826 #define GLPRT_PRC511H_PRC511H_S 0
7827 #define GLPRT_PRC511H_PRC511H_M MAKEMASK(0xFF, 0)
7828 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7829 #define GLPRT_PRC511L_MAX_INDEX 7
7830 #define GLPRT_PRC511L_PRC511L_S 0
7831 #define GLPRT_PRC511L_PRC511L_M MAKEMASK(0xFFFFFFFF, 0)
7832 #define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7833 #define GLPRT_PRC64H_MAX_INDEX 7
7834 #define GLPRT_PRC64H_PRC64H_S 0
7835 #define GLPRT_PRC64H_PRC64H_M MAKEMASK(0xFF, 0)
7836 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7837 #define GLPRT_PRC64L_MAX_INDEX 7
7838 #define GLPRT_PRC64L_PRC64L_S 0
7839 #define GLPRT_PRC64L_PRC64L_M MAKEMASK(0xFFFFFFFF, 0)
7840 #define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7841 #define GLPRT_PRC9522H_MAX_INDEX 7
7842 #define GLPRT_PRC9522H_PRC1522H_S 0
7843 #define GLPRT_PRC9522H_PRC1522H_M MAKEMASK(0xFF, 0)
7844 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7845 #define GLPRT_PRC9522L_MAX_INDEX 7
7846 #define GLPRT_PRC9522L_PRC1522L_S 0
7847 #define GLPRT_PRC9522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7848 #define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7849 #define GLPRT_PTC1023H_MAX_INDEX 7
7850 #define GLPRT_PTC1023H_PTC1023H_S 0
7851 #define GLPRT_PTC1023H_PTC1023H_M MAKEMASK(0xFF, 0)
7852 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7853 #define GLPRT_PTC1023L_MAX_INDEX 7
7854 #define GLPRT_PTC1023L_PTC1023L_S 0
7855 #define GLPRT_PTC1023L_PTC1023L_M MAKEMASK(0xFFFFFFFF, 0)
7856 #define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7857 #define GLPRT_PTC127H_MAX_INDEX 7
7858 #define GLPRT_PTC127H_PTC127H_S 0
7859 #define GLPRT_PTC127H_PTC127H_M MAKEMASK(0xFF, 0)
7860 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7861 #define GLPRT_PTC127L_MAX_INDEX 7
7862 #define GLPRT_PTC127L_PTC127L_S 0
7863 #define GLPRT_PTC127L_PTC127L_M MAKEMASK(0xFFFFFFFF, 0)
7864 #define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7865 #define GLPRT_PTC1522H_MAX_INDEX 7
7866 #define GLPRT_PTC1522H_PTC1522H_S 0
7867 #define GLPRT_PTC1522H_PTC1522H_M MAKEMASK(0xFF, 0)
7868 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7869 #define GLPRT_PTC1522L_MAX_INDEX 7
7870 #define GLPRT_PTC1522L_PTC1522L_S 0
7871 #define GLPRT_PTC1522L_PTC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7872 #define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7873 #define GLPRT_PTC255H_MAX_INDEX 7
7874 #define GLPRT_PTC255H_PTC255H_S 0
7875 #define GLPRT_PTC255H_PTC255H_M MAKEMASK(0xFF, 0)
7876 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7877 #define GLPRT_PTC255L_MAX_INDEX 7
7878 #define GLPRT_PTC255L_PTC255L_S 0
7879 #define GLPRT_PTC255L_PTC255L_M MAKEMASK(0xFFFFFFFF, 0)
7880 #define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7881 #define GLPRT_PTC511H_MAX_INDEX 7
7882 #define GLPRT_PTC511H_PTC511H_S 0
7883 #define GLPRT_PTC511H_PTC511H_M MAKEMASK(0xFF, 0)
7884 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7885 #define GLPRT_PTC511L_MAX_INDEX 7
7886 #define GLPRT_PTC511L_PTC511L_S 0
7887 #define GLPRT_PTC511L_PTC511L_M MAKEMASK(0xFFFFFFFF, 0)
7888 #define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7889 #define GLPRT_PTC64H_MAX_INDEX 7
7890 #define GLPRT_PTC64H_PTC64H_S 0
7891 #define GLPRT_PTC64H_PTC64H_M MAKEMASK(0xFF, 0)
7892 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7893 #define GLPRT_PTC64L_MAX_INDEX 7
7894 #define GLPRT_PTC64L_PTC64L_S 0
7895 #define GLPRT_PTC64L_PTC64L_M MAKEMASK(0xFFFFFFFF, 0)
7896 #define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7897 #define GLPRT_PTC9522H_MAX_INDEX 7
7898 #define GLPRT_PTC9522H_PTC9522H_S 0
7899 #define GLPRT_PTC9522H_PTC9522H_M MAKEMASK(0xFF, 0)
7900 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7901 #define GLPRT_PTC9522L_MAX_INDEX 7
7902 #define GLPRT_PTC9522L_PTC9522L_S 0
7903 #define GLPRT_PTC9522L_PTC9522L_M MAKEMASK(0xFFFFFFFF, 0)
7904 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7905 #define GLPRT_PXOFFRXC_MAX_INDEX 7
7906 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_S 0
7907 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7908 #define GLPRT_PXOFFRXC_H(_i, _j) (0x00380504 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7909 #define GLPRT_PXOFFRXC_H_MAX_INDEX 7
7910 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_S 0
7911 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7912 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7913 #define GLPRT_PXOFFTXC_MAX_INDEX 7
7914 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_S 0
7915 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7916 #define GLPRT_PXOFFTXC_H(_i, _j) (0x00380F44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7917 #define GLPRT_PXOFFTXC_H_MAX_INDEX 7
7918 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_S 0
7919 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7920 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7921 #define GLPRT_PXONRXC_MAX_INDEX 7
7922 #define GLPRT_PXONRXC_PRPXONRXCNT_S 0
7923 #define GLPRT_PXONRXC_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7924 #define GLPRT_PXONRXC_H(_i, _j) (0x00380304 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7925 #define GLPRT_PXONRXC_H_MAX_INDEX 7
7926 #define GLPRT_PXONRXC_H_PRPXONRXCNT_S 0
7927 #define GLPRT_PXONRXC_H_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7928 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7929 #define GLPRT_PXONTXC_MAX_INDEX 7
7930 #define GLPRT_PXONTXC_PRPXONTXC_S 0
7931 #define GLPRT_PXONTXC_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7932 #define GLPRT_PXONTXC_H(_i, _j) (0x00380D44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7933 #define GLPRT_PXONTXC_H_MAX_INDEX 7
7934 #define GLPRT_PXONTXC_H_PRPXONTXC_S 0
7935 #define GLPRT_PXONTXC_H_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7936 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7937 #define GLPRT_RFC_MAX_INDEX 7
7938 #define GLPRT_RFC_RFC_S 0
7939 #define GLPRT_RFC_RFC_M MAKEMASK(0xFFFFFFFF, 0)
7940 #define GLPRT_RFC_H(_i) (0x00380AC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7941 #define GLPRT_RFC_H_MAX_INDEX 7
7942 #define GLPRT_RFC_H_RFC_S 0
7943 #define GLPRT_RFC_H_RFC_M MAKEMASK(0xFFFFFFFF, 0)
7944 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7945 #define GLPRT_RJC_MAX_INDEX 7
7946 #define GLPRT_RJC_RJC_S 0
7947 #define GLPRT_RJC_RJC_M MAKEMASK(0xFFFFFFFF, 0)
7948 #define GLPRT_RJC_H(_i) (0x00380B04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7949 #define GLPRT_RJC_H_MAX_INDEX 7
7950 #define GLPRT_RJC_H_RJC_S 0
7951 #define GLPRT_RJC_H_RJC_M MAKEMASK(0xFFFFFFFF, 0)
7952 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7953 #define GLPRT_RLEC_MAX_INDEX 7
7954 #define GLPRT_RLEC_RLEC_S 0
7955 #define GLPRT_RLEC_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
7956 #define GLPRT_RLEC_H(_i) (0x00380144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7957 #define GLPRT_RLEC_H_MAX_INDEX 7
7958 #define GLPRT_RLEC_H_RLEC_S 0
7959 #define GLPRT_RLEC_H_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
7960 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7961 #define GLPRT_ROC_MAX_INDEX 7
7962 #define GLPRT_ROC_ROC_S 0
7963 #define GLPRT_ROC_ROC_M MAKEMASK(0xFFFFFFFF, 0)
7964 #define GLPRT_ROC_H(_i) (0x00380244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7965 #define GLPRT_ROC_H_MAX_INDEX 7
7966 #define GLPRT_ROC_H_ROC_S 0
7967 #define GLPRT_ROC_H_ROC_M MAKEMASK(0xFFFFFFFF, 0)
7968 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7969 #define GLPRT_RUC_MAX_INDEX 7
7970 #define GLPRT_RUC_RUC_S 0
7971 #define GLPRT_RUC_RUC_M MAKEMASK(0xFFFFFFFF, 0)
7972 #define GLPRT_RUC_H(_i) (0x00380204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7973 #define GLPRT_RUC_H_MAX_INDEX 7
7974 #define GLPRT_RUC_H_RUC_S 0
7975 #define GLPRT_RUC_H_RUC_M MAKEMASK(0xFFFFFFFF, 0)
7976 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7977 #define GLPRT_RXON2OFFCNT_MAX_INDEX 7
7978 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_S 0
7979 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
7980 #define GLPRT_RXON2OFFCNT_H(_i, _j) (0x00380704 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7981 #define GLPRT_RXON2OFFCNT_H_MAX_INDEX 7
7982 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_S 0
7983 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
7984 #define GLPRT_STDC(_i) (0x00340000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7985 #define GLPRT_STDC_MAX_INDEX 7
7986 #define GLPRT_STDC_STDC_S 0
7987 #define GLPRT_STDC_STDC_M MAKEMASK(0xFFFFFFFF, 0)
7988 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7989 #define GLPRT_TDOLD_MAX_INDEX 7
7990 #define GLPRT_TDOLD_GLPRT_TDOLD_S 0
7991 #define GLPRT_TDOLD_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
7992 #define GLPRT_TDOLD_H(_i) (0x00381284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7993 #define GLPRT_TDOLD_H_MAX_INDEX 7
7994 #define GLPRT_TDOLD_H_GLPRT_TDOLD_S 0
7995 #define GLPRT_TDOLD_H_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
7996 #define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7997 #define GLPRT_UPRCH_MAX_INDEX 7
7998 #define GLPRT_UPRCH_UPRCH_S 0
7999 #define GLPRT_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8000 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8001 #define GLPRT_UPRCL_MAX_INDEX 7
8002 #define GLPRT_UPRCL_UPRCL_S 0
8003 #define GLPRT_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8004 #define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8005 #define GLPRT_UPTCH_MAX_INDEX 7
8006 #define GLPRT_UPTCH_UPTCH_S 0
8007 #define GLPRT_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
8008 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8009 #define GLPRT_UPTCL_MAX_INDEX 7
8010 #define GLPRT_UPTCL_VUPTCH_S 0
8011 #define GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0)
8012 #define GLSTAT_ACL_CNT_0_H(_i) (0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8013 #define GLSTAT_ACL_CNT_0_H_MAX_INDEX 511
8014 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_S 0
8015 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8016 #define GLSTAT_ACL_CNT_0_L(_i) (0x00388000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8017 #define GLSTAT_ACL_CNT_0_L_MAX_INDEX 511
8018 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_S 0
8019 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8020 #define GLSTAT_ACL_CNT_1_H(_i) (0x00389004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8021 #define GLSTAT_ACL_CNT_1_H_MAX_INDEX 511
8022 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_S 0
8023 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8024 #define GLSTAT_ACL_CNT_1_L(_i) (0x00389000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8025 #define GLSTAT_ACL_CNT_1_L_MAX_INDEX 511
8026 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_S 0
8027 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8028 #define GLSTAT_ACL_CNT_2_H(_i) (0x0038A004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8029 #define GLSTAT_ACL_CNT_2_H_MAX_INDEX 511
8030 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_S 0
8031 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8032 #define GLSTAT_ACL_CNT_2_L(_i) (0x0038A000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8033 #define GLSTAT_ACL_CNT_2_L_MAX_INDEX 511
8034 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_S 0
8035 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8036 #define GLSTAT_ACL_CNT_3_H(_i) (0x0038B004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8037 #define GLSTAT_ACL_CNT_3_H_MAX_INDEX 511
8038 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_S 0
8039 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8040 #define GLSTAT_ACL_CNT_3_L(_i) (0x0038B000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8041 #define GLSTAT_ACL_CNT_3_L_MAX_INDEX 511
8042 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_S 0
8043 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8044 #define GLSTAT_FD_CNT0H(_i) (0x003A0004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8045 #define GLSTAT_FD_CNT0H_MAX_INDEX 4095
8046 #define GLSTAT_FD_CNT0H_FD0_CNT_H_S 0
8047 #define GLSTAT_FD_CNT0H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8048 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8049 #define GLSTAT_FD_CNT0L_MAX_INDEX 4095
8050 #define GLSTAT_FD_CNT0L_FD0_CNT_L_S 0
8051 #define GLSTAT_FD_CNT0L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8052 #define GLSTAT_FD_CNT1H(_i) (0x003A8004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8053 #define GLSTAT_FD_CNT1H_MAX_INDEX 4095
8054 #define GLSTAT_FD_CNT1H_FD0_CNT_H_S 0
8055 #define GLSTAT_FD_CNT1H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8056 #define GLSTAT_FD_CNT1L(_i) (0x003A8000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8057 #define GLSTAT_FD_CNT1L_MAX_INDEX 4095
8058 #define GLSTAT_FD_CNT1L_FD0_CNT_L_S 0
8059 #define GLSTAT_FD_CNT1L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8060 #define GLSW_BPRCH(_i) (0x00346204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8061 #define GLSW_BPRCH_MAX_INDEX 31
8062 #define GLSW_BPRCH_BPRCH_S 0
8063 #define GLSW_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8064 #define GLSW_BPRCL(_i) (0x00346200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8065 #define GLSW_BPRCL_MAX_INDEX 31
8066 #define GLSW_BPRCL_BPRCL_S 0
8067 #define GLSW_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8068 #define GLSW_BPTCH(_i) (0x00310204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8069 #define GLSW_BPTCH_MAX_INDEX 31
8070 #define GLSW_BPTCH_BPTCH_S 0
8071 #define GLSW_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8072 #define GLSW_BPTCL(_i) (0x00310200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8073 #define GLSW_BPTCL_MAX_INDEX 31
8074 #define GLSW_BPTCL_BPTCL_S 0
8075 #define GLSW_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8076 #define GLSW_GORCH(_i) (0x00341004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8077 #define GLSW_GORCH_MAX_INDEX 31
8078 #define GLSW_GORCH_GORCH_S 0
8079 #define GLSW_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8080 #define GLSW_GORCL(_i) (0x00341000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8081 #define GLSW_GORCL_MAX_INDEX 31
8082 #define GLSW_GORCL_GORCL_S 0
8083 #define GLSW_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8084 #define GLSW_GOTCH(_i) (0x00302004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8085 #define GLSW_GOTCH_MAX_INDEX 31
8086 #define GLSW_GOTCH_GOTCH_S 0
8087 #define GLSW_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8088 #define GLSW_GOTCL(_i) (0x00302000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8089 #define GLSW_GOTCL_MAX_INDEX 31
8090 #define GLSW_GOTCL_GOTCL_S 0
8091 #define GLSW_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8092 #define GLSW_MPRCH(_i) (0x00346104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8093 #define GLSW_MPRCH_MAX_INDEX 31
8094 #define GLSW_MPRCH_MPRCH_S 0
8095 #define GLSW_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8096 #define GLSW_MPRCL(_i) (0x00346100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8097 #define GLSW_MPRCL_MAX_INDEX 31
8098 #define GLSW_MPRCL_MPRCL_S 0
8099 #define GLSW_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8100 #define GLSW_MPTCH(_i) (0x00310104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8101 #define GLSW_MPTCH_MAX_INDEX 31
8102 #define GLSW_MPTCH_MPTCH_S 0
8103 #define GLSW_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8104 #define GLSW_MPTCL(_i) (0x00310100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8105 #define GLSW_MPTCL_MAX_INDEX 31
8106 #define GLSW_MPTCL_MPTCL_S 0
8107 #define GLSW_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8108 #define GLSW_UPRCH(_i) (0x00346004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8109 #define GLSW_UPRCH_MAX_INDEX 31
8110 #define GLSW_UPRCH_UPRCH_S 0
8111 #define GLSW_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8112 #define GLSW_UPRCL(_i) (0x00346000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8113 #define GLSW_UPRCL_MAX_INDEX 31
8114 #define GLSW_UPRCL_UPRCL_S 0
8115 #define GLSW_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8116 #define GLSW_UPTCH(_i) (0x00310004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8117 #define GLSW_UPTCH_MAX_INDEX 31
8118 #define GLSW_UPTCH_UPTCH_S 0
8119 #define GLSW_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
8120 #define GLSW_UPTCL(_i) (0x00310000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8121 #define GLSW_UPTCL_MAX_INDEX 31
8122 #define GLSW_UPTCL_UPTCL_S 0
8123 #define GLSW_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8124 #define GLSWID_RUPP(_i) (0x00345000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
8125 #define GLSWID_RUPP_MAX_INDEX 255
8126 #define GLSWID_RUPP_RUPP_S 0
8127 #define GLSWID_RUPP_RUPP_M MAKEMASK(0xFFFFFFFF, 0)
8128 #define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8129 #define GLV_BPRCH_MAX_INDEX 767
8130 #define GLV_BPRCH_BPRCH_S 0
8131 #define GLV_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8132 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8133 #define GLV_BPRCL_MAX_INDEX 767
8134 #define GLV_BPRCL_BPRCL_S 0
8135 #define GLV_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8136 #define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8137 #define GLV_BPTCH_MAX_INDEX 767
8138 #define GLV_BPTCH_BPTCH_S 0
8139 #define GLV_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8140 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8141 #define GLV_BPTCL_MAX_INDEX 767
8142 #define GLV_BPTCL_BPTCL_S 0
8143 #define GLV_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8144 #define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8145 #define GLV_GORCH_MAX_INDEX 767
8146 #define GLV_GORCH_GORCH_S 0
8147 #define GLV_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8148 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8149 #define GLV_GORCL_MAX_INDEX 767
8150 #define GLV_GORCL_GORCL_S 0
8151 #define GLV_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8152 #define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8153 #define GLV_GOTCH_MAX_INDEX 767
8154 #define GLV_GOTCH_GOTCH_S 0
8155 #define GLV_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8156 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8157 #define GLV_GOTCL_MAX_INDEX 767
8158 #define GLV_GOTCL_GOTCL_S 0
8159 #define GLV_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8160 #define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8161 #define GLV_MPRCH_MAX_INDEX 767
8162 #define GLV_MPRCH_MPRCH_S 0
8163 #define GLV_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8164 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8165 #define GLV_MPRCL_MAX_INDEX 767
8166 #define GLV_MPRCL_MPRCL_S 0
8167 #define GLV_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8168 #define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8169 #define GLV_MPTCH_MAX_INDEX 767
8170 #define GLV_MPTCH_MPTCH_S 0
8171 #define GLV_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8172 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8173 #define GLV_MPTCL_MAX_INDEX 767
8174 #define GLV_MPTCL_MPTCL_S 0
8175 #define GLV_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8176 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8177 #define GLV_RDPC_MAX_INDEX 767
8178 #define GLV_RDPC_RDPC_S 0
8179 #define GLV_RDPC_RDPC_M MAKEMASK(0xFFFFFFFF, 0)
8180 #define GLV_REPC(_i) (0x00295804 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8181 #define GLV_REPC_MAX_INDEX 767
8182 #define GLV_REPC_NO_DESC_CNT_S 0
8183 #define GLV_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
8184 #define GLV_REPC_ERROR_CNT_S 16
8185 #define GLV_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
8186 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8187 #define GLV_TEPC_MAX_INDEX 767
8188 #define GLV_TEPC_TEPC_S 0
8189 #define GLV_TEPC_TEPC_M MAKEMASK(0xFFFFFFFF, 0)
8190 #define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8191 #define GLV_UPRCH_MAX_INDEX 767
8192 #define GLV_UPRCH_UPRCH_S 0
8193 #define GLV_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8194 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8195 #define GLV_UPRCL_MAX_INDEX 767
8196 #define GLV_UPRCL_UPRCL_S 0
8197 #define GLV_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8198 #define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8199 #define GLV_UPTCH_MAX_INDEX 767
8200 #define GLV_UPTCH_GLVUPTCH_S 0
8201 #define GLV_UPTCH_GLVUPTCH_M MAKEMASK(0xFF, 0)
8202 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8203 #define GLV_UPTCL_MAX_INDEX 767
8204 #define GLV_UPTCL_UPTCL_S 0
8205 #define GLV_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8206 #define GLVEBUP_RBCH(_i, _j) (0x00343004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8207 #define GLVEBUP_RBCH_MAX_INDEX 7
8208 #define GLVEBUP_RBCH_UPBCH_S 0
8209 #define GLVEBUP_RBCH_UPBCH_M MAKEMASK(0xFF, 0)
8210 #define GLVEBUP_RBCL(_i, _j) (0x00343000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8211 #define GLVEBUP_RBCL_MAX_INDEX 7
8212 #define GLVEBUP_RBCL_UPBCL_S 0
8213 #define GLVEBUP_RBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8214 #define GLVEBUP_RPCH(_i, _j) (0x00344004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8215 #define GLVEBUP_RPCH_MAX_INDEX 7
8216 #define GLVEBUP_RPCH_UPPCH_S 0
8217 #define GLVEBUP_RPCH_UPPCH_M MAKEMASK(0xFF, 0)
8218 #define GLVEBUP_RPCL(_i, _j) (0x00344000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8219 #define GLVEBUP_RPCL_MAX_INDEX 7
8220 #define GLVEBUP_RPCL_UPPCL_S 0
8221 #define GLVEBUP_RPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8222 #define GLVEBUP_TBCH(_i, _j) (0x00306004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8223 #define GLVEBUP_TBCH_MAX_INDEX 7
8224 #define GLVEBUP_TBCH_UPBCH_S 0
8225 #define GLVEBUP_TBCH_UPBCH_M MAKEMASK(0xFF, 0)
8226 #define GLVEBUP_TBCL(_i, _j) (0x00306000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8227 #define GLVEBUP_TBCL_MAX_INDEX 7
8228 #define GLVEBUP_TBCL_UPBCL_S 0
8229 #define GLVEBUP_TBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8230 #define GLVEBUP_TPCH(_i, _j) (0x00308004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8231 #define GLVEBUP_TPCH_MAX_INDEX 7
8232 #define GLVEBUP_TPCH_UPPCH_S 0
8233 #define GLVEBUP_TPCH_UPPCH_M MAKEMASK(0xFF, 0)
8234 #define GLVEBUP_TPCL(_i, _j) (0x00308000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8235 #define GLVEBUP_TPCL_MAX_INDEX 7
8236 #define GLVEBUP_TPCL_UPPCL_S 0
8237 #define GLVEBUP_TPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8238 #define PRTRPB_LDPC 0x000AC280 /* Reset Source: CORER */
8239 #define PRTRPB_LDPC_CRCERRS_S 0
8240 #define PRTRPB_LDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8241 #define PRTRPB_RDPC 0x000AC260 /* Reset Source: CORER */
8242 #define PRTRPB_RDPC_CRCERRS_S 0
8243 #define PRTRPB_RDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8244 #define PRTTPB_STAT_TC_BYTES_SENTL(_i) (0x00098200 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8245 #define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX 63
8246 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0
8247 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8248 #define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
8249 #define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX 7
8250 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0
8251 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)
8252 #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8253 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
8254 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0
8255 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8256 #define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */
8257 #define EMP_SWT_PRUNIND_OPCODE_S 0
8258 #define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0)
8259 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S 4
8260 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4)
8261 #define EMP_SWT_PRUNIND_VSI_NUM_S 16
8262 #define EMP_SWT_PRUNIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8263 #define EMP_SWT_PRUNIND_BIT_VALUE_S 31
8264 #define EMP_SWT_PRUNIND_BIT_VALUE_M BIT(31)
8265 #define EMP_SWT_REPIND 0x0020401C /* Reset Source: CORER */
8266 #define EMP_SWT_REPIND_OPCODE_S 0
8267 #define EMP_SWT_REPIND_OPCODE_M MAKEMASK(0xF, 0)
8268 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_S 4
8269 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_M MAKEMASK(0x3FF, 4)
8270 #define EMP_SWT_REPIND_VSI_NUM_S 16
8271 #define EMP_SWT_REPIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8272 #define EMP_SWT_REPIND_BIT_VALUE_S 31
8273 #define EMP_SWT_REPIND_BIT_VALUE_M BIT(31)
8274 #define GL_OVERRIDEC 0x002040A4 /* Reset Source: CORER */
8275 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S 0
8276 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M MAKEMASK(0xFFFF, 0)
8277 #define GL_OVERRIDEC_LAST_VSI_S 16
8278 #define GL_OVERRIDEC_LAST_VSI_M MAKEMASK(0x3FF, 16)
8279 #define GL_PLG_AVG_CALC_CFG 0x0020A5AC /* Reset Source: CORER */
8280 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_S 0
8281 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_M MAKEMASK(0x7FFFFFFF, 0)
8282 #define GL_PLG_AVG_CALC_CFG_MODE_S 31
8283 #define GL_PLG_AVG_CALC_CFG_MODE_M BIT(31)
8284 #define GL_PLG_AVG_CALC_ST 0x0020A5B0 /* Reset Source: CORER */
8285 #define GL_PLG_AVG_CALC_ST_IN_DATA_S 0
8286 #define GL_PLG_AVG_CALC_ST_IN_DATA_M MAKEMASK(0x7FFF, 0)
8287 #define GL_PLG_AVG_CALC_ST_OUT_DATA_S 16
8288 #define GL_PLG_AVG_CALC_ST_OUT_DATA_M MAKEMASK(0x7FFF, 16)
8289 #define GL_PLG_AVG_CALC_ST_VALID_S 31
8290 #define GL_PLG_AVG_CALC_ST_VALID_M BIT(31)
8291 #define GL_PRE_CFG_CMD 0x00214090 /* Reset Source: CORER */
8292 #define GL_PRE_CFG_CMD_ADDR_S 0
8293 #define GL_PRE_CFG_CMD_ADDR_M MAKEMASK(0x1FFF, 0)
8294 #define GL_PRE_CFG_CMD_TBLIDX_S 16
8295 #define GL_PRE_CFG_CMD_TBLIDX_M MAKEMASK(0x7, 16)
8296 #define GL_PRE_CFG_CMD_CMD_S 29
8297 #define GL_PRE_CFG_CMD_CMD_M BIT(29)
8298 #define GL_PRE_CFG_CMD_DONE_S 31
8299 #define GL_PRE_CFG_CMD_DONE_M BIT(31)
8300 #define GL_PRE_CFG_DATA(_i) (0x00214074 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
8301 #define GL_PRE_CFG_DATA_MAX_INDEX 6
8302 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_S 0
8303 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_M MAKEMASK(0xFFFFFFFF, 0)
8304 #define GL_SWT_FUNCFILT 0x001D2698 /* Reset Source: CORER */
8305 #define GL_SWT_FUNCFILT_FUNCFILT_S 0
8306 #define GL_SWT_FUNCFILT_FUNCFILT_M BIT(0)
8307 #define GL_SWT_FW_STS(_i) (0x00216000 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
8308 #define GL_SWT_FW_STS_MAX_INDEX 5
8309 #define GL_SWT_FW_STS_GL_SWT_FW_STS_S 0
8310 #define GL_SWT_FW_STS_GL_SWT_FW_STS_M MAKEMASK(0xFFFFFFFF, 0)
8311 #define GL_SWT_LAT_DOUBLE 0x00204004 /* Reset Source: CORER */
8312 #define GL_SWT_LAT_DOUBLE_BASE_S 0
8313 #define GL_SWT_LAT_DOUBLE_BASE_M MAKEMASK(0x7FF, 0)
8314 #define GL_SWT_LAT_DOUBLE_SIZE_S 16
8315 #define GL_SWT_LAT_DOUBLE_SIZE_M MAKEMASK(0x7FF, 16)
8316 #define GL_SWT_LAT_QUAD 0x00204008 /* Reset Source: CORER */
8317 #define GL_SWT_LAT_QUAD_BASE_S 0
8318 #define GL_SWT_LAT_QUAD_BASE_M MAKEMASK(0x7FF, 0)
8319 #define GL_SWT_LAT_QUAD_SIZE_S 16
8320 #define GL_SWT_LAT_QUAD_SIZE_M MAKEMASK(0x7FF, 16)
8321 #define GL_SWT_LAT_SINGLE 0x00204000 /* Reset Source: CORER */
8322 #define GL_SWT_LAT_SINGLE_BASE_S 0
8323 #define GL_SWT_LAT_SINGLE_BASE_M MAKEMASK(0x7FF, 0)
8324 #define GL_SWT_LAT_SINGLE_SIZE_S 16
8325 #define GL_SWT_LAT_SINGLE_SIZE_M MAKEMASK(0x7FF, 16)
8326 #define GL_SWT_MD_PRI 0x002040AC /* Reset Source: CORER */
8327 #define GL_SWT_MD_PRI_VSI_PRI_S 0
8328 #define GL_SWT_MD_PRI_VSI_PRI_M MAKEMASK(0x7, 0)
8329 #define GL_SWT_MD_PRI_LB_PRI_S 4
8330 #define GL_SWT_MD_PRI_LB_PRI_M MAKEMASK(0x7, 4)
8331 #define GL_SWT_MD_PRI_LAN_EN_PRI_S 8
8332 #define GL_SWT_MD_PRI_LAN_EN_PRI_M MAKEMASK(0x7, 8)
8333 #define GL_SWT_MD_PRI_QH_PRI_S 12
8334 #define GL_SWT_MD_PRI_QH_PRI_M MAKEMASK(0x7, 12)
8335 #define GL_SWT_MD_PRI_QL_PRI_S 16
8336 #define GL_SWT_MD_PRI_QL_PRI_M MAKEMASK(0x7, 16)
8337 #define GL_SWT_MIRTARVSI(_i) (0x00204500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8338 #define GL_SWT_MIRTARVSI_MAX_INDEX 63
8339 #define GL_SWT_MIRTARVSI_VFVMNUMBER_S 0
8340 #define GL_SWT_MIRTARVSI_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
8341 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_S 10
8342 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
8343 #define GL_SWT_MIRTARVSI_PFNUMBER_S 12
8344 #define GL_SWT_MIRTARVSI_PFNUMBER_M MAKEMASK(0x7, 12)
8345 #define GL_SWT_MIRTARVSI_TARGETVSI_S 20
8346 #define GL_SWT_MIRTARVSI_TARGETVSI_M MAKEMASK(0x3FF, 20)
8347 #define GL_SWT_MIRTARVSI_RULEENABLE_S 31
8348 #define GL_SWT_MIRTARVSI_RULEENABLE_M BIT(31)
8349 #define GL_SWT_SWIDFVIDX 0x00214114 /* Reset Source: CORER */
8350 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_S 0
8351 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_M MAKEMASK(0x3F, 0)
8352 #define GL_SWT_SWIDFVIDX_PORT_TYPE_S 31
8353 #define GL_SWT_SWIDFVIDX_PORT_TYPE_M BIT(31)
8354 #define GL_VP_SWITCHID(_i) (0x00214094 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8355 #define GL_VP_SWITCHID_MAX_INDEX 31
8356 #define GL_VP_SWITCHID_SWITCHID_S 0
8357 #define GL_VP_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8358 #define GLSWID_STAT_BLOCK(_i) (0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
8359 #define GLSWID_STAT_BLOCK_MAX_INDEX 255
8360 #define GLSWID_STAT_BLOCK_VEBID_S 0
8361 #define GLSWID_STAT_BLOCK_VEBID_M MAKEMASK(0x1F, 0)
8362 #define GLSWID_STAT_BLOCK_VEBID_VALID_S 31
8363 #define GLSWID_STAT_BLOCK_VEBID_VALID_M BIT(31)
8364 #define GLSWT_ACT_RESP_0 0x0020A5A4 /* Reset Source: CORER */
8365 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_S 0
8366 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8367 #define GLSWT_ACT_RESP_1 0x0020A5A8 /* Reset Source: CORER */
8368 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_S 0
8369 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8370 #define GLSWT_ARB_MODE 0x0020A674 /* Reset Source: CORER */
8371 #define GLSWT_ARB_MODE_FLU_PRI_SHM_S 0
8372 #define GLSWT_ARB_MODE_FLU_PRI_SHM_M BIT(0)
8373 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_S 1
8374 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_M BIT(1)
8375 #define PRT_SBPVSI 0x00204120 /* Reset Source: CORER */
8376 #define PRT_SBPVSI_BAD_FRAMES_VSI_S 0
8377 #define PRT_SBPVSI_BAD_FRAMES_VSI_M MAKEMASK(0x3FF, 0)
8378 #define PRT_SBPVSI_SBP_S 31
8379 #define PRT_SBPVSI_SBP_M BIT(31)
8380 #define PRT_SCSTS 0x00204140 /* Reset Source: CORER */
8381 #define PRT_SCSTS_BSCA_S 0
8382 #define PRT_SCSTS_BSCA_M BIT(0)
8383 #define PRT_SCSTS_BSCAP_S 1
8384 #define PRT_SCSTS_BSCAP_M BIT(1)
8385 #define PRT_SCSTS_MSCA_S 2
8386 #define PRT_SCSTS_MSCA_M BIT(2)
8387 #define PRT_SCSTS_MSCAP_S 3
8388 #define PRT_SCSTS_MSCAP_M BIT(3)
8389 #define PRT_SWT_BSCCNT 0x00204160 /* Reset Source: CORER */
8390 #define PRT_SWT_BSCCNT_CCOUNT_S 0
8391 #define PRT_SWT_BSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8392 #define PRT_SWT_BSCTRH 0x00204180 /* Reset Source: CORER */
8393 #define PRT_SWT_BSCTRH_UTRESH_S 0
8394 #define PRT_SWT_BSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8395 #define PRT_SWT_MIREG 0x002042A0 /* Reset Source: CORER */
8396 #define PRT_SWT_MIREG_MIRRULE_S 0
8397 #define PRT_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8398 #define PRT_SWT_MIREG_MIRENA_S 7
8399 #define PRT_SWT_MIREG_MIRENA_M BIT(7)
8400 #define PRT_SWT_MIRIG 0x00204280 /* Reset Source: CORER */
8401 #define PRT_SWT_MIRIG_MIRRULE_S 0
8402 #define PRT_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8403 #define PRT_SWT_MIRIG_MIRENA_S 7
8404 #define PRT_SWT_MIRIG_MIRENA_M BIT(7)
8405 #define PRT_SWT_MSCCNT 0x00204100 /* Reset Source: CORER */
8406 #define PRT_SWT_MSCCNT_CCOUNT_S 0
8407 #define PRT_SWT_MSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8408 #define PRT_SWT_MSCTRH 0x002041C0 /* Reset Source: CORER */
8409 #define PRT_SWT_MSCTRH_UTRESH_S 0
8410 #define PRT_SWT_MSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8411 #define PRT_SWT_SCBI 0x002041E0 /* Reset Source: CORER */
8412 #define PRT_SWT_SCBI_BI_S 0
8413 #define PRT_SWT_SCBI_BI_M MAKEMASK(0x1FFFFFF, 0)
8414 #define PRT_SWT_SCCRL 0x00204200 /* Reset Source: CORER */
8415 #define PRT_SWT_SCCRL_MDIPW_S 0
8416 #define PRT_SWT_SCCRL_MDIPW_M BIT(0)
8417 #define PRT_SWT_SCCRL_MDICW_S 1
8418 #define PRT_SWT_SCCRL_MDICW_M BIT(1)
8419 #define PRT_SWT_SCCRL_BDIPW_S 2
8420 #define PRT_SWT_SCCRL_BDIPW_M BIT(2)
8421 #define PRT_SWT_SCCRL_BDICW_S 3
8422 #define PRT_SWT_SCCRL_BDICW_M BIT(3)
8423 #define PRT_SWT_SCCRL_INTERVAL_S 8
8424 #define PRT_SWT_SCCRL_INTERVAL_M MAKEMASK(0xFFFFF, 8)
8425 #define PRT_TCTUPR(_i) (0x00040840 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8426 #define PRT_TCTUPR_MAX_INDEX 31
8427 #define PRT_TCTUPR_UP0_S 0
8428 #define PRT_TCTUPR_UP0_M MAKEMASK(0x7, 0)
8429 #define PRT_TCTUPR_UP1_S 4
8430 #define PRT_TCTUPR_UP1_M MAKEMASK(0x7, 4)
8431 #define PRT_TCTUPR_UP2_S 8
8432 #define PRT_TCTUPR_UP2_M MAKEMASK(0x7, 8)
8433 #define PRT_TCTUPR_UP3_S 12
8434 #define PRT_TCTUPR_UP3_M MAKEMASK(0x7, 12)
8435 #define PRT_TCTUPR_UP4_S 16
8436 #define PRT_TCTUPR_UP4_M MAKEMASK(0x7, 16)
8437 #define PRT_TCTUPR_UP5_S 20
8438 #define PRT_TCTUPR_UP5_M MAKEMASK(0x7, 20)
8439 #define PRT_TCTUPR_UP6_S 24
8440 #define PRT_TCTUPR_UP6_M MAKEMASK(0x7, 24)
8441 #define PRT_TCTUPR_UP7_S 28
8442 #define PRT_TCTUPR_UP7_M MAKEMASK(0x7, 28)
8443 #define GLHH_ART_CTL 0x000A41D4 /* Reset Source: POR */
8444 #define GLHH_ART_CTL_ACTIVE_S 0
8445 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
8446 #define GLHH_ART_CTL_TIME_OUT1_S 1
8447 #define GLHH_ART_CTL_TIME_OUT1_M BIT(1)
8448 #define GLHH_ART_CTL_TIME_OUT2_S 2
8449 #define GLHH_ART_CTL_TIME_OUT2_M BIT(2)
8450 #define GLHH_ART_CTL_RESET_HH_S 31
8451 #define GLHH_ART_CTL_RESET_HH_M BIT(31)
8452 #define GLHH_ART_DATA 0x000A41E0 /* Reset Source: POR */
8453 #define GLHH_ART_DATA_AGENT_TYPE_S 0
8454 #define GLHH_ART_DATA_AGENT_TYPE_M MAKEMASK(0x7, 0)
8455 #define GLHH_ART_DATA_SYNC_TYPE_S 3
8456 #define GLHH_ART_DATA_SYNC_TYPE_M BIT(3)
8457 #define GLHH_ART_DATA_MAX_DELAY_S 4
8458 #define GLHH_ART_DATA_MAX_DELAY_M MAKEMASK(0xF, 4)
8459 #define GLHH_ART_DATA_TIME_BASE_S 8
8460 #define GLHH_ART_DATA_TIME_BASE_M MAKEMASK(0xF, 8)
8461 #define GLHH_ART_DATA_RSV_DATA_S 12
8462 #define GLHH_ART_DATA_RSV_DATA_M MAKEMASK(0xFFFFF, 12)
8463 #define GLHH_ART_TIME_H 0x000A41D8 /* Reset Source: POR */
8464 #define GLHH_ART_TIME_H_ART_TIME_H_S 0
8465 #define GLHH_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8466 #define GLHH_ART_TIME_L 0x000A41DC /* Reset Source: POR */
8467 #define GLHH_ART_TIME_L_ART_TIME_L_S 0
8468 #define GLHH_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8469 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8470 #define GLTSYN_AUX_IN_0_MAX_INDEX 1
8471 #define GLTSYN_AUX_IN_0_EVNTLVL_S 0
8472 #define GLTSYN_AUX_IN_0_EVNTLVL_M MAKEMASK(0x3, 0)
8473 #define GLTSYN_AUX_IN_0_INT_ENA_S 4
8474 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
8475 #define GLTSYN_AUX_IN_1(_i) (0x000889E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8476 #define GLTSYN_AUX_IN_1_MAX_INDEX 1
8477 #define GLTSYN_AUX_IN_1_EVNTLVL_S 0
8478 #define GLTSYN_AUX_IN_1_EVNTLVL_M MAKEMASK(0x3, 0)
8479 #define GLTSYN_AUX_IN_1_INT_ENA_S 4
8480 #define GLTSYN_AUX_IN_1_INT_ENA_M BIT(4)
8481 #define GLTSYN_AUX_IN_2(_i) (0x000889E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8482 #define GLTSYN_AUX_IN_2_MAX_INDEX 1
8483 #define GLTSYN_AUX_IN_2_EVNTLVL_S 0
8484 #define GLTSYN_AUX_IN_2_EVNTLVL_M MAKEMASK(0x3, 0)
8485 #define GLTSYN_AUX_IN_2_INT_ENA_S 4
8486 #define GLTSYN_AUX_IN_2_INT_ENA_M BIT(4)
8487 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8488 #define GLTSYN_AUX_OUT_0_MAX_INDEX 1
8489 #define GLTSYN_AUX_OUT_0_OUT_ENA_S 0
8490 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
8491 #define GLTSYN_AUX_OUT_0_OUTMOD_S 1
8492 #define GLTSYN_AUX_OUT_0_OUTMOD_M MAKEMASK(0x3, 1)
8493 #define GLTSYN_AUX_OUT_0_OUTLVL_S 3
8494 #define GLTSYN_AUX_OUT_0_OUTLVL_M BIT(3)
8495 #define GLTSYN_AUX_OUT_0_INT_ENA_S 4
8496 #define GLTSYN_AUX_OUT_0_INT_ENA_M BIT(4)
8497 #define GLTSYN_AUX_OUT_0_PULSEW_S 8
8498 #define GLTSYN_AUX_OUT_0_PULSEW_M MAKEMASK(0xF, 8)
8499 #define GLTSYN_AUX_OUT_1(_i) (0x000889A0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8500 #define GLTSYN_AUX_OUT_1_MAX_INDEX 1
8501 #define GLTSYN_AUX_OUT_1_OUT_ENA_S 0
8502 #define GLTSYN_AUX_OUT_1_OUT_ENA_M BIT(0)
8503 #define GLTSYN_AUX_OUT_1_OUTMOD_S 1
8504 #define GLTSYN_AUX_OUT_1_OUTMOD_M MAKEMASK(0x3, 1)
8505 #define GLTSYN_AUX_OUT_1_OUTLVL_S 3
8506 #define GLTSYN_AUX_OUT_1_OUTLVL_M BIT(3)
8507 #define GLTSYN_AUX_OUT_1_INT_ENA_S 4
8508 #define GLTSYN_AUX_OUT_1_INT_ENA_M BIT(4)
8509 #define GLTSYN_AUX_OUT_1_PULSEW_S 8
8510 #define GLTSYN_AUX_OUT_1_PULSEW_M MAKEMASK(0xF, 8)
8511 #define GLTSYN_AUX_OUT_2(_i) (0x000889A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8512 #define GLTSYN_AUX_OUT_2_MAX_INDEX 1
8513 #define GLTSYN_AUX_OUT_2_OUT_ENA_S 0
8514 #define GLTSYN_AUX_OUT_2_OUT_ENA_M BIT(0)
8515 #define GLTSYN_AUX_OUT_2_OUTMOD_S 1
8516 #define GLTSYN_AUX_OUT_2_OUTMOD_M MAKEMASK(0x3, 1)
8517 #define GLTSYN_AUX_OUT_2_OUTLVL_S 3
8518 #define GLTSYN_AUX_OUT_2_OUTLVL_M BIT(3)
8519 #define GLTSYN_AUX_OUT_2_INT_ENA_S 4
8520 #define GLTSYN_AUX_OUT_2_INT_ENA_M BIT(4)
8521 #define GLTSYN_AUX_OUT_2_PULSEW_S 8
8522 #define GLTSYN_AUX_OUT_2_PULSEW_M MAKEMASK(0xF, 8)
8523 #define GLTSYN_AUX_OUT_3(_i) (0x000889B0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8524 #define GLTSYN_AUX_OUT_3_MAX_INDEX 1
8525 #define GLTSYN_AUX_OUT_3_OUT_ENA_S 0
8526 #define GLTSYN_AUX_OUT_3_OUT_ENA_M BIT(0)
8527 #define GLTSYN_AUX_OUT_3_OUTMOD_S 1
8528 #define GLTSYN_AUX_OUT_3_OUTMOD_M MAKEMASK(0x3, 1)
8529 #define GLTSYN_AUX_OUT_3_OUTLVL_S 3
8530 #define GLTSYN_AUX_OUT_3_OUTLVL_M BIT(3)
8531 #define GLTSYN_AUX_OUT_3_INT_ENA_S 4
8532 #define GLTSYN_AUX_OUT_3_INT_ENA_M BIT(4)
8533 #define GLTSYN_AUX_OUT_3_PULSEW_S 8
8534 #define GLTSYN_AUX_OUT_3_PULSEW_M MAKEMASK(0xF, 8)
8535 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8536 #define GLTSYN_CLKO_0_MAX_INDEX 1
8537 #define GLTSYN_CLKO_0_TSYNCLKO_S 0
8538 #define GLTSYN_CLKO_0_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8539 #define GLTSYN_CLKO_1(_i) (0x000889C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8540 #define GLTSYN_CLKO_1_MAX_INDEX 1
8541 #define GLTSYN_CLKO_1_TSYNCLKO_S 0
8542 #define GLTSYN_CLKO_1_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8543 #define GLTSYN_CLKO_2(_i) (0x000889C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8544 #define GLTSYN_CLKO_2_MAX_INDEX 1
8545 #define GLTSYN_CLKO_2_TSYNCLKO_S 0
8546 #define GLTSYN_CLKO_2_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8547 #define GLTSYN_CLKO_3(_i) (0x000889D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8548 #define GLTSYN_CLKO_3_MAX_INDEX 1
8549 #define GLTSYN_CLKO_3_TSYNCLKO_S 0
8550 #define GLTSYN_CLKO_3_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8551 #define GLTSYN_CMD 0x00088810 /* Reset Source: CORER */
8552 #define GLTSYN_CMD_CMD_S 0
8553 #define GLTSYN_CMD_CMD_M MAKEMASK(0xFF, 0)
8554 #define GLTSYN_CMD_SEL_MASTER_S 8
8555 #define GLTSYN_CMD_SEL_MASTER_M BIT(8)
8556 #define GLTSYN_CMD_SYNC 0x00088814 /* Reset Source: CORER */
8557 #define GLTSYN_CMD_SYNC_SYNC_S 0
8558 #define GLTSYN_CMD_SYNC_SYNC_M MAKEMASK(0x3, 0)
8559 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8560 #define GLTSYN_ENA_MAX_INDEX 1
8561 #define GLTSYN_ENA_TSYN_ENA_S 0
8562 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
8563 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8564 #define GLTSYN_EVNT_H_0_MAX_INDEX 1
8565 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_S 0
8566 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8567 #define GLTSYN_EVNT_H_1(_i) (0x00088980 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8568 #define GLTSYN_EVNT_H_1_MAX_INDEX 1
8569 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_S 0
8570 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8571 #define GLTSYN_EVNT_H_2(_i) (0x00088990 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8572 #define GLTSYN_EVNT_H_2_MAX_INDEX 1
8573 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_S 0
8574 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8575 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8576 #define GLTSYN_EVNT_L_0_MAX_INDEX 1
8577 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_S 0
8578 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8579 #define GLTSYN_EVNT_L_1(_i) (0x00088978 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8580 #define GLTSYN_EVNT_L_1_MAX_INDEX 1
8581 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_S 0
8582 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8583 #define GLTSYN_EVNT_L_2(_i) (0x00088988 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8584 #define GLTSYN_EVNT_L_2_MAX_INDEX 1
8585 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_S 0
8586 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8587 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8588 #define GLTSYN_HHTIME_H_MAX_INDEX 1
8589 #define GLTSYN_HHTIME_H_TSYNEVNT_H_S 0
8590 #define GLTSYN_HHTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8591 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8592 #define GLTSYN_HHTIME_L_MAX_INDEX 1
8593 #define GLTSYN_HHTIME_L_TSYNEVNT_L_S 0
8594 #define GLTSYN_HHTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8595 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8596 #define GLTSYN_INCVAL_H_MAX_INDEX 1
8597 #define GLTSYN_INCVAL_H_INCVAL_H_S 0
8598 #define GLTSYN_INCVAL_H_INCVAL_H_M MAKEMASK(0xFF, 0)
8599 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8600 #define GLTSYN_INCVAL_L_MAX_INDEX 1
8601 #define GLTSYN_INCVAL_L_INCVAL_L_S 0
8602 #define GLTSYN_INCVAL_L_INCVAL_L_M MAKEMASK(0xFFFFFFFF, 0)
8603 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8604 #define GLTSYN_SHADJ_H_MAX_INDEX 1
8605 #define GLTSYN_SHADJ_H_ADJUST_H_S 0
8606 #define GLTSYN_SHADJ_H_ADJUST_H_M MAKEMASK(0xFFFFFFFF, 0)
8607 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8608 #define GLTSYN_SHADJ_L_MAX_INDEX 1
8609 #define GLTSYN_SHADJ_L_ADJUST_L_S 0
8610 #define GLTSYN_SHADJ_L_ADJUST_L_M MAKEMASK(0xFFFFFFFF, 0)
8611 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8612 #define GLTSYN_SHTIME_0_MAX_INDEX 1
8613 #define GLTSYN_SHTIME_0_TSYNTIME_0_S 0
8614 #define GLTSYN_SHTIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8615 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8616 #define GLTSYN_SHTIME_H_MAX_INDEX 1
8617 #define GLTSYN_SHTIME_H_TSYNTIME_H_S 0
8618 #define GLTSYN_SHTIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8619 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8620 #define GLTSYN_SHTIME_L_MAX_INDEX 1
8621 #define GLTSYN_SHTIME_L_TSYNTIME_L_S 0
8622 #define GLTSYN_SHTIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8623 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8624 #define GLTSYN_STAT_MAX_INDEX 1
8625 #define GLTSYN_STAT_EVENT0_S 0
8626 #define GLTSYN_STAT_EVENT0_M BIT(0)
8627 #define GLTSYN_STAT_EVENT1_S 1
8628 #define GLTSYN_STAT_EVENT1_M BIT(1)
8629 #define GLTSYN_STAT_EVENT2_S 2
8630 #define GLTSYN_STAT_EVENT2_M BIT(2)
8631 #define GLTSYN_STAT_TGT0_S 4
8632 #define GLTSYN_STAT_TGT0_M BIT(4)
8633 #define GLTSYN_STAT_TGT1_S 5
8634 #define GLTSYN_STAT_TGT1_M BIT(5)
8635 #define GLTSYN_STAT_TGT2_S 6
8636 #define GLTSYN_STAT_TGT2_M BIT(6)
8637 #define GLTSYN_STAT_TGT3_S 7
8638 #define GLTSYN_STAT_TGT3_M BIT(7)
8639 #define GLTSYN_SYNC_DLAY 0x00088818 /* Reset Source: CORER */
8640 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_S 0
8641 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_M MAKEMASK(0x1F, 0)
8642 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8643 #define GLTSYN_TGT_H_0_MAX_INDEX 1
8644 #define GLTSYN_TGT_H_0_TSYNTGTT_H_S 0
8645 #define GLTSYN_TGT_H_0_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8646 #define GLTSYN_TGT_H_1(_i) (0x00088940 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8647 #define GLTSYN_TGT_H_1_MAX_INDEX 1
8648 #define GLTSYN_TGT_H_1_TSYNTGTT_H_S 0
8649 #define GLTSYN_TGT_H_1_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8650 #define GLTSYN_TGT_H_2(_i) (0x00088950 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8651 #define GLTSYN_TGT_H_2_MAX_INDEX 1
8652 #define GLTSYN_TGT_H_2_TSYNTGTT_H_S 0
8653 #define GLTSYN_TGT_H_2_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8654 #define GLTSYN_TGT_H_3(_i) (0x00088960 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8655 #define GLTSYN_TGT_H_3_MAX_INDEX 1
8656 #define GLTSYN_TGT_H_3_TSYNTGTT_H_S 0
8657 #define GLTSYN_TGT_H_3_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8658 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8659 #define GLTSYN_TGT_L_0_MAX_INDEX 1
8660 #define GLTSYN_TGT_L_0_TSYNTGTT_L_S 0
8661 #define GLTSYN_TGT_L_0_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8662 #define GLTSYN_TGT_L_1(_i) (0x00088938 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8663 #define GLTSYN_TGT_L_1_MAX_INDEX 1
8664 #define GLTSYN_TGT_L_1_TSYNTGTT_L_S 0
8665 #define GLTSYN_TGT_L_1_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8666 #define GLTSYN_TGT_L_2(_i) (0x00088948 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8667 #define GLTSYN_TGT_L_2_MAX_INDEX 1
8668 #define GLTSYN_TGT_L_2_TSYNTGTT_L_S 0
8669 #define GLTSYN_TGT_L_2_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8670 #define GLTSYN_TGT_L_3(_i) (0x00088958 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8671 #define GLTSYN_TGT_L_3_MAX_INDEX 1
8672 #define GLTSYN_TGT_L_3_TSYNTGTT_L_S 0
8673 #define GLTSYN_TGT_L_3_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8674 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8675 #define GLTSYN_TIME_0_MAX_INDEX 1
8676 #define GLTSYN_TIME_0_TSYNTIME_0_S 0
8677 #define GLTSYN_TIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8678 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8679 #define GLTSYN_TIME_H_MAX_INDEX 1
8680 #define GLTSYN_TIME_H_TSYNTIME_H_S 0
8681 #define GLTSYN_TIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8682 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8683 #define GLTSYN_TIME_L_MAX_INDEX 1
8684 #define GLTSYN_TIME_L_TSYNTIME_L_S 0
8685 #define GLTSYN_TIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8686 #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */
8687 #define PFHH_SEM_BUSY_S 0
8688 #define PFHH_SEM_BUSY_M BIT(0)
8689 #define PFHH_SEM_PF_OWNER_S 4
8690 #define PFHH_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8691 #define PFTSYN_SEM 0x00088880 /* Reset Source: PFR */
8692 #define PFTSYN_SEM_BUSY_S 0
8693 #define PFTSYN_SEM_BUSY_M BIT(0)
8694 #define PFTSYN_SEM_PF_OWNER_S 4
8695 #define PFTSYN_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8696 #define GLPE_TSCD_FLR(_i) (0x0051E24C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
8697 #define GLPE_TSCD_FLR_MAX_INDEX 3
8698 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S 0
8699 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M MAKEMASK(0x3, 0)
8700 #define GLPE_TSCD_FLR_PORT_S 2
8701 #define GLPE_TSCD_FLR_PORT_M MAKEMASK(0x7, 2)
8702 #define GLPE_TSCD_FLR_PF_NUM_S 5
8703 #define GLPE_TSCD_FLR_PF_NUM_M MAKEMASK(0x7, 5)
8704 #define GLPE_TSCD_FLR_VM_VF_TYPE_S 8
8705 #define GLPE_TSCD_FLR_VM_VF_TYPE_M MAKEMASK(0x3, 8)
8706 #define GLPE_TSCD_FLR_VM_VF_NUM_S 16
8707 #define GLPE_TSCD_FLR_VM_VF_NUM_M MAKEMASK(0x3FF, 16)
8708 #define GLPE_TSCD_FLR_VLD_S 31
8709 #define GLPE_TSCD_FLR_VLD_M BIT(31)
8710 #define GLPE_TSCD_PEPM 0x0051E228 /* Reset Source: CORER */
8711 #define GLPE_TSCD_PEPM_MDQ_CREDITS_S 0
8712 #define GLPE_TSCD_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
8713 #define PF_VIRT_VSTATUS 0x0009E680 /* Reset Source: PFR */
8714 #define PF_VIRT_VSTATUS_NUM_VFS_S 0
8715 #define PF_VIRT_VSTATUS_NUM_VFS_M MAKEMASK(0xFF, 0)
8716 #define PF_VIRT_VSTATUS_TOTAL_VFS_S 8
8717 #define PF_VIRT_VSTATUS_TOTAL_VFS_M MAKEMASK(0xFF, 8)
8718 #define PF_VIRT_VSTATUS_IOV_ACTIVE_S 16
8719 #define PF_VIRT_VSTATUS_IOV_ACTIVE_M BIT(16)
8720 #define PF_VT_PFALLOC 0x001D2480 /* Reset Source: CORER */
8721 #define PF_VT_PFALLOC_FIRSTVF_S 0
8722 #define PF_VT_PFALLOC_FIRSTVF_M MAKEMASK(0xFF, 0)
8723 #define PF_VT_PFALLOC_LASTVF_S 8
8724 #define PF_VT_PFALLOC_LASTVF_M MAKEMASK(0xFF, 8)
8725 #define PF_VT_PFALLOC_VALID_S 31
8726 #define PF_VT_PFALLOC_VALID_M BIT(31)
8727 #define PF_VT_PFALLOC_HIF 0x0009DD80 /* Reset Source: PCIR */
8728 #define PF_VT_PFALLOC_HIF_FIRSTVF_S 0
8729 #define PF_VT_PFALLOC_HIF_FIRSTVF_M MAKEMASK(0xFF, 0)
8730 #define PF_VT_PFALLOC_HIF_LASTVF_S 8
8731 #define PF_VT_PFALLOC_HIF_LASTVF_M MAKEMASK(0xFF, 8)
8732 #define PF_VT_PFALLOC_HIF_VALID_S 31
8733 #define PF_VT_PFALLOC_HIF_VALID_M BIT(31)
8734 #define PF_VT_PFALLOC_PCIE 0x000BE080 /* Reset Source: PCIR */
8735 #define PF_VT_PFALLOC_PCIE_FIRSTVF_S 0
8736 #define PF_VT_PFALLOC_PCIE_FIRSTVF_M MAKEMASK(0xFF, 0)
8737 #define PF_VT_PFALLOC_PCIE_LASTVF_S 8
8738 #define PF_VT_PFALLOC_PCIE_LASTVF_M MAKEMASK(0xFF, 8)
8739 #define PF_VT_PFALLOC_PCIE_VALID_S 31
8740 #define PF_VT_PFALLOC_PCIE_VALID_M BIT(31)
8741 #define VSI_L2TAGSTXVALID(_VSI) (0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8742 #define VSI_L2TAGSTXVALID_MAX_INDEX 767
8743 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S 0
8744 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M MAKEMASK(0x7, 0)
8745 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_S 3
8746 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_M BIT(3)
8747 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_S 4
8748 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_M MAKEMASK(0x7, 4)
8749 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_S 7
8750 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_M BIT(7)
8751 #define VSI_L2TAGSTXVALID_TIR0INSERTID_S 16
8752 #define VSI_L2TAGSTXVALID_TIR0INSERTID_M MAKEMASK(0x7, 16)
8753 #define VSI_L2TAGSTXVALID_TIR0_INSERT_S 19
8754 #define VSI_L2TAGSTXVALID_TIR0_INSERT_M BIT(19)
8755 #define VSI_L2TAGSTXVALID_TIR1INSERTID_S 20
8756 #define VSI_L2TAGSTXVALID_TIR1INSERTID_M MAKEMASK(0x7, 20)
8757 #define VSI_L2TAGSTXVALID_TIR1_INSERT_S 23
8758 #define VSI_L2TAGSTXVALID_TIR1_INSERT_M BIT(23)
8759 #define VSI_L2TAGSTXVALID_TIR2INSERTID_S 24
8760 #define VSI_L2TAGSTXVALID_TIR2INSERTID_M MAKEMASK(0x7, 24)
8761 #define VSI_L2TAGSTXVALID_TIR2_INSERT_S 27
8762 #define VSI_L2TAGSTXVALID_TIR2_INSERT_M BIT(27)
8763 #define VSI_PASID(_VSI) (0x0009C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8764 #define VSI_PASID_MAX_INDEX 767
8765 #define VSI_PASID_PASID_S 0
8766 #define VSI_PASID_PASID_M MAKEMASK(0xFFFFF, 0)
8767 #define VSI_PASID_EN_S 31
8768 #define VSI_PASID_EN_M BIT(31)
8769 #define VSI_RUPR(_VSI) (0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8770 #define VSI_RUPR_MAX_INDEX 767
8771 #define VSI_RUPR_UP0_S 0
8772 #define VSI_RUPR_UP0_M MAKEMASK(0x7, 0)
8773 #define VSI_RUPR_UP1_S 3
8774 #define VSI_RUPR_UP1_M MAKEMASK(0x7, 3)
8775 #define VSI_RUPR_UP2_S 6
8776 #define VSI_RUPR_UP2_M MAKEMASK(0x7, 6)
8777 #define VSI_RUPR_UP3_S 9
8778 #define VSI_RUPR_UP3_M MAKEMASK(0x7, 9)
8779 #define VSI_RUPR_UP4_S 12
8780 #define VSI_RUPR_UP4_M MAKEMASK(0x7, 12)
8781 #define VSI_RUPR_UP5_S 15
8782 #define VSI_RUPR_UP5_M MAKEMASK(0x7, 15)
8783 #define VSI_RUPR_UP6_S 18
8784 #define VSI_RUPR_UP6_M MAKEMASK(0x7, 18)
8785 #define VSI_RUPR_UP7_S 21
8786 #define VSI_RUPR_UP7_M MAKEMASK(0x7, 21)
8787 #define VSI_RXSWCTRL(_VSI) (0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8788 #define VSI_RXSWCTRL_MAX_INDEX 767
8789 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_S 8
8790 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M BIT(8)
8791 #define VSI_RXSWCTRL_PRUNEENABLE_S 9
8792 #define VSI_RXSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 9)
8793 #define VSI_RXSWCTRL_SRCPRUNEENABLE_S 13
8794 #define VSI_RXSWCTRL_SRCPRUNEENABLE_M BIT(13)
8795 #define VSI_SRCSWCTRL(_VSI) (0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8796 #define VSI_SRCSWCTRL_MAX_INDEX 767
8797 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S 0
8798 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M BIT(0)
8799 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_S 1
8800 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_M BIT(1)
8801 #define VSI_SRCSWCTRL_LANENABLE_S 2
8802 #define VSI_SRCSWCTRL_LANENABLE_M BIT(2)
8803 #define VSI_SRCSWCTRL_MACAS_S 3
8804 #define VSI_SRCSWCTRL_MACAS_M BIT(3)
8805 #define VSI_SRCSWCTRL_PRUNEENABLE_S 4
8806 #define VSI_SRCSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 4)
8807 #define VSI_SWITCHID(_VSI) (0x00215000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8808 #define VSI_SWITCHID_MAX_INDEX 767
8809 #define VSI_SWITCHID_SWITCHID_S 0
8810 #define VSI_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8811 #define VSI_SWT_MIREG(_VSI) (0x00207000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8812 #define VSI_SWT_MIREG_MAX_INDEX 767
8813 #define VSI_SWT_MIREG_MIRRULE_S 0
8814 #define VSI_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8815 #define VSI_SWT_MIREG_MIRENA_S 7
8816 #define VSI_SWT_MIREG_MIRENA_M BIT(7)
8817 #define VSI_SWT_MIRIG(_VSI) (0x00208000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8818 #define VSI_SWT_MIRIG_MAX_INDEX 767
8819 #define VSI_SWT_MIRIG_MIRRULE_S 0
8820 #define VSI_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8821 #define VSI_SWT_MIRIG_MIRENA_S 7
8822 #define VSI_SWT_MIRIG_MIRENA_M BIT(7)
8823 #define VSI_TAIR(_VSI) (0x00044000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8824 #define VSI_TAIR_MAX_INDEX 767
8825 #define VSI_TAIR_PORT_TAG_ID_S 0
8826 #define VSI_TAIR_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8827 #define VSI_TAR(_VSI) (0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8828 #define VSI_TAR_MAX_INDEX 767
8829 #define VSI_TAR_ACCEPTTAGGED_S 0
8830 #define VSI_TAR_ACCEPTTAGGED_M MAKEMASK(0x3FF, 0)
8831 #define VSI_TAR_ACCEPTUNTAGGED_S 16
8832 #define VSI_TAR_ACCEPTUNTAGGED_M MAKEMASK(0x3FF, 16)
8833 #define VSI_TIR_0(_VSI) (0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8834 #define VSI_TIR_0_MAX_INDEX 767
8835 #define VSI_TIR_0_PORT_TAG_ID_S 0
8836 #define VSI_TIR_0_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8837 #define VSI_TIR_1(_VSI) (0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8838 #define VSI_TIR_1_MAX_INDEX 767
8839 #define VSI_TIR_1_PORT_TAG_ID_S 0
8840 #define VSI_TIR_1_PORT_TAG_ID_M MAKEMASK(0xFFFFFFFF, 0)
8841 #define VSI_TIR_2(_VSI) (0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8842 #define VSI_TIR_2_MAX_INDEX 767
8843 #define VSI_TIR_2_PORT_TAG_ID_S 0
8844 #define VSI_TIR_2_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8845 #define VSI_TSR(_VSI) (0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8846 #define VSI_TSR_MAX_INDEX 767
8847 #define VSI_TSR_STRIPTAG_S 0
8848 #define VSI_TSR_STRIPTAG_M MAKEMASK(0x3FF, 0)
8849 #define VSI_TSR_SHOWTAG_S 10
8850 #define VSI_TSR_SHOWTAG_M MAKEMASK(0x3FF, 10)
8851 #define VSI_TSR_SHOWPRIONLY_S 20
8852 #define VSI_TSR_SHOWPRIONLY_M MAKEMASK(0x3FF, 20)
8853 #define VSI_TUPIOM(_VSI) (0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8854 #define VSI_TUPIOM_MAX_INDEX 767
8855 #define VSI_TUPIOM_UP0_S 0
8856 #define VSI_TUPIOM_UP0_M MAKEMASK(0x7, 0)
8857 #define VSI_TUPIOM_UP1_S 3
8858 #define VSI_TUPIOM_UP1_M MAKEMASK(0x7, 3)
8859 #define VSI_TUPIOM_UP2_S 6
8860 #define VSI_TUPIOM_UP2_M MAKEMASK(0x7, 6)
8861 #define VSI_TUPIOM_UP3_S 9
8862 #define VSI_TUPIOM_UP3_M MAKEMASK(0x7, 9)
8863 #define VSI_TUPIOM_UP4_S 12
8864 #define VSI_TUPIOM_UP4_M MAKEMASK(0x7, 12)
8865 #define VSI_TUPIOM_UP5_S 15
8866 #define VSI_TUPIOM_UP5_M MAKEMASK(0x7, 15)
8867 #define VSI_TUPIOM_UP6_S 18
8868 #define VSI_TUPIOM_UP6_M MAKEMASK(0x7, 18)
8869 #define VSI_TUPIOM_UP7_S 21
8870 #define VSI_TUPIOM_UP7_M MAKEMASK(0x7, 21)
8871 #define VSI_TUPR(_VSI) (0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8872 #define VSI_TUPR_MAX_INDEX 767
8873 #define VSI_TUPR_UP0_S 0
8874 #define VSI_TUPR_UP0_M MAKEMASK(0x7, 0)
8875 #define VSI_TUPR_UP1_S 3
8876 #define VSI_TUPR_UP1_M MAKEMASK(0x7, 3)
8877 #define VSI_TUPR_UP2_S 6
8878 #define VSI_TUPR_UP2_M MAKEMASK(0x7, 6)
8879 #define VSI_TUPR_UP3_S 9
8880 #define VSI_TUPR_UP3_M MAKEMASK(0x7, 9)
8881 #define VSI_TUPR_UP4_S 12
8882 #define VSI_TUPR_UP4_M MAKEMASK(0x7, 12)
8883 #define VSI_TUPR_UP5_S 15
8884 #define VSI_TUPR_UP5_M MAKEMASK(0x7, 15)
8885 #define VSI_TUPR_UP6_S 18
8886 #define VSI_TUPR_UP6_M MAKEMASK(0x7, 18)
8887 #define VSI_TUPR_UP7_S 21
8888 #define VSI_TUPR_UP7_M MAKEMASK(0x7, 21)
8889 #define VSI_VSI2F(_VSI) (0x001D0000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8890 #define VSI_VSI2F_MAX_INDEX 767
8891 #define VSI_VSI2F_VFVMNUMBER_S 0
8892 #define VSI_VSI2F_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
8893 #define VSI_VSI2F_FUNCTIONTYPE_S 10
8894 #define VSI_VSI2F_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
8895 #define VSI_VSI2F_PFNUMBER_S 12
8896 #define VSI_VSI2F_PFNUMBER_M MAKEMASK(0x7, 12)
8897 #define VSI_VSI2F_BUFFERNUMBER_S 16
8898 #define VSI_VSI2F_BUFFERNUMBER_M MAKEMASK(0x7, 16)
8899 #define VSI_VSI2F_VSI_NUMBER_S 20
8900 #define VSI_VSI2F_VSI_NUMBER_M MAKEMASK(0x3FF, 20)
8901 #define VSI_VSI2F_VSI_ENABLE_S 31
8902 #define VSI_VSI2F_VSI_ENABLE_M BIT(31)
8903 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8904 #define VSIQF_FD_CNT_MAX_INDEX 767
8905 #define VSIQF_FD_CNT_FD_GCNT_S 0
8906 #define VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0)
8907 #define VSIQF_FD_CNT_FD_BCNT_S 16
8908 #define VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16)
8909 #define VSIQF_FD_CTL1(_VSI) (0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8910 #define VSIQF_FD_CTL1_MAX_INDEX 767
8911 #define VSIQF_FD_CTL1_FLT_ENA_S 0
8912 #define VSIQF_FD_CTL1_FLT_ENA_M BIT(0)
8913 #define VSIQF_FD_CTL1_CFG_ENA_S 1
8914 #define VSIQF_FD_CTL1_CFG_ENA_M BIT(1)
8915 #define VSIQF_FD_CTL1_EVICT_ENA_S 2
8916 #define VSIQF_FD_CTL1_EVICT_ENA_M BIT(2)
8917 #define VSIQF_FD_DFLT(_VSI) (0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8918 #define VSIQF_FD_DFLT_MAX_INDEX 767
8919 #define VSIQF_FD_DFLT_DEFLT_QINDX_S 0
8920 #define VSIQF_FD_DFLT_DEFLT_QINDX_M MAKEMASK(0x7FF, 0)
8921 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_S 12
8922 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_M MAKEMASK(0x7, 12)
8923 #define VSIQF_FD_DFLT_COMP_QINDX_S 16
8924 #define VSIQF_FD_DFLT_COMP_QINDX_M MAKEMASK(0x7FF, 16)
8925 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_S 28
8926 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_M MAKEMASK(0x7, 28)
8927 #define VSIQF_FD_DFLT_DEFLT_DROP_S 31
8928 #define VSIQF_FD_DFLT_DEFLT_DROP_M BIT(31)
8929 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8930 #define VSIQF_FD_SIZE_MAX_INDEX 767
8931 #define VSIQF_FD_SIZE_FD_GSIZE_S 0
8932 #define VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0)
8933 #define VSIQF_FD_SIZE_FD_BSIZE_S 16
8934 #define VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16)
8935 #define VSIQF_HASH_CTL(_VSI) (0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8936 #define VSIQF_HASH_CTL_MAX_INDEX 767
8937 #define VSIQF_HASH_CTL_HASH_LUT_SEL_S 0
8938 #define VSIQF_HASH_CTL_HASH_LUT_SEL_M MAKEMASK(0x3, 0)
8939 #define VSIQF_HASH_CTL_GLOB_LUT_S 2
8940 #define VSIQF_HASH_CTL_GLOB_LUT_M MAKEMASK(0xF, 2)
8941 #define VSIQF_HASH_CTL_HASH_SCHEME_S 6
8942 #define VSIQF_HASH_CTL_HASH_SCHEME_M MAKEMASK(0x3, 6)
8943 #define VSIQF_HASH_CTL_TC_OVER_SEL_S 8
8944 #define VSIQF_HASH_CTL_TC_OVER_SEL_M MAKEMASK(0x1F, 8)
8945 #define VSIQF_HASH_CTL_TC_OVER_ENA_S 15
8946 #define VSIQF_HASH_CTL_TC_OVER_ENA_M BIT(15)
8947 #define VSIQF_HKEY(_i, _VSI) (0x00400000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...12, _VSI=0...767 */ /* Reset Source: PFR */
8948 #define VSIQF_HKEY_MAX_INDEX 12
8949 #define VSIQF_HKEY_KEY_0_S 0
8950 #define VSIQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
8951 #define VSIQF_HKEY_KEY_1_S 8
8952 #define VSIQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
8953 #define VSIQF_HKEY_KEY_2_S 16
8954 #define VSIQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
8955 #define VSIQF_HKEY_KEY_3_S 24
8956 #define VSIQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
8957 #define VSIQF_HLUT(_i, _VSI) (0x00420000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...15, _VSI=0...767 */ /* Reset Source: PFR */
8958 #define VSIQF_HLUT_MAX_INDEX 15
8959 #define VSIQF_HLUT_LUT0_S 0
8960 #define VSIQF_HLUT_LUT0_M MAKEMASK(0xF, 0)
8961 #define VSIQF_HLUT_LUT1_S 8
8962 #define VSIQF_HLUT_LUT1_M MAKEMASK(0xF, 8)
8963 #define VSIQF_HLUT_LUT2_S 16
8964 #define VSIQF_HLUT_LUT2_M MAKEMASK(0xF, 16)
8965 #define VSIQF_HLUT_LUT3_S 24
8966 #define VSIQF_HLUT_LUT3_M MAKEMASK(0xF, 24)
8967 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8968 #define VSIQF_PE_CTL1_MAX_INDEX 767
8969 #define VSIQF_PE_CTL1_PE_FLTENA_S 0
8970 #define VSIQF_PE_CTL1_PE_FLTENA_M BIT(0)
8971 #define VSIQF_TC_REGION(_i, _VSI) (0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: CORER */
8972 #define VSIQF_TC_REGION_MAX_INDEX 3
8973 #define VSIQF_TC_REGION_TC_BASE0_S 0
8974 #define VSIQF_TC_REGION_TC_BASE0_M MAKEMASK(0x7FF, 0)
8975 #define VSIQF_TC_REGION_TC_SIZE0_S 11
8976 #define VSIQF_TC_REGION_TC_SIZE0_M MAKEMASK(0xF, 11)
8977 #define VSIQF_TC_REGION_TC_BASE1_S 16
8978 #define VSIQF_TC_REGION_TC_BASE1_M MAKEMASK(0x7FF, 16)
8979 #define VSIQF_TC_REGION_TC_SIZE1_S 27
8980 #define VSIQF_TC_REGION_TC_SIZE1_M MAKEMASK(0xF, 27)
8981 #define GLPM_WUMC 0x0009DEE4 /* Reset Source: POR */
8982 #define GLPM_WUMC_MNG_WU_PF_S 16
8983 #define GLPM_WUMC_MNG_WU_PF_M MAKEMASK(0xFF, 16)
8984 #define PFPM_APM 0x000B8080 /* Reset Source: POR */
8985 #define PFPM_APM_APME_S 0
8986 #define PFPM_APM_APME_M BIT(0)
8987 #define PFPM_WUC 0x0009DC80 /* Reset Source: POR */
8988 #define PFPM_WUC_EN_APM_D0_S 5
8989 #define PFPM_WUC_EN_APM_D0_M BIT(5)
8990 #define PFPM_WUFC 0x0009DC00 /* Reset Source: POR */
8991 #define PFPM_WUFC_LNKC_S 0
8992 #define PFPM_WUFC_LNKC_M BIT(0)
8993 #define PFPM_WUFC_MAG_S 1
8994 #define PFPM_WUFC_MAG_M BIT(1)
8995 #define PFPM_WUFC_MNG_S 3
8996 #define PFPM_WUFC_MNG_M BIT(3)
8997 #define PFPM_WUFC_FLX0_ACT_S 4
8998 #define PFPM_WUFC_FLX0_ACT_M BIT(4)
8999 #define PFPM_WUFC_FLX1_ACT_S 5
9000 #define PFPM_WUFC_FLX1_ACT_M BIT(5)
9001 #define PFPM_WUFC_FLX2_ACT_S 6
9002 #define PFPM_WUFC_FLX2_ACT_M BIT(6)
9003 #define PFPM_WUFC_FLX3_ACT_S 7
9004 #define PFPM_WUFC_FLX3_ACT_M BIT(7)
9005 #define PFPM_WUFC_FLX4_ACT_S 8
9006 #define PFPM_WUFC_FLX4_ACT_M BIT(8)
9007 #define PFPM_WUFC_FLX5_ACT_S 9
9008 #define PFPM_WUFC_FLX5_ACT_M BIT(9)
9009 #define PFPM_WUFC_FLX6_ACT_S 10
9010 #define PFPM_WUFC_FLX6_ACT_M BIT(10)
9011 #define PFPM_WUFC_FLX7_ACT_S 11
9012 #define PFPM_WUFC_FLX7_ACT_M BIT(11)
9013 #define PFPM_WUFC_FLX0_S 16
9014 #define PFPM_WUFC_FLX0_M BIT(16)
9015 #define PFPM_WUFC_FLX1_S 17
9016 #define PFPM_WUFC_FLX1_M BIT(17)
9017 #define PFPM_WUFC_FLX2_S 18
9018 #define PFPM_WUFC_FLX2_M BIT(18)
9019 #define PFPM_WUFC_FLX3_S 19
9020 #define PFPM_WUFC_FLX3_M BIT(19)
9021 #define PFPM_WUFC_FLX4_S 20
9022 #define PFPM_WUFC_FLX4_M BIT(20)
9023 #define PFPM_WUFC_FLX5_S 21
9024 #define PFPM_WUFC_FLX5_M BIT(21)
9025 #define PFPM_WUFC_FLX6_S 22
9026 #define PFPM_WUFC_FLX6_M BIT(22)
9027 #define PFPM_WUFC_FLX7_S 23
9028 #define PFPM_WUFC_FLX7_M BIT(23)
9029 #define PFPM_WUFC_FW_RST_WK_S 31
9030 #define PFPM_WUFC_FW_RST_WK_M BIT(31)
9031 #define PFPM_WUS 0x0009DB80 /* Reset Source: POR */
9032 #define PFPM_WUS_LNKC_S 0
9033 #define PFPM_WUS_LNKC_M BIT(0)
9034 #define PFPM_WUS_MAG_S 1
9035 #define PFPM_WUS_MAG_M BIT(1)
9036 #define PFPM_WUS_PME_STATUS_S 2
9037 #define PFPM_WUS_PME_STATUS_M BIT(2)
9038 #define PFPM_WUS_MNG_S 3
9039 #define PFPM_WUS_MNG_M BIT(3)
9040 #define PFPM_WUS_FLX0_S 16
9041 #define PFPM_WUS_FLX0_M BIT(16)
9042 #define PFPM_WUS_FLX1_S 17
9043 #define PFPM_WUS_FLX1_M BIT(17)
9044 #define PFPM_WUS_FLX2_S 18
9045 #define PFPM_WUS_FLX2_M BIT(18)
9046 #define PFPM_WUS_FLX3_S 19
9047 #define PFPM_WUS_FLX3_M BIT(19)
9048 #define PFPM_WUS_FLX4_S 20
9049 #define PFPM_WUS_FLX4_M BIT(20)
9050 #define PFPM_WUS_FLX5_S 21
9051 #define PFPM_WUS_FLX5_M BIT(21)
9052 #define PFPM_WUS_FLX6_S 22
9053 #define PFPM_WUS_FLX6_M BIT(22)
9054 #define PFPM_WUS_FLX7_S 23
9055 #define PFPM_WUS_FLX7_M BIT(23)
9056 #define PFPM_WUS_FW_RST_WK_S 31
9057 #define PFPM_WUS_FW_RST_WK_M BIT(31)
9058 #define PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9059 #define PRTPM_SAH_MAX_INDEX 3
9060 #define PRTPM_SAH_PFPM_SAH_S 0
9061 #define PRTPM_SAH_PFPM_SAH_M MAKEMASK(0xFFFF, 0)
9062 #define PRTPM_SAH_PF_NUM_S 26
9063 #define PRTPM_SAH_PF_NUM_M MAKEMASK(0xF, 26)
9064 #define PRTPM_SAH_MC_MAG_EN_S 30
9065 #define PRTPM_SAH_MC_MAG_EN_M BIT(30)
9066 #define PRTPM_SAH_AV_S 31
9067 #define PRTPM_SAH_AV_M BIT(31)
9068 #define PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9069 #define PRTPM_SAL_MAX_INDEX 3
9070 #define PRTPM_SAL_PFPM_SAL_S 0
9071 #define PRTPM_SAL_PFPM_SAL_M MAKEMASK(0xFFFFFFFF, 0)
9072 #define GLPE_CQM_FUNC_INVALIDATE 0x00503300 /* Reset Source: CORER */
9073 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_S 0
9074 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_M MAKEMASK(0x7, 0)
9075 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_S 3
9076 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_M MAKEMASK(0x3FF, 3)
9077 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_S 13
9078 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M MAKEMASK(0x3, 13)
9079 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_S 31
9080 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M BIT(31)
9081 #define VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */
9082 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
9083 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9084 #define GLTSYN_HH_DLAY 0x0008881C /* Reset Source: CORER */
9085 #define GLTSYN_HH_DLAY_SYNC_DELAY_S 0
9086 #define GLTSYN_HH_DLAY_SYNC_DELAY_M MAKEMASK(0xF, 0)
9087 #define VF_MBX_ARQBAH1 0x00006000 /* Reset Source: CORER */
9088 #define VF_MBX_ARQBAH1_ARQBAH_S 0
9089 #define VF_MBX_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9090 #define VF_MBX_ARQBAL1 0x00006C00 /* Reset Source: CORER */
9091 #define VF_MBX_ARQBAL1_ARQBAL_LSB_S 0
9092 #define VF_MBX_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9093 #define VF_MBX_ARQBAL1_ARQBAL_S 6
9094 #define VF_MBX_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9095 #define VF_MBX_ARQH1 0x00007400 /* Reset Source: CORER */
9096 #define VF_MBX_ARQH1_ARQH_S 0
9097 #define VF_MBX_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9098 #define VF_MBX_ARQLEN1 0x00008000 /* Reset Source: PFR */
9099 #define VF_MBX_ARQLEN1_ARQLEN_S 0
9100 #define VF_MBX_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9101 #define VF_MBX_ARQLEN1_ARQVFE_S 28
9102 #define VF_MBX_ARQLEN1_ARQVFE_M BIT(28)
9103 #define VF_MBX_ARQLEN1_ARQOVFL_S 29
9104 #define VF_MBX_ARQLEN1_ARQOVFL_M BIT(29)
9105 #define VF_MBX_ARQLEN1_ARQCRIT_S 30
9106 #define VF_MBX_ARQLEN1_ARQCRIT_M BIT(30)
9107 #define VF_MBX_ARQLEN1_ARQENABLE_S 31
9108 #define VF_MBX_ARQLEN1_ARQENABLE_M BIT(31)
9109 #define VF_MBX_ARQT1 0x00007000 /* Reset Source: CORER */
9110 #define VF_MBX_ARQT1_ARQT_S 0
9111 #define VF_MBX_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9112 #define VF_MBX_ATQBAH1 0x00007800 /* Reset Source: CORER */
9113 #define VF_MBX_ATQBAH1_ATQBAH_S 0
9114 #define VF_MBX_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9115 #define VF_MBX_ATQBAL1 0x00007C00 /* Reset Source: CORER */
9116 #define VF_MBX_ATQBAL1_ATQBAL_S 6
9117 #define VF_MBX_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9118 #define VF_MBX_ATQH1 0x00006400 /* Reset Source: CORER */
9119 #define VF_MBX_ATQH1_ATQH_S 0
9120 #define VF_MBX_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9121 #define VF_MBX_ATQLEN1 0x00006800 /* Reset Source: PFR */
9122 #define VF_MBX_ATQLEN1_ATQLEN_S 0
9123 #define VF_MBX_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9124 #define VF_MBX_ATQLEN1_ATQVFE_S 28
9125 #define VF_MBX_ATQLEN1_ATQVFE_M BIT(28)
9126 #define VF_MBX_ATQLEN1_ATQOVFL_S 29
9127 #define VF_MBX_ATQLEN1_ATQOVFL_M BIT(29)
9128 #define VF_MBX_ATQLEN1_ATQCRIT_S 30
9129 #define VF_MBX_ATQLEN1_ATQCRIT_M BIT(30)
9130 #define VF_MBX_ATQLEN1_ATQENABLE_S 31
9131 #define VF_MBX_ATQLEN1_ATQENABLE_M BIT(31)
9132 #define VF_MBX_ATQT1 0x00008400 /* Reset Source: CORER */
9133 #define VF_MBX_ATQT1_ATQT_S 0
9134 #define VF_MBX_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9135 #define PFPCI_VF_FLUSH_DONE1 0x0000E400 /* Reset Source: PCIR */
9136 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_S 0
9137 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M BIT(0)
9138 #define VFGEN_RSTAT1 0x00008800 /* Reset Source: VFR */
9139 #define VFGEN_RSTAT1_VFR_STATE_S 0
9140 #define VFGEN_RSTAT1_VFR_STATE_M MAKEMASK(0x3, 0)
9141 #define VFINT_DYN_CTL0 0x00005C00 /* Reset Source: CORER */
9142 #define VFINT_DYN_CTL0_INTENA_S 0
9143 #define VFINT_DYN_CTL0_INTENA_M BIT(0)
9144 #define VFINT_DYN_CTL0_CLEARPBA_S 1
9145 #define VFINT_DYN_CTL0_CLEARPBA_M BIT(1)
9146 #define VFINT_DYN_CTL0_SWINT_TRIG_S 2
9147 #define VFINT_DYN_CTL0_SWINT_TRIG_M BIT(2)
9148 #define VFINT_DYN_CTL0_ITR_INDX_S 3
9149 #define VFINT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, 3)
9150 #define VFINT_DYN_CTL0_INTERVAL_S 5
9151 #define VFINT_DYN_CTL0_INTERVAL_M MAKEMASK(0xFFF, 5)
9152 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_S 24
9153 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_M BIT(24)
9154 #define VFINT_DYN_CTL0_SW_ITR_INDX_S 25
9155 #define VFINT_DYN_CTL0_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9156 #define VFINT_DYN_CTL0_WB_ON_ITR_S 30
9157 #define VFINT_DYN_CTL0_WB_ON_ITR_M BIT(30)
9158 #define VFINT_DYN_CTL0_INTENA_MSK_S 31
9159 #define VFINT_DYN_CTL0_INTENA_MSK_M BIT(31)
9160 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9161 #define VFINT_DYN_CTLN_MAX_INDEX 63
9162 #define VFINT_DYN_CTLN_INTENA_S 0
9163 #define VFINT_DYN_CTLN_INTENA_M BIT(0)
9164 #define VFINT_DYN_CTLN_CLEARPBA_S 1
9165 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
9166 #define VFINT_DYN_CTLN_SWINT_TRIG_S 2
9167 #define VFINT_DYN_CTLN_SWINT_TRIG_M BIT(2)
9168 #define VFINT_DYN_CTLN_ITR_INDX_S 3
9169 #define VFINT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, 3)
9170 #define VFINT_DYN_CTLN_INTERVAL_S 5
9171 #define VFINT_DYN_CTLN_INTERVAL_M MAKEMASK(0xFFF, 5)
9172 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_S 24
9173 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(24)
9174 #define VFINT_DYN_CTLN_SW_ITR_INDX_S 25
9175 #define VFINT_DYN_CTLN_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9176 #define VFINT_DYN_CTLN_WB_ON_ITR_S 30
9177 #define VFINT_DYN_CTLN_WB_ON_ITR_M BIT(30)
9178 #define VFINT_DYN_CTLN_INTENA_MSK_S 31
9179 #define VFINT_DYN_CTLN_INTENA_MSK_M BIT(31)
9180 #define VFINT_ITR0(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
9181 #define VFINT_ITR0_MAX_INDEX 2
9182 #define VFINT_ITR0_INTERVAL_S 0
9183 #define VFINT_ITR0_INTERVAL_M MAKEMASK(0xFFF, 0)
9184 #define VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
9185 #define VFINT_ITRN_MAX_INDEX 2
9186 #define VFINT_ITRN_INTERVAL_S 0
9187 #define VFINT_ITRN_INTERVAL_M MAKEMASK(0xFFF, 0)
9188 #define QRX_TAIL1(_QRX) (0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9189 #define QRX_TAIL1_MAX_INDEX 255
9190 #define QRX_TAIL1_TAIL_S 0
9191 #define QRX_TAIL1_TAIL_M MAKEMASK(0x1FFF, 0)
9192 #define QTX_TAIL(_DBQM) (0x00000000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9193 #define QTX_TAIL_MAX_INDEX 255
9194 #define QTX_TAIL_QTX_COMM_DBELL_S 0
9195 #define QTX_TAIL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9196 #define VF_MBX_CPM_ARQBAH1 0x0000F060 /* Reset Source: CORER */
9197 #define VF_MBX_CPM_ARQBAH1_ARQBAH_S 0
9198 #define VF_MBX_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9199 #define VF_MBX_CPM_ARQBAL1 0x0000F050 /* Reset Source: CORER */
9200 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_S 0
9201 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9202 #define VF_MBX_CPM_ARQBAL1_ARQBAL_S 6
9203 #define VF_MBX_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9204 #define VF_MBX_CPM_ARQH1 0x0000F080 /* Reset Source: CORER */
9205 #define VF_MBX_CPM_ARQH1_ARQH_S 0
9206 #define VF_MBX_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9207 #define VF_MBX_CPM_ARQLEN1 0x0000F070 /* Reset Source: PFR */
9208 #define VF_MBX_CPM_ARQLEN1_ARQLEN_S 0
9209 #define VF_MBX_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9210 #define VF_MBX_CPM_ARQLEN1_ARQVFE_S 28
9211 #define VF_MBX_CPM_ARQLEN1_ARQVFE_M BIT(28)
9212 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_S 29
9213 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_M BIT(29)
9214 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_S 30
9215 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_M BIT(30)
9216 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_S 31
9217 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_M BIT(31)
9218 #define VF_MBX_CPM_ARQT1 0x0000F090 /* Reset Source: CORER */
9219 #define VF_MBX_CPM_ARQT1_ARQT_S 0
9220 #define VF_MBX_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9221 #define VF_MBX_CPM_ATQBAH1 0x0000F010 /* Reset Source: CORER */
9222 #define VF_MBX_CPM_ATQBAH1_ATQBAH_S 0
9223 #define VF_MBX_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9224 #define VF_MBX_CPM_ATQBAL1 0x0000F000 /* Reset Source: CORER */
9225 #define VF_MBX_CPM_ATQBAL1_ATQBAL_S 6
9226 #define VF_MBX_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9227 #define VF_MBX_CPM_ATQH1 0x0000F030 /* Reset Source: CORER */
9228 #define VF_MBX_CPM_ATQH1_ATQH_S 0
9229 #define VF_MBX_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9230 #define VF_MBX_CPM_ATQLEN1 0x0000F020 /* Reset Source: PFR */
9231 #define VF_MBX_CPM_ATQLEN1_ATQLEN_S 0
9232 #define VF_MBX_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9233 #define VF_MBX_CPM_ATQLEN1_ATQVFE_S 28
9234 #define VF_MBX_CPM_ATQLEN1_ATQVFE_M BIT(28)
9235 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_S 29
9236 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_M BIT(29)
9237 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_S 30
9238 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_M BIT(30)
9239 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_S 31
9240 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_M BIT(31)
9241 #define VF_MBX_CPM_ATQT1 0x0000F040 /* Reset Source: CORER */
9242 #define VF_MBX_CPM_ATQT1_ATQT_S 0
9243 #define VF_MBX_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9244 #define VF_MBX_HLP_ARQBAH1 0x00020060 /* Reset Source: CORER */
9245 #define VF_MBX_HLP_ARQBAH1_ARQBAH_S 0
9246 #define VF_MBX_HLP_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9247 #define VF_MBX_HLP_ARQBAL1 0x00020050 /* Reset Source: CORER */
9248 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_S 0
9249 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9250 #define VF_MBX_HLP_ARQBAL1_ARQBAL_S 6
9251 #define VF_MBX_HLP_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9252 #define VF_MBX_HLP_ARQH1 0x00020080 /* Reset Source: CORER */
9253 #define VF_MBX_HLP_ARQH1_ARQH_S 0
9254 #define VF_MBX_HLP_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9255 #define VF_MBX_HLP_ARQLEN1 0x00020070 /* Reset Source: PFR */
9256 #define VF_MBX_HLP_ARQLEN1_ARQLEN_S 0
9257 #define VF_MBX_HLP_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9258 #define VF_MBX_HLP_ARQLEN1_ARQVFE_S 28
9259 #define VF_MBX_HLP_ARQLEN1_ARQVFE_M BIT(28)
9260 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_S 29
9261 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_M BIT(29)
9262 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_S 30
9263 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_M BIT(30)
9264 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_S 31
9265 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_M BIT(31)
9266 #define VF_MBX_HLP_ARQT1 0x00020090 /* Reset Source: CORER */
9267 #define VF_MBX_HLP_ARQT1_ARQT_S 0
9268 #define VF_MBX_HLP_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9269 #define VF_MBX_HLP_ATQBAH1 0x00020010 /* Reset Source: CORER */
9270 #define VF_MBX_HLP_ATQBAH1_ATQBAH_S 0
9271 #define VF_MBX_HLP_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9272 #define VF_MBX_HLP_ATQBAL1 0x00020000 /* Reset Source: CORER */
9273 #define VF_MBX_HLP_ATQBAL1_ATQBAL_S 6
9274 #define VF_MBX_HLP_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9275 #define VF_MBX_HLP_ATQH1 0x00020030 /* Reset Source: CORER */
9276 #define VF_MBX_HLP_ATQH1_ATQH_S 0
9277 #define VF_MBX_HLP_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9278 #define VF_MBX_HLP_ATQLEN1 0x00020020 /* Reset Source: PFR */
9279 #define VF_MBX_HLP_ATQLEN1_ATQLEN_S 0
9280 #define VF_MBX_HLP_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9281 #define VF_MBX_HLP_ATQLEN1_ATQVFE_S 28
9282 #define VF_MBX_HLP_ATQLEN1_ATQVFE_M BIT(28)
9283 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_S 29
9284 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_M BIT(29)
9285 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_S 30
9286 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_M BIT(30)
9287 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_S 31
9288 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_M BIT(31)
9289 #define VF_MBX_HLP_ATQT1 0x00020040 /* Reset Source: CORER */
9290 #define VF_MBX_HLP_ATQT1_ATQT_S 0
9291 #define VF_MBX_HLP_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9292 #define VF_MBX_PSM_ARQBAH1 0x00021060 /* Reset Source: CORER */
9293 #define VF_MBX_PSM_ARQBAH1_ARQBAH_S 0
9294 #define VF_MBX_PSM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9295 #define VF_MBX_PSM_ARQBAL1 0x00021050 /* Reset Source: CORER */
9296 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_S 0
9297 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9298 #define VF_MBX_PSM_ARQBAL1_ARQBAL_S 6
9299 #define VF_MBX_PSM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9300 #define VF_MBX_PSM_ARQH1 0x00021080 /* Reset Source: CORER */
9301 #define VF_MBX_PSM_ARQH1_ARQH_S 0
9302 #define VF_MBX_PSM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9303 #define VF_MBX_PSM_ARQLEN1 0x00021070 /* Reset Source: PFR */
9304 #define VF_MBX_PSM_ARQLEN1_ARQLEN_S 0
9305 #define VF_MBX_PSM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9306 #define VF_MBX_PSM_ARQLEN1_ARQVFE_S 28
9307 #define VF_MBX_PSM_ARQLEN1_ARQVFE_M BIT(28)
9308 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_S 29
9309 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_M BIT(29)
9310 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_S 30
9311 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_M BIT(30)
9312 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_S 31
9313 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_M BIT(31)
9314 #define VF_MBX_PSM_ARQT1 0x00021090 /* Reset Source: CORER */
9315 #define VF_MBX_PSM_ARQT1_ARQT_S 0
9316 #define VF_MBX_PSM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9317 #define VF_MBX_PSM_ATQBAH1 0x00021010 /* Reset Source: CORER */
9318 #define VF_MBX_PSM_ATQBAH1_ATQBAH_S 0
9319 #define VF_MBX_PSM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9320 #define VF_MBX_PSM_ATQBAL1 0x00021000 /* Reset Source: CORER */
9321 #define VF_MBX_PSM_ATQBAL1_ATQBAL_S 6
9322 #define VF_MBX_PSM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9323 #define VF_MBX_PSM_ATQH1 0x00021030 /* Reset Source: CORER */
9324 #define VF_MBX_PSM_ATQH1_ATQH_S 0
9325 #define VF_MBX_PSM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9326 #define VF_MBX_PSM_ATQLEN1 0x00021020 /* Reset Source: PFR */
9327 #define VF_MBX_PSM_ATQLEN1_ATQLEN_S 0
9328 #define VF_MBX_PSM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9329 #define VF_MBX_PSM_ATQLEN1_ATQVFE_S 28
9330 #define VF_MBX_PSM_ATQLEN1_ATQVFE_M BIT(28)
9331 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_S 29
9332 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_M BIT(29)
9333 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_S 30
9334 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_M BIT(30)
9335 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_S 31
9336 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_M BIT(31)
9337 #define VF_MBX_PSM_ATQT1 0x00021040 /* Reset Source: CORER */
9338 #define VF_MBX_PSM_ATQT1_ATQT_S 0
9339 #define VF_MBX_PSM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9340 #define VF_SB_CPM_ARQBAH1 0x0000F160 /* Reset Source: CORER */
9341 #define VF_SB_CPM_ARQBAH1_ARQBAH_S 0
9342 #define VF_SB_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9343 #define VF_SB_CPM_ARQBAL1 0x0000F150 /* Reset Source: CORER */
9344 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_S 0
9345 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9346 #define VF_SB_CPM_ARQBAL1_ARQBAL_S 6
9347 #define VF_SB_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9348 #define VF_SB_CPM_ARQH1 0x0000F180 /* Reset Source: CORER */
9349 #define VF_SB_CPM_ARQH1_ARQH_S 0
9350 #define VF_SB_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9351 #define VF_SB_CPM_ARQLEN1 0x0000F170 /* Reset Source: PFR */
9352 #define VF_SB_CPM_ARQLEN1_ARQLEN_S 0
9353 #define VF_SB_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9354 #define VF_SB_CPM_ARQLEN1_ARQVFE_S 28
9355 #define VF_SB_CPM_ARQLEN1_ARQVFE_M BIT(28)
9356 #define VF_SB_CPM_ARQLEN1_ARQOVFL_S 29
9357 #define VF_SB_CPM_ARQLEN1_ARQOVFL_M BIT(29)
9358 #define VF_SB_CPM_ARQLEN1_ARQCRIT_S 30
9359 #define VF_SB_CPM_ARQLEN1_ARQCRIT_M BIT(30)
9360 #define VF_SB_CPM_ARQLEN1_ARQENABLE_S 31
9361 #define VF_SB_CPM_ARQLEN1_ARQENABLE_M BIT(31)
9362 #define VF_SB_CPM_ARQT1 0x0000F190 /* Reset Source: CORER */
9363 #define VF_SB_CPM_ARQT1_ARQT_S 0
9364 #define VF_SB_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9365 #define VF_SB_CPM_ATQBAH1 0x0000F110 /* Reset Source: CORER */
9366 #define VF_SB_CPM_ATQBAH1_ATQBAH_S 0
9367 #define VF_SB_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9368 #define VF_SB_CPM_ATQBAL1 0x0000F100 /* Reset Source: CORER */
9369 #define VF_SB_CPM_ATQBAL1_ATQBAL_S 6
9370 #define VF_SB_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9371 #define VF_SB_CPM_ATQH1 0x0000F130 /* Reset Source: CORER */
9372 #define VF_SB_CPM_ATQH1_ATQH_S 0
9373 #define VF_SB_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9374 #define VF_SB_CPM_ATQLEN1 0x0000F120 /* Reset Source: PFR */
9375 #define VF_SB_CPM_ATQLEN1_ATQLEN_S 0
9376 #define VF_SB_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9377 #define VF_SB_CPM_ATQLEN1_ATQVFE_S 28
9378 #define VF_SB_CPM_ATQLEN1_ATQVFE_M BIT(28)
9379 #define VF_SB_CPM_ATQLEN1_ATQOVFL_S 29
9380 #define VF_SB_CPM_ATQLEN1_ATQOVFL_M BIT(29)
9381 #define VF_SB_CPM_ATQLEN1_ATQCRIT_S 30
9382 #define VF_SB_CPM_ATQLEN1_ATQCRIT_M BIT(30)
9383 #define VF_SB_CPM_ATQLEN1_ATQENABLE_S 31
9384 #define VF_SB_CPM_ATQLEN1_ATQENABLE_M BIT(31)
9385 #define VF_SB_CPM_ATQT1 0x0000F140 /* Reset Source: CORER */
9386 #define VF_SB_CPM_ATQT1_ATQT_S 0
9387 #define VF_SB_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9388 #define VFINT_DYN_CTL(_i) (0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9389 #define VFINT_DYN_CTL_MAX_INDEX 7
9390 #define VFINT_DYN_CTL_INTENA_S 0
9391 #define VFINT_DYN_CTL_INTENA_M BIT(0)
9392 #define VFINT_DYN_CTL_CLEARPBA_S 1
9393 #define VFINT_DYN_CTL_CLEARPBA_M BIT(1)
9394 #define VFINT_DYN_CTL_SWINT_TRIG_S 2
9395 #define VFINT_DYN_CTL_SWINT_TRIG_M BIT(2)
9396 #define VFINT_DYN_CTL_ITR_INDX_S 3
9397 #define VFINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
9398 #define VFINT_DYN_CTL_INTERVAL_S 5
9399 #define VFINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
9400 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_S 24
9401 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
9402 #define VFINT_DYN_CTL_SW_ITR_INDX_S 25
9403 #define VFINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9404 #define VFINT_DYN_CTL_WB_ON_ITR_S 30
9405 #define VFINT_DYN_CTL_WB_ON_ITR_M BIT(30)
9406 #define VFINT_DYN_CTL_INTENA_MSK_S 31
9407 #define VFINT_DYN_CTL_INTENA_MSK_M BIT(31)
9408 #define VFINT_ITR_0(_i) (0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9409 #define VFINT_ITR_0_MAX_INDEX 7
9410 #define VFINT_ITR_0_INTERVAL_S 0
9411 #define VFINT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
9412 #define VFINT_ITR_1(_i) (0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9413 #define VFINT_ITR_1_MAX_INDEX 7
9414 #define VFINT_ITR_1_INTERVAL_S 0
9415 #define VFINT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
9416 #define VFINT_ITR_2(_i) (0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9417 #define VFINT_ITR_2_MAX_INDEX 7
9418 #define VFINT_ITR_2_INTERVAL_S 0
9419 #define VFINT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
9420 #define VFQRX_TAIL(_QRX) (0x0002E000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9421 #define VFQRX_TAIL_MAX_INDEX 255
9422 #define VFQRX_TAIL_TAIL_S 0
9423 #define VFQRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
9424 #define VFQTX_COMM_DBELL(_DBQM) (0x00030000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9425 #define VFQTX_COMM_DBELL_MAX_INDEX 255
9426 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_S 0
9427 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9428 #define VFQTX_COMM_DBLQ_DBELL(_DBLQ) (0x00022000 + ((_DBLQ) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
9429 #define VFQTX_COMM_DBLQ_DBELL_MAX_INDEX 3
9430 #define VFQTX_COMM_DBLQ_DBELL_TAIL_S 0
9431 #define VFQTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
9432 #define MSIX_TMSG1(_i) (0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
9433 #define MSIX_TMSG1_MAX_INDEX 64
9434 #define MSIX_TMSG1_MSIXTMSG_S 0
9435 #define MSIX_TMSG1_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
9436 #define VFPE_AEQALLOC1 0x0000A400 /* Reset Source: VFR */
9437 #define VFPE_AEQALLOC1_AECOUNT_S 0
9438 #define VFPE_AEQALLOC1_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
9439 #define VFPE_CCQPHIGH1 0x00009800 /* Reset Source: VFR */
9440 #define VFPE_CCQPHIGH1_PECCQPHIGH_S 0
9441 #define VFPE_CCQPHIGH1_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
9442 #define VFPE_CCQPLOW1 0x0000AC00 /* Reset Source: VFR */
9443 #define VFPE_CCQPLOW1_PECCQPLOW_S 0
9444 #define VFPE_CCQPLOW1_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
9445 #define VFPE_CCQPSTATUS1 0x0000B800 /* Reset Source: VFR */
9446 #define VFPE_CCQPSTATUS1_CCQP_DONE_S 0
9447 #define VFPE_CCQPSTATUS1_CCQP_DONE_M BIT(0)
9448 #define VFPE_CCQPSTATUS1_HMC_PROFILE_S 4
9449 #define VFPE_CCQPSTATUS1_HMC_PROFILE_M MAKEMASK(0x7, 4)
9450 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S 16
9451 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
9452 #define VFPE_CCQPSTATUS1_CCQP_ERR_S 31
9453 #define VFPE_CCQPSTATUS1_CCQP_ERR_M BIT(31)
9454 #define VFPE_CQACK1 0x0000B000 /* Reset Source: VFR */
9455 #define VFPE_CQACK1_PECQID_S 0
9456 #define VFPE_CQACK1_PECQID_M MAKEMASK(0x7FFFF, 0)
9457 #define VFPE_CQARM1 0x0000B400 /* Reset Source: VFR */
9458 #define VFPE_CQARM1_PECQID_S 0
9459 #define VFPE_CQARM1_PECQID_M MAKEMASK(0x7FFFF, 0)
9460 #define VFPE_CQPDB1 0x0000BC00 /* Reset Source: VFR */
9461 #define VFPE_CQPDB1_WQHEAD_S 0
9462 #define VFPE_CQPDB1_WQHEAD_M MAKEMASK(0x7FF, 0)
9463 #define VFPE_CQPERRCODES1 0x00009C00 /* Reset Source: VFR */
9464 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S 0
9465 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
9466 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S 16
9467 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
9468 #define VFPE_CQPTAIL1 0x0000A000 /* Reset Source: VFR */
9469 #define VFPE_CQPTAIL1_WQTAIL_S 0
9470 #define VFPE_CQPTAIL1_WQTAIL_M MAKEMASK(0x7FF, 0)
9471 #define VFPE_CQPTAIL1_CQP_OP_ERR_S 31
9472 #define VFPE_CQPTAIL1_CQP_OP_ERR_M BIT(31)
9473 #define VFPE_IPCONFIG01 0x00008C00 /* Reset Source: VFR */
9474 #define VFPE_IPCONFIG01_PEIPID_S 0
9475 #define VFPE_IPCONFIG01_PEIPID_M MAKEMASK(0xFFFF, 0)
9476 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_S 16
9477 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_M BIT(16)
9478 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S 17
9479 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M BIT(17)
9480 #define VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
9481 #define VFPE_MRTEIDXMASK1_MAX_INDEX 255
9482 #define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0
9483 #define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9484 #define VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */
9485 #define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
9486 #define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
9487 #define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */
9488 #define VFPE_TCPNOWTIMER1_TCP_NOW_S 0
9489 #define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
9490 #define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */
9491 #define VFPE_WQEALLOC1_PEQPID_S 0
9492 #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
9493 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20
9494 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
9495 #endif /* !_ICE_HW_AUTOGEN_H_ */
9496
9497 #ifndef _ICE_ADMINQ_CMD_H_
9498 #define _ICE_ADMINQ_CMD_H_
9499
9500 /* This header file defines the Admin Queue commands, error codes and
9501 * descriptor format. It is shared between Firmware and Software.
9502 */
9503
9504 #if 0
9505 #include "ice_osdep.h"
9506 #include "ice_defs.h"
9507 #include "ice_bitops.h"
9508 #endif
9509
9510 #define ICE_MAX_VSI 768
9511 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
9512 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
9513
9514 enum ice_aq_res_access_type {
9515 ICE_RES_READ = 1,
9516 ICE_RES_WRITE
9517 };
9518
9519 struct ice_aqc_generic {
9520 uint32_t param0;
9521 uint32_t param1;
9522 uint32_t addr_high;
9523 uint32_t addr_low;
9524 };
9525
9526 /* Get version (direct 0x0001) */
9527 struct ice_aqc_get_ver {
9528 uint32_t rom_ver;
9529 uint32_t fw_build;
9530 uint8_t fw_branch;
9531 uint8_t fw_major;
9532 uint8_t fw_minor;
9533 uint8_t fw_patch;
9534 uint8_t api_branch;
9535 uint8_t api_major;
9536 uint8_t api_minor;
9537 uint8_t api_patch;
9538 };
9539
9540 /* Send driver version (indirect 0x0002) */
9541 struct ice_aqc_driver_ver {
9542 uint8_t major_ver;
9543 uint8_t minor_ver;
9544 uint8_t build_ver;
9545 uint8_t subbuild_ver;
9546 uint8_t reserved[4];
9547 uint32_t addr_high;
9548 uint32_t addr_low;
9549 };
9550
9551 /* Queue Shutdown (direct 0x0003) */
9552 struct ice_aqc_q_shutdown {
9553 uint8_t driver_unloading;
9554 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
9555 uint8_t reserved[15];
9556 };
9557
9558 /* Get Expanded Error Code (0x0005, direct) */
9559 struct ice_aqc_get_exp_err {
9560 uint32_t reason;
9561 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF
9562 uint32_t identifier;
9563 uint8_t rsvd[8];
9564 };
9565
9566 /* Request resource ownership (direct 0x0008)
9567 * Release resource ownership (direct 0x0009)
9568 */
9569 struct ice_aqc_req_res {
9570 uint16_t res_id;
9571 #define ICE_AQC_RES_ID_NVM 1
9572 #define ICE_AQC_RES_ID_SDP 2
9573 #define ICE_AQC_RES_ID_CHNG_LOCK 3
9574 #define ICE_AQC_RES_ID_GLBL_LOCK 4
9575 uint16_t access_type;
9576 #define ICE_AQC_RES_ACCESS_READ 1
9577 #define ICE_AQC_RES_ACCESS_WRITE 2
9578
9579 /* Upon successful completion, FW writes this value and driver is
9580 * expected to release resource before timeout. This value is provided
9581 * in milliseconds.
9582 */
9583 uint32_t timeout;
9584 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
9585 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
9586 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
9587 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
9588 /* For SDP: pin ID of the SDP */
9589 uint32_t res_number;
9590 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
9591 uint16_t status;
9592 #define ICE_AQ_RES_GLBL_SUCCESS 0
9593 #define ICE_AQ_RES_GLBL_IN_PROG 1
9594 #define ICE_AQ_RES_GLBL_DONE 2
9595 uint8_t reserved[2];
9596 };
9597
9598 /* Get function capabilities (indirect 0x000A)
9599 * Get device capabilities (indirect 0x000B)
9600 */
9601 struct ice_aqc_list_caps {
9602 uint8_t cmd_flags;
9603 uint8_t pf_index;
9604 uint8_t reserved[2];
9605 uint32_t count;
9606 uint32_t addr_high;
9607 uint32_t addr_low;
9608 };
9609
9610 /* Device/Function buffer entry, repeated per reported capability */
9611 struct ice_aqc_list_caps_elem {
9612 uint16_t cap;
9613 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001
9614 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002
9615 #define ICE_AQC_CAPS_OS2BMC 0x0004
9616 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
9617 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
9618 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006
9619 #define ICE_AQC_CAPS_WOL_PROXY 0x0008
9620 #define ICE_AQC_CAPS_SRIOV 0x0012
9621 #define ICE_AQC_CAPS_VF 0x0013
9622 #define ICE_AQC_CAPS_VMDQ 0x0014
9623 #define ICE_AQC_CAPS_802_1QBG 0x0015
9624 #define ICE_AQC_CAPS_802_1BR 0x0016
9625 #define ICE_AQC_CAPS_VSI 0x0017
9626 #define ICE_AQC_CAPS_DCB 0x0018
9627 #define ICE_AQC_CAPS_RSVD 0x0021
9628 #define ICE_AQC_CAPS_ISCSI 0x0022
9629 #define ICE_AQC_CAPS_RSS 0x0040
9630 #define ICE_AQC_CAPS_RXQS 0x0041
9631 #define ICE_AQC_CAPS_TXQS 0x0042
9632 #define ICE_AQC_CAPS_MSIX 0x0043
9633 #define ICE_AQC_CAPS_MAX_MTU 0x0047
9634 #define ICE_AQC_CAPS_CEM 0x00F2
9635 #define ICE_AQC_CAPS_IWARP 0x0051
9636 #define ICE_AQC_CAPS_LED 0x0061
9637 #define ICE_AQC_CAPS_SDP 0x0062
9638 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064
9639 #define ICE_AQC_CAPS_SENSOR_READING 0x0067
9640 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073
9641 #define ICE_AQC_CAPS_SKU 0x0074
9642 #define ICE_AQC_CAPS_PORT_MAP 0x0075
9643 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
9644 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
9645 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
9646 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
9647 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
9648 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
9649 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
9650 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
9651 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
9652 #define ICE_AQC_CAPS_DYN_FLATTENING 0x008A
9653 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE 0x0090
9654 #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092
9655 #define ICE_AQC_BIT_ROCEV2_LAG 0x01
9656 #define ICE_AQC_BIT_SRIOV_LAG 0x02
9657
9658 uint8_t major_ver;
9659 uint8_t minor_ver;
9660 /* Number of resources described by this capability */
9661 uint32_t number;
9662 /* Only meaningful for some types of resources */
9663 uint32_t logical_id;
9664 /* Only meaningful for some types of resources */
9665 uint32_t phys_id;
9666 uint64_t rsvd1;
9667 uint64_t rsvd2;
9668 };
9669
9670 /* Manage MAC address, read command - indirect (0x0107)
9671 * This struct is also used for the response
9672 */
9673 struct ice_aqc_manage_mac_read {
9674 uint16_t flags; /* Zeroed by device driver */
9675 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
9676 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
9677 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
9678 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
9679 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
9680 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
9681 #define ICE_AQC_MAN_MAC_READ_S 4
9682 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
9683 uint8_t rsvd[2];
9684 uint8_t num_addr; /* Used in response */
9685 uint8_t rsvd1[3];
9686 uint32_t addr_high;
9687 uint32_t addr_low;
9688 };
9689
9690 /* Response buffer format for manage MAC read command */
9691 struct ice_aqc_manage_mac_read_resp {
9692 uint8_t lport_num;
9693 uint8_t addr_type;
9694 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
9695 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
9696 uint8_t mac_addr[ETHER_ADDR_LEN];
9697 };
9698
9699 /* Manage MAC address, write command - direct (0x0108) */
9700 struct ice_aqc_manage_mac_write {
9701 uint8_t rsvd;
9702 uint8_t flags;
9703 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
9704 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
9705 #define ICE_AQC_MAN_MAC_WR_S 6
9706 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
9707 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
9708 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
9709 /* byte stream in network order */
9710 uint8_t mac_addr[ETHER_ADDR_LEN];
9711 uint32_t addr_high;
9712 uint32_t addr_low;
9713 };
9714
9715 /* Clear PXE Command and response (direct 0x0110) */
9716 struct ice_aqc_clear_pxe {
9717 uint8_t rx_cnt;
9718 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
9719 uint8_t reserved[15];
9720 };
9721
9722 /* Configure No-Drop Policy Command (direct 0x0112) */
9723 struct ice_aqc_config_no_drop_policy {
9724 uint8_t opts;
9725 #define ICE_AQC_FORCE_NO_DROP BIT(0)
9726 uint8_t rsvd[15];
9727 };
9728
9729 /* Get switch configuration (0x0200) */
9730 struct ice_aqc_get_sw_cfg {
9731 /* Reserved for command and copy of request flags for response */
9732 uint16_t flags;
9733 /* First desc in case of command and next_elem in case of response
9734 * In case of response, if it is not zero, means all the configuration
9735 * was not returned and new command shall be sent with this value in
9736 * the 'first desc' field
9737 */
9738 uint16_t element;
9739 /* Reserved for command, only used for response */
9740 uint16_t num_elems;
9741 uint16_t rsvd;
9742 uint32_t addr_high;
9743 uint32_t addr_low;
9744 };
9745
9746 /* Each entry in the response buffer is of the following type: */
9747 struct ice_aqc_get_sw_cfg_resp_elem {
9748 /* VSI/Port Number */
9749 uint16_t vsi_port_num;
9750 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
9751 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
9752 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
9753 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
9754 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
9755 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
9756 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
9757 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
9758
9759 /* SWID VSI/Port belongs to */
9760 uint16_t swid;
9761
9762 /* Bit 14..0 : PF/VF number VSI belongs to
9763 * Bit 15 : VF indication bit
9764 */
9765 uint16_t pf_vf_num;
9766 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
9767 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
9768 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
9769 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
9770 };
9771
9772 /* Set Port parameters, (direct, 0x0203) */
9773 struct ice_aqc_set_port_params {
9774 uint16_t cmd_flags;
9775 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
9776 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
9777 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
9778 uint16_t bad_frame_vsi;
9779 #define ICE_AQC_SET_P_PARAMS_VSI_S 0
9780 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
9781 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
9782 uint16_t swid;
9783 #define ICE_AQC_SET_P_PARAMS_SWID_S 0
9784 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
9785 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8
9786 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \
9787 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
9788 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
9789 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
9790 uint8_t reserved[10];
9791 };
9792
9793 /* These resource type defines are used for all switch resource
9794 * commands where a resource type is required, such as:
9795 * Get Resource Allocation command (indirect 0x0204)
9796 * Allocate Resources command (indirect 0x0208)
9797 * Free Resources command (indirect 0x0209)
9798 * Get Allocated Resource Descriptors Command (indirect 0x020A)
9799 */
9800 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
9801 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
9802 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
9803 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
9804 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
9805 #define ICE_AQC_RES_TYPE_RECIPE 0x05
9806 #define ICE_AQC_RES_TYPE_PROFILE 0x06
9807 #define ICE_AQC_RES_TYPE_SWID 0x07
9808 #define ICE_AQC_RES_TYPE_VSI 0x08
9809 #define ICE_AQC_RES_TYPE_FLU 0x09
9810 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
9811 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
9812 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
9813 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
9814 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
9815 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
9816 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
9817 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
9818 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
9819 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
9820 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
9821 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
9822 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
9823 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
9824 /* Resource types 0x62-67 are reserved for Hash profile builder */
9825 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
9826 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
9827
9828 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
9829 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
9830 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
9831 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14)
9832 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15)
9833
9834 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
9835
9836 #define ICE_AQC_RES_TYPE_S 0
9837 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
9838
9839 /* Get Resource Allocation command (indirect 0x0204) */
9840 struct ice_aqc_get_res_alloc {
9841 uint16_t resp_elem_num; /* Used in response, reserved in command */
9842 uint8_t reserved[6];
9843 uint32_t addr_high;
9844 uint32_t addr_low;
9845 };
9846
9847 /* Get Resource Allocation Response Buffer per response */
9848 struct ice_aqc_get_res_resp_elem {
9849 uint16_t res_type; /* Types defined above cmd 0x0204 */
9850 uint16_t total_capacity; /* Resources available to all PF's */
9851 uint16_t total_function; /* Resources allocated for a PF */
9852 uint16_t total_shared; /* Resources allocated as shared */
9853 uint16_t total_free; /* Resources un-allocated/not reserved by any PF */
9854 };
9855
9856 /* Allocate Resources command (indirect 0x0208)
9857 * Free Resources command (indirect 0x0209)
9858 */
9859 struct ice_aqc_alloc_free_res_cmd {
9860 uint16_t num_entries; /* Number of Resource entries */
9861 uint8_t reserved[6];
9862 uint32_t addr_high;
9863 uint32_t addr_low;
9864 };
9865
9866 /* Resource descriptor */
9867 struct ice_aqc_res_elem {
9868 union {
9869 uint16_t sw_resp;
9870 uint16_t flu_resp;
9871 } e;
9872 };
9873
9874 /* Buffer for Allocate/Free Resources commands */
9875 struct ice_aqc_alloc_free_res_elem {
9876 uint16_t res_type; /* Types defined above cmd 0x0204 */
9877 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
9878 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
9879 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
9880 uint16_t num_elems;
9881 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
9882 };
9883
9884 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
9885 struct ice_aqc_get_allocd_res_desc {
9886 union {
9887 struct {
9888 uint16_t res; /* Types defined above cmd 0x0204 */
9889 uint16_t first_desc;
9890 uint32_t reserved;
9891 } cmd;
9892 struct {
9893 uint16_t res;
9894 uint16_t next_desc;
9895 uint16_t num_desc;
9896 uint16_t reserved;
9897 } resp;
9898 } ops;
9899 uint32_t addr_high;
9900 uint32_t addr_low;
9901 };
9902
9903 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
9904 struct ice_aqc_set_vlan_mode {
9905 uint8_t reserved;
9906 uint8_t l2tag_prio_tagging;
9907 #define ICE_AQ_VLAN_PRIO_TAG_S 0
9908 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
9909 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
9910 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
9911 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
9912 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
9913 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
9914 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
9915 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
9916 uint8_t l2tag_reserved[64];
9917 uint8_t rdma_packet;
9918 #define ICE_AQ_VLAN_RDMA_TAG_S 0
9919 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
9920 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
9921 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
9922 uint8_t rdma_reserved[2];
9923 uint8_t mng_vlan_prot_id;
9924 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
9925 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
9926 uint8_t prot_id_reserved[30];
9927 };
9928
9929 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
9930 struct ice_aqc_get_vlan_mode {
9931 uint8_t vlan_mode;
9932 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
9933 uint8_t l2tag_prio_tagging;
9934 uint8_t reserved[98];
9935 };
9936
9937 /* Add VSI (indirect 0x0210)
9938 * Update VSI (indirect 0x0211)
9939 * Get VSI (indirect 0x0212)
9940 * Free VSI (indirect 0x0213)
9941 */
9942 struct ice_aqc_add_get_update_free_vsi {
9943 uint16_t vsi_num;
9944 #define ICE_AQ_VSI_NUM_S 0
9945 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
9946 #define ICE_AQ_VSI_IS_VALID BIT(15)
9947 uint16_t cmd_flags;
9948 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
9949 uint8_t vf_id;
9950 uint8_t reserved;
9951 uint16_t vsi_flags;
9952 #define ICE_AQ_VSI_TYPE_S 0
9953 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
9954 #define ICE_AQ_VSI_TYPE_VF 0x0
9955 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
9956 #define ICE_AQ_VSI_TYPE_PF 0x2
9957 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
9958 uint32_t addr_high;
9959 uint32_t addr_low;
9960 };
9961
9962 /* Response descriptor for:
9963 * Add VSI (indirect 0x0210)
9964 * Update VSI (indirect 0x0211)
9965 * Free VSI (indirect 0x0213)
9966 */
9967 struct ice_aqc_add_update_free_vsi_resp {
9968 uint16_t vsi_num;
9969 uint16_t ext_status;
9970 uint16_t vsi_used;
9971 uint16_t vsi_free;
9972 uint32_t addr_high;
9973 uint32_t addr_low;
9974 };
9975
9976 struct ice_aqc_get_vsi_resp {
9977 uint16_t vsi_num;
9978 uint8_t vf_id;
9979 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
9980 * These are found above in struct ice_aqc_add_get_update_free_vsi.
9981 */
9982 uint8_t vsi_flags;
9983 uint16_t vsi_used;
9984 uint16_t vsi_free;
9985 uint32_t addr_high;
9986 uint32_t addr_low;
9987 };
9988
9989 struct ice_aqc_vsi_props {
9990 uint16_t valid_sections;
9991 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
9992 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
9993 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
9994 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
9995 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
9996 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
9997 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
9998 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
9999 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
10000 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
10001 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
10002 /* switch section */
10003 uint8_t sw_id;
10004 uint8_t sw_flags;
10005 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
10006 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
10007 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
10008 uint8_t sw_flags2;
10009 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
10010 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
10011 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
10012 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3)
10013 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
10014 uint8_t veb_stat_id;
10015 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
10016 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
10017 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
10018 /* security section */
10019 uint8_t sec_flags;
10020 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
10021 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
10022 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
10023 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
10024 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
10025 uint8_t sec_reserved;
10026 /* VLAN section */
10027 uint16_t port_based_inner_vlan; /* VLANS include priority bits */
10028 uint8_t inner_vlan_reserved[2];
10029 uint8_t inner_vlan_flags;
10030 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
10031 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
10032 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
10033 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
10034 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
10035 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
10036 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
10037 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
10038 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
10039 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
10040 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
10041 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
10042 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
10043 uint8_t inner_vlan_reserved2[3];
10044 /* ingress egress up sections */
10045 uint32_t ingress_table; /* bitmap, 3 bits per up */
10046 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
10047 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
10048 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
10049 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
10050 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
10051 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
10052 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
10053 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
10054 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
10055 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
10056 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
10057 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
10058 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
10059 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
10060 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
10061 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
10062 uint32_t egress_table; /* same defines as for ingress table */
10063 /* outer tags section */
10064 uint16_t port_based_outer_vlan;
10065 uint8_t outer_vlan_flags;
10066 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
10067 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
10068 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
10069 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
10070 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
10071 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
10072 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
10073 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
10074 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
10075 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
10076 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
10077 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
10078 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
10079 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
10080 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
10081 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
10082 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
10083 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
10084 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
10085 uint8_t outer_vlan_reserved;
10086 /* queue mapping section */
10087 uint16_t mapping_flags;
10088 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
10089 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
10090 uint16_t q_mapping[16];
10091 #define ICE_AQ_VSI_Q_S 0
10092 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
10093 uint16_t tc_mapping[8];
10094 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
10095 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
10096 #define ICE_AQ_VSI_TC_Q_NUM_S 11
10097 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
10098 /* queueing option section */
10099 uint8_t q_opt_rss;
10100 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
10101 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
10102 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
10103 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
10104 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
10105 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
10106 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
10107 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
10108 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
10109 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
10110 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
10111 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
10112 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
10113 uint8_t q_opt_tc;
10114 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
10115 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
10116 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
10117 uint8_t q_opt_flags;
10118 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
10119 uint8_t q_opt_reserved[3];
10120 /* outer up section */
10121 uint32_t outer_up_table; /* same structure and defines as ingress tbl */
10122 /* section 10 */
10123 uint16_t sect_10_reserved;
10124 /* flow director section */
10125 uint16_t fd_options;
10126 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
10127 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
10128 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
10129 uint16_t max_fd_fltr_dedicated;
10130 uint16_t max_fd_fltr_shared;
10131 uint16_t fd_def_q;
10132 #define ICE_AQ_VSI_FD_DEF_Q_S 0
10133 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
10134 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
10135 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
10136 uint16_t fd_report_opt;
10137 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
10138 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
10139 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
10140 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
10141 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
10142 /* PASID section */
10143 uint32_t pasid_id;
10144 #define ICE_AQ_VSI_PASID_ID_S 0
10145 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
10146 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
10147 uint8_t reserved[24];
10148 };
10149
10150 /* Add/update mirror rule - direct (0x0260) */
10151 #define ICE_AQC_RULE_ID_VALID_S 7
10152 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
10153 #define ICE_AQC_RULE_ID_S 0
10154 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
10155
10156 /* Following defines to be used while processing caller specified mirror list
10157 * of VSI indexes.
10158 */
10159 /* Action: Byte.bit (1.7)
10160 * 0 = Remove VSI from mirror rule
10161 * 1 = Add VSI to mirror rule
10162 */
10163 #define ICE_AQC_RULE_ACT_S 15
10164 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
10165 /* Action: 1.2:0.0 = Mirrored VSI */
10166 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
10167 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
10168
10169 /* This is to be used by add/update mirror rule Admin Queue command.
10170 * In case of add mirror rule - if rule ID is specified as
10171 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
10172 * If specified rule_id is valid, then it is used. If specified rule_id
10173 * is in use then new mirroring rule is added.
10174 */
10175 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
10176
10177 struct ice_aqc_add_update_mir_rule {
10178 uint16_t rule_id;
10179
10180 uint16_t rule_type;
10181 #define ICE_AQC_RULE_TYPE_S 0
10182 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
10183 /* VPORT ingress/egress */
10184 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
10185 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
10186 /* Physical port ingress mirroring.
10187 * All traffic received by this port
10188 */
10189 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
10190 /* Physical port egress mirroring. All traffic sent by this port */
10191 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
10192
10193 /* Number of mirrored entries.
10194 * The values are in the command buffer
10195 */
10196 uint16_t num_entries;
10197
10198 /* Destination VSI */
10199 uint16_t dest;
10200 uint32_t addr_high;
10201 uint32_t addr_low;
10202 };
10203
10204 /* Delete mirror rule - direct(0x0261) */
10205 struct ice_aqc_delete_mir_rule {
10206 uint16_t rule_id;
10207 uint16_t rsvd;
10208
10209 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
10210 * the PF allocated resources, otherwise it is returned to the
10211 * shared pool
10212 */
10213 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
10214 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
10215 uint16_t flags;
10216
10217 uint8_t reserved[10];
10218 };
10219
10220 /* Set/Get storm config - (direct 0x0280, 0x0281) */
10221 /* This structure holds get storm configuration response and same structure
10222 * is used to perform set_storm_cfg
10223 */
10224 struct ice_aqc_storm_cfg {
10225 uint32_t bcast_thresh_size;
10226 uint32_t mcast_thresh_size;
10227 /* Bit 18:0 - Traffic upper threshold size
10228 * Bit 31:19 - Reserved
10229 */
10230 #define ICE_AQ_THRESHOLD_S 0
10231 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
10232
10233 uint32_t storm_ctrl_ctrl;
10234 /* Bit 0: MDIPW - Drop Multicast packets in previous window
10235 * Bit 1: MDICW - Drop multicast packets in current window
10236 * Bit 2: BDIPW - Drop broadcast packets in previous window
10237 * Bit 3: BDICW - Drop broadcast packets in current window
10238 */
10239 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
10240 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
10241 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
10242 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
10243 /* Bit 7:5 : Reserved */
10244 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
10245 * interval size for applying ingress broadcast or multicast storm
10246 * control.
10247 */
10248 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
10249 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
10250 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
10251 uint32_t reserved;
10252 };
10253
10254 #define ICE_MAX_NUM_RECIPES 64
10255
10256 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
10257 */
10258 struct ice_aqc_sw_rules {
10259 /* ops: add switch rules, referring the number of rules.
10260 * ops: update switch rules, referring the number of filters
10261 * ops: remove switch rules, referring the entry index.
10262 * ops: get switch rules, referring to the number of filters.
10263 */
10264 uint16_t num_rules_fltr_entry_index;
10265 uint8_t reserved[6];
10266 uint32_t addr_high;
10267 uint32_t addr_low;
10268 };
10269
10270 /* Add switch rule response:
10271 * Content of return buffer is same as the input buffer. The status field and
10272 * LUT index are updated as part of the response
10273 */
10274 struct ice_aqc_sw_rules_elem_hdr {
10275 uint16_t type; /* Switch rule type, one of T_... */
10276 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
10277 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
10278 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
10279 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
10280 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
10281 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
10282 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
10283 uint16_t status;
10284 };
10285
10286 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
10287 * This structures describes the lookup rules and associated actions. "index"
10288 * is returned as part of a response to a successful Add command, and can be
10289 * used to identify the rule for Update/Get/Remove commands.
10290 */
10291 struct ice_sw_rule_lkup_rx_tx {
10292 struct ice_aqc_sw_rules_elem_hdr hdr;
10293
10294 uint16_t recipe_id;
10295 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
10296 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
10297 uint16_t src;
10298 uint32_t act;
10299
10300 /* Bit 0:1 - Action type */
10301 #define ICE_SINGLE_ACT_TYPE_S 0x00
10302 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
10303
10304 /* Bit 2 - Loop back enable
10305 * Bit 3 - LAN enable
10306 */
10307 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
10308 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
10309
10310 /* Action type = 0 - Forward to VSI or VSI list */
10311 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
10312
10313 #define ICE_SINGLE_ACT_VSI_ID_S 4
10314 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
10315 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
10316 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
10317 /* This bit needs to be set if action is forward to VSI list */
10318 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
10319 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
10320 #define ICE_SINGLE_ACT_DROP BIT(18)
10321
10322 /* Action type = 1 - Forward to Queue of Queue group */
10323 #define ICE_SINGLE_ACT_TO_Q 0x1
10324 #define ICE_SINGLE_ACT_Q_INDEX_S 4
10325 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
10326 #define ICE_SINGLE_ACT_Q_REGION_S 15
10327 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
10328 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
10329
10330 /* Action type = 2 - Prune */
10331 #define ICE_SINGLE_ACT_PRUNE 0x2
10332 #define ICE_SINGLE_ACT_EGRESS BIT(15)
10333 #define ICE_SINGLE_ACT_INGRESS BIT(16)
10334 #define ICE_SINGLE_ACT_PRUNET BIT(17)
10335 /* Bit 18 should be set to 0 for this action */
10336
10337 /* Action type = 2 - Pointer */
10338 #define ICE_SINGLE_ACT_PTR 0x2
10339 #define ICE_SINGLE_ACT_PTR_VAL_S 4
10340 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
10341 /* Bit 17 should be set if pointed action includes a FWD cmd */
10342 #define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17)
10343 /* Bit 18 should be set to 1 */
10344 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
10345
10346 /* Action type = 3 - Other actions. Last two bits
10347 * are other action identifier
10348 */
10349 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
10350 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
10351 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
10352 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
10353
10354 /* Bit 17:18 - Defines other actions */
10355 /* Other action = 0 - Mirror VSI */
10356 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
10357 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
10358 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
10359 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
10360
10361 /* Other action = 3 - Set Stat count */
10362 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
10363 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
10364 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
10365 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
10366
10367 uint16_t index; /* The index of the rule in the lookup table */
10368 /* Length and values of the header to be matched per recipe or
10369 * lookup-type
10370 */
10371 uint16_t hdr_len;
10372 uint8_t hdr_data[STRUCT_HACK_VAR_LEN];
10373 };
10374
10375 /* Add/Update/Remove large action command/response entry
10376 * "index" is returned as part of a response to a successful Add command, and
10377 * can be used to identify the action for Update/Get/Remove commands.
10378 */
10379 struct ice_sw_rule_lg_act {
10380 struct ice_aqc_sw_rules_elem_hdr hdr;
10381
10382 uint16_t index; /* Index in large action table */
10383 uint16_t size;
10384 /* Max number of large actions */
10385 #define ICE_MAX_LG_ACT 4
10386 /* Bit 0:1 - Action type */
10387 #define ICE_LG_ACT_TYPE_S 0
10388 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
10389
10390 /* Action type = 0 - Forward to VSI or VSI list */
10391 #define ICE_LG_ACT_VSI_FORWARDING 0
10392 #define ICE_LG_ACT_VSI_ID_S 3
10393 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
10394 #define ICE_LG_ACT_VSI_LIST_ID_S 3
10395 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
10396 /* This bit needs to be set if action is forward to VSI list */
10397 #define ICE_LG_ACT_VSI_LIST BIT(13)
10398
10399 #define ICE_LG_ACT_VALID_BIT BIT(16)
10400
10401 /* Action type = 1 - Forward to Queue of Queue group */
10402 #define ICE_LG_ACT_TO_Q 0x1
10403 #define ICE_LG_ACT_Q_INDEX_S 3
10404 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
10405 #define ICE_LG_ACT_Q_REGION_S 14
10406 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
10407 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
10408
10409 /* Action type = 2 - Prune */
10410 #define ICE_LG_ACT_PRUNE 0x2
10411 #define ICE_LG_ACT_EGRESS BIT(14)
10412 #define ICE_LG_ACT_INGRESS BIT(15)
10413 #define ICE_LG_ACT_PRUNET BIT(16)
10414
10415 /* Action type = 3 - Mirror VSI */
10416 #define ICE_LG_OTHER_ACT_MIRROR 0x3
10417 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
10418 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
10419
10420 /* Action type = 5 - Generic Value */
10421 #define ICE_LG_ACT_GENERIC 0x5
10422 #define ICE_LG_ACT_GENERIC_VALUE_S 3
10423 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
10424 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
10425 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
10426 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
10427 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
10428 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
10429
10430 /* Action = 7 - Set Stat count */
10431 #define ICE_LG_ACT_STAT_COUNT 0x7
10432 #define ICE_LG_ACT_STAT_COUNT_S 3
10433 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
10434 uint32_t act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
10435 } __packed;
10436
10437 /* Add/Update/Remove VSI list command/response entry
10438 * "index" is returned as part of a response to a successful Add command, and
10439 * can be used to identify the VSI list for Update/Get/Remove commands.
10440 */
10441 struct ice_sw_rule_vsi_list {
10442 struct ice_aqc_sw_rules_elem_hdr hdr;
10443
10444 uint16_t index; /* Index of VSI/Prune list */
10445 uint16_t number_vsi;
10446 uint16_t vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
10447 } __packed;
10448
10449 /* Query VSI list command/response entry */
10450 struct ice_sw_rule_vsi_list_query {
10451 uint16_t index;
10452 uint8_t vsi_list[howmany(ICE_MAX_VSI, 8)];
10453 } __packed;
10454
10455 /* PFC Ignore (direct 0x0301)
10456 * The command and response use the same descriptor structure
10457 */
10458 struct ice_aqc_pfc_ignore {
10459 uint8_t tc_bitmap;
10460 uint8_t cmd_flags; /* unused in response */
10461 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
10462 #define ICE_AQC_PFC_IGNORE_CLEAR 0
10463 uint8_t reserved[14];
10464 };
10465
10466 /* Query PFC Mode (direct 0x0302)
10467 * Set PFC Mode (direct 0x0303)
10468 */
10469 struct ice_aqc_set_query_pfc_mode {
10470 uint8_t pfc_mode;
10471 /* For Set Command response, reserved in all other cases */
10472 #define ICE_AQC_PFC_NOT_CONFIGURED 0
10473 /* For Query Command response, reserved in all other cases */
10474 #define ICE_AQC_DCB_DIS 0
10475 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
10476 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
10477 uint8_t rsvd[15];
10478 };
10479
10480 /* Set DCB Parameters (direct 0x0306) */
10481 struct ice_aqc_set_dcb_params {
10482 uint8_t cmd_flags; /* unused in response */
10483 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
10484 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
10485 uint8_t valid_flags; /* unused in response */
10486 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
10487 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
10488 uint8_t rsvd[14];
10489 };
10490
10491 /* Get Default Topology (indirect 0x0400) */
10492 struct ice_aqc_get_topo {
10493 uint8_t port_num;
10494 uint8_t num_branches;
10495 uint16_t reserved1;
10496 uint32_t reserved2;
10497 uint32_t addr_high;
10498 uint32_t addr_low;
10499 };
10500
10501 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */
10502 struct ice_aqc_get_set_tx_topo {
10503 uint8_t set_flags;
10504 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)
10505 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1)
10506 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2)
10507 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4)
10508 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5)
10509 uint8_t get_flags;
10510 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0
10511 #define ICE_AQC_TX_TOPO_GET_PSM 1
10512 #define ICE_AQC_TX_TOPO_GET_RAM 2
10513 uint16_t reserved1;
10514 uint32_t reserved2;
10515 uint32_t addr_high;
10516 uint32_t addr_low;
10517 };
10518
10519 /* Update TSE (indirect 0x0403)
10520 * Get TSE (indirect 0x0404)
10521 * Add TSE (indirect 0x0401)
10522 * Delete TSE (indirect 0x040F)
10523 * Move TSE (indirect 0x0408)
10524 * Suspend Nodes (indirect 0x0409)
10525 * Resume Nodes (indirect 0x040A)
10526 */
10527 struct ice_aqc_sched_elem_cmd {
10528 uint16_t num_elem_req; /* Used by commands */
10529 uint16_t num_elem_resp; /* Used by responses */
10530 uint32_t reserved;
10531 uint32_t addr_high;
10532 uint32_t addr_low;
10533 };
10534
10535 struct ice_aqc_txsched_move_grp_info_hdr {
10536 uint32_t src_parent_teid;
10537 uint32_t dest_parent_teid;
10538 uint16_t num_elems;
10539 uint8_t flags;
10540 uint8_t reserved;
10541 };
10542
10543 struct ice_aqc_move_elem {
10544 struct ice_aqc_txsched_move_grp_info_hdr hdr;
10545 uint32_t teid[STRUCT_HACK_VAR_LEN];
10546 };
10547
10548 struct ice_aqc_elem_info_bw {
10549 uint16_t bw_profile_idx;
10550 uint16_t bw_alloc;
10551 };
10552
10553 struct ice_aqc_txsched_elem {
10554 uint8_t elem_type; /* Special field, reserved for some aq calls */
10555 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
10556 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
10557 #define ICE_AQC_ELEM_TYPE_TC 0x2
10558 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
10559 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
10560 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
10561 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
10562 uint8_t valid_sections;
10563 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
10564 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
10565 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
10566 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
10567 uint8_t generic;
10568 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
10569 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
10570 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
10571 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
10572 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
10573 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
10574 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
10575 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
10576 uint8_t flags; /* Special field, reserved for some aq calls */
10577 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
10578 struct ice_aqc_elem_info_bw cir_bw;
10579 struct ice_aqc_elem_info_bw eir_bw;
10580 uint16_t srl_id;
10581 uint16_t reserved2;
10582 };
10583
10584 struct ice_aqc_txsched_elem_data {
10585 uint32_t parent_teid;
10586 uint32_t node_teid;
10587 struct ice_aqc_txsched_elem data;
10588 };
10589
10590 struct ice_aqc_txsched_topo_grp_info_hdr {
10591 uint32_t parent_teid;
10592 uint16_t num_elems;
10593 uint16_t reserved2;
10594 };
10595
10596 struct ice_aqc_add_elem {
10597 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
10598 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
10599 };
10600
10601 struct ice_aqc_get_topo_elem {
10602 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
10603 struct ice_aqc_txsched_elem_data
10604 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
10605 };
10606
10607 struct ice_aqc_delete_elem {
10608 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
10609 uint32_t teid[STRUCT_HACK_VAR_LEN];
10610 };
10611
10612 /* Query Port ETS (indirect 0x040E)
10613 *
10614 * This indirect command is used to query port TC node configuration.
10615 */
10616 struct ice_aqc_query_port_ets {
10617 uint32_t port_teid;
10618 uint32_t reserved;
10619 uint32_t addr_high;
10620 uint32_t addr_low;
10621 };
10622
10623 struct ice_aqc_port_ets_elem {
10624 uint8_t tc_valid_bits;
10625 uint8_t reserved[3];
10626 /* 3 bits for UP per TC 0-7, 4th byte reserved */
10627 uint32_t up2tc;
10628 uint8_t tc_bw_share[8];
10629 uint32_t port_eir_prof_id;
10630 uint32_t port_cir_prof_id;
10631 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
10632 uint32_t tc_node_prio;
10633 #define ICE_TC_NODE_PRIO_S 0x4
10634 uint8_t reserved1[4];
10635 uint32_t tc_node_teid[8]; /* Used for response, reserved in command */
10636 };
10637
10638 /* Rate limiting profile for
10639 * Add RL profile (indirect 0x0410)
10640 * Query RL profile (indirect 0x0411)
10641 * Remove RL profile (indirect 0x0415)
10642 * These indirect commands acts on single or multiple
10643 * RL profiles with specified data.
10644 */
10645 struct ice_aqc_rl_profile {
10646 uint16_t num_profiles;
10647 uint16_t num_processed; /* Only for response. Reserved in Command. */
10648 uint8_t reserved[4];
10649 uint32_t addr_high;
10650 uint32_t addr_low;
10651 };
10652
10653 struct ice_aqc_rl_profile_elem {
10654 uint8_t level;
10655 uint8_t flags;
10656 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
10657 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
10658 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
10659 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
10660 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
10661 /* The following flag is used for Query RL Profile Data */
10662 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
10663 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
10664
10665 uint16_t profile_id;
10666 uint16_t max_burst_size;
10667 uint16_t rl_multiply;
10668 uint16_t wake_up_calc;
10669 uint16_t rl_encode;
10670 };
10671
10672 /* Config Node Attributes (indirect 0x0419)
10673 * Query Node Attributes (indirect 0x041A)
10674 */
10675 struct ice_aqc_node_attr {
10676 uint16_t num_entries; /* Number of attributes structures in the buffer */
10677 uint8_t reserved[6];
10678 uint32_t addr_high;
10679 uint32_t addr_low;
10680 };
10681
10682 struct ice_aqc_node_attr_elem {
10683 uint32_t node_teid;
10684 uint16_t max_children;
10685 uint16_t children_level;
10686 };
10687
10688 /* Configure L2 Node CGD (indirect 0x0414)
10689 * This indirect command allows configuring a congestion domain for given L2
10690 * node TEIDs in the scheduler topology.
10691 */
10692 struct ice_aqc_cfg_l2_node_cgd {
10693 uint16_t num_l2_nodes;
10694 uint8_t reserved[6];
10695 uint32_t addr_high;
10696 uint32_t addr_low;
10697 };
10698
10699 struct ice_aqc_cfg_l2_node_cgd_elem {
10700 uint32_t node_teid;
10701 uint8_t cgd;
10702 uint8_t reserved[3];
10703 };
10704
10705 /* Query Scheduler Resource Allocation (indirect 0x0412)
10706 * This indirect command retrieves the scheduler resources allocated by
10707 * EMP Firmware to the given PF.
10708 */
10709 struct ice_aqc_query_txsched_res {
10710 uint8_t reserved[8];
10711 uint32_t addr_high;
10712 uint32_t addr_low;
10713 };
10714
10715 struct ice_aqc_generic_sched_props {
10716 uint16_t phys_levels;
10717 uint16_t logical_levels;
10718 uint8_t flattening_bitmap;
10719 uint8_t max_device_cgds;
10720 uint8_t max_pf_cgds;
10721 uint8_t rsvd0;
10722 uint16_t rdma_qsets;
10723 uint8_t rsvd1[22];
10724 };
10725
10726 struct ice_aqc_layer_props {
10727 uint8_t logical_layer;
10728 uint8_t chunk_size;
10729 uint16_t max_device_nodes;
10730 uint16_t max_pf_nodes;
10731 uint8_t rsvd0[4];
10732 uint16_t max_sibl_grp_sz;
10733 uint16_t max_cir_rl_profiles;
10734 uint16_t max_eir_rl_profiles;
10735 uint16_t max_srl_profiles;
10736 uint8_t rsvd1[14];
10737 };
10738
10739 struct ice_aqc_query_txsched_res_resp {
10740 struct ice_aqc_generic_sched_props sched_props;
10741 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
10742 };
10743
10744 /* Query Node to Root Topology (indirect 0x0413)
10745 * This command uses ice_aqc_get_elem as its data buffer.
10746 */
10747 struct ice_aqc_query_node_to_root {
10748 uint32_t teid;
10749 uint32_t num_nodes; /* Response only */
10750 uint32_t addr_high;
10751 uint32_t addr_low;
10752 };
10753
10754 /* Get PHY capabilities (indirect 0x0600) */
10755 struct ice_aqc_get_phy_caps {
10756 uint8_t lport_num;
10757 uint8_t reserved;
10758 uint16_t param0;
10759 /* 18.0 - Report qualified modules */
10760 #define ICE_AQC_GET_PHY_RQM BIT(0)
10761 /* 18.1 - 18.3 : Report mode
10762 * 000b - Report topology capabilities, without media
10763 * 001b - Report topology capabilities, with media
10764 * 010b - Report Active configuration
10765 * 011b - Report PHY Type and FEC mode capabilities
10766 * 100b - Report Default capabilities
10767 */
10768 #define ICE_AQC_REPORT_MODE_S 1
10769 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
10770 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
10771 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
10772 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
10773 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
10774 uint32_t reserved1;
10775 uint32_t addr_high;
10776 uint32_t addr_low;
10777 };
10778
10779 /* This is #define of PHY type (Extended):
10780 * The first set of defines is for phy_type_low.
10781 */
10782 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
10783 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
10784 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
10785 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
10786 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
10787 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
10788 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
10789 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
10790 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
10791 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
10792 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
10793 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
10794 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
10795 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
10796 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
10797 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
10798 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
10799 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
10800 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
10801 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
10802 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
10803 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
10804 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
10805 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
10806 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
10807 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
10808 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
10809 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
10810 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
10811 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
10812 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
10813 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
10814 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
10815 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
10816 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
10817 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
10818 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
10819 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
10820 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
10821 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
10822 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
10823 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
10824 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
10825 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
10826 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
10827 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
10828 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
10829 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
10830 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
10831 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
10832 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
10833 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
10834 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
10835 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
10836 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
10837 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
10838 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
10839 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
10840 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
10841 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
10842 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
10843 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
10844 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
10845 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
10846 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
10847 /* The second set of defines is for phy_type_high. */
10848 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
10849 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
10850 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
10851 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
10852 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
10853 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 4
10854
10855 struct ice_aqc_get_phy_caps_data {
10856 uint64_t phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
10857 uint64_t phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
10858 uint8_t caps;
10859 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
10860 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
10861 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
10862 #define ICE_AQC_PHY_EN_LINK BIT(3)
10863 #define ICE_AQC_PHY_AN_MODE BIT(4)
10864 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
10865 #define ICE_AQC_PHY_EN_LESM BIT(6)
10866 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
10867 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
10868 uint8_t low_power_ctrl_an;
10869 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
10870 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
10871 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
10872 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
10873 uint16_t eee_cap;
10874 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
10875 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
10876 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
10877 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
10878 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
10879 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
10880 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
10881 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
10882 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
10883 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
10884 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
10885 uint16_t eeer_value;
10886 uint8_t phy_id_oui[4]; /* PHY/Module ID connected on the port */
10887 uint8_t phy_fw_ver[8];
10888 uint8_t link_fec_options;
10889 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
10890 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
10891 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
10892 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
10893 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
10894 #define ICE_AQC_PHY_FEC_DIS BIT(5)
10895 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
10896 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
10897 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
10898 uint8_t module_compliance_enforcement;
10899 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
10900 uint8_t extended_compliance_code;
10901 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
10902 uint8_t module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
10903 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
10904 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
10905 #define ICE_AQC_MOD_TYPE_IDENT 1
10906 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
10907 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
10908 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
10909 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
10910 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
10911 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
10912 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
10913 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
10914 uint8_t qualified_module_count;
10915 uint8_t rsvd2[7]; /* Bytes 47:41 reserved */
10916 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
10917 struct {
10918 uint8_t v_oui[3];
10919 uint8_t rsvd3;
10920 uint8_t v_part[16];
10921 uint32_t v_rev;
10922 uint64_t rsvd4;
10923 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
10924 };
10925
10926 /* Set PHY capabilities (direct 0x0601)
10927 * NOTE: This command must be followed by setup link and restart auto-neg
10928 */
10929 struct ice_aqc_set_phy_cfg {
10930 uint8_t lport_num;
10931 uint8_t reserved[7];
10932 uint32_t addr_high;
10933 uint32_t addr_low;
10934 };
10935
10936 /* Set PHY config command data structure */
10937 struct ice_aqc_set_phy_cfg_data {
10938 uint64_t phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
10939 uint64_t phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
10940 uint8_t caps;
10941 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
10942 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
10943 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
10944 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
10945 #define ICE_AQ_PHY_ENA_LINK BIT(3)
10946 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
10947 #define ICE_AQ_PHY_ENA_LESM BIT(6)
10948 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
10949 uint8_t low_power_ctrl_an;
10950 uint16_t eee_cap; /* Value from ice_aqc_get_phy_caps */
10951 uint16_t eeer_value;
10952 uint8_t link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
10953 uint8_t module_compliance_enforcement;
10954 };
10955
10956 /* Set MAC Config command data structure (direct 0x0603) */
10957 struct ice_aqc_set_mac_cfg {
10958 uint16_t max_frame_size;
10959 uint8_t params;
10960 #define ICE_AQ_SET_MAC_PACE_S 3
10961 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
10962 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
10963 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
10964 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
10965 uint8_t tx_tmr_priority;
10966 uint16_t tx_tmr_value;
10967 uint16_t fc_refresh_threshold;
10968 uint8_t drop_opts;
10969 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
10970 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
10971 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
10972 uint8_t reserved[7];
10973 };
10974
10975 /* Restart AN command data structure (direct 0x0605)
10976 * Also used for response, with only the lport_num field present.
10977 */
10978 struct ice_aqc_restart_an {
10979 uint8_t lport_num;
10980 uint8_t reserved;
10981 uint8_t cmd_flags;
10982 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
10983 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
10984 uint8_t reserved2[13];
10985 };
10986
10987 /* Get link status (indirect 0x0607), also used for Link Status Event */
10988 struct ice_aqc_get_link_status {
10989 uint8_t lport_num;
10990 uint8_t reserved;
10991 uint16_t cmd_flags;
10992 #define ICE_AQ_LSE_M 0x3
10993 #define ICE_AQ_LSE_NOP 0x0
10994 #define ICE_AQ_LSE_DIS 0x2
10995 #define ICE_AQ_LSE_ENA 0x3
10996 /* only response uses this flag */
10997 #define ICE_AQ_LSE_IS_ENABLED 0x1
10998 uint32_t reserved2;
10999 uint32_t addr_high;
11000 uint32_t addr_low;
11001 };
11002
11003 enum ice_get_link_status_data_version {
11004 ICE_GET_LINK_STATUS_DATA_V1 = 1,
11005 };
11006
11007 #define ICE_GET_LINK_STATUS_DATALEN_V1 32
11008
11009 /* Get link status response data structure, also used for Link Status Event */
11010 struct ice_aqc_get_link_status_data {
11011 uint8_t topo_media_conflict;
11012 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
11013 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
11014 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
11015 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
11016 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
11017 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
11018 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
11019 uint8_t link_cfg_err;
11020 #define ICE_AQ_LINK_CFG_ERR BIT(0)
11021 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
11022 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
11023 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
11024 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
11025 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
11026 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
11027 uint8_t link_info;
11028 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
11029 #define ICE_AQ_LINK_FAULT BIT(1)
11030 #define ICE_AQ_LINK_FAULT_TX BIT(2)
11031 #define ICE_AQ_LINK_FAULT_RX BIT(3)
11032 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
11033 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
11034 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
11035 #define ICE_AQ_SIGNAL_DETECT BIT(7)
11036 uint8_t an_info;
11037 #define ICE_AQ_AN_COMPLETED BIT(0)
11038 #define ICE_AQ_LP_AN_ABILITY BIT(1)
11039 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
11040 #define ICE_AQ_FEC_EN BIT(3)
11041 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
11042 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
11043 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
11044 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
11045 uint8_t ext_info;
11046 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
11047 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
11048 /* Port Tx Suspended */
11049 #define ICE_AQ_LINK_TX_S 2
11050 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
11051 #define ICE_AQ_LINK_TX_ACTIVE 0
11052 #define ICE_AQ_LINK_TX_DRAINED 1
11053 #define ICE_AQ_LINK_TX_FLUSHED 3
11054 uint8_t lb_status;
11055 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
11056 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
11057 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
11058 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
11059 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
11060 uint16_t max_frame_size;
11061 uint8_t cfg;
11062 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
11063 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
11064 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
11065 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
11066 /* Pacing Config */
11067 #define ICE_AQ_CFG_PACING_S 3
11068 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
11069 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
11070 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
11071 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
11072 /* External Device Power Ability */
11073 uint8_t power_desc;
11074 #define ICE_AQ_PWR_CLASS_M 0x3F
11075 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
11076 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
11077 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
11078 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
11079 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
11080 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
11081 uint16_t link_speed;
11082 #define ICE_AQ_LINK_SPEED_M 0x7FF
11083 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
11084 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
11085 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
11086 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
11087 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
11088 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
11089 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
11090 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
11091 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
11092 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
11093 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
11094 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
11095 uint32_t reserved3; /* Aligns next field to 8-byte boundary */
11096 uint64_t phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
11097 uint64_t phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
11098 };
11099
11100 /* Set event mask command (direct 0x0613) */
11101 struct ice_aqc_set_event_mask {
11102 uint8_t lport_num;
11103 uint8_t reserved[7];
11104 uint16_t event_mask;
11105 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
11106 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
11107 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
11108 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
11109 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
11110 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
11111 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
11112 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
11113 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
11114 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
11115 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
11116 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
11117 uint8_t reserved1[6];
11118 };
11119
11120 /* Set PHY Loopback command (direct 0x0619) */
11121 struct ice_aqc_set_phy_lb {
11122 uint8_t lport_num;
11123 uint8_t lport_num_valid;
11124 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)
11125 uint8_t phy_index;
11126 uint8_t lb_mode;
11127 #define ICE_AQ_PHY_LB_EN BIT(0)
11128 #define ICE_AQ_PHY_LB_TYPE_M BIT(1)
11129 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0
11130 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M
11131 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2)
11132 #define ICE_AQ_PHY_LB_LEVEL_PMD 0
11133 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M
11134 uint8_t reserved2[12];
11135 };
11136
11137 /* Set MAC Loopback command (direct 0x0620) */
11138 struct ice_aqc_set_mac_lb {
11139 uint8_t lb_mode;
11140 #define ICE_AQ_MAC_LB_EN BIT(0)
11141 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
11142 uint8_t reserved[15];
11143 };
11144
11145 /* Get sensor reading (direct 0x0632) */
11146 struct ice_aqc_get_sensor_reading {
11147 uint8_t sensor;
11148 #define ICE_AQC_INT_TEMP_SENSOR 0x0
11149 uint8_t format;
11150 #define ICE_AQC_INT_TEMP_FORMAT 0x0
11151 uint8_t reserved[6];
11152 uint32_t addr_high;
11153 uint32_t addr_low;
11154 };
11155
11156 /* Get sensor reading response (direct 0x0632) */
11157 struct ice_aqc_get_sensor_reading_resp {
11158 union {
11159 uint8_t raw[8];
11160 /* Output data for sensor 0x00, format 0x00 */
11161 struct {
11162 int8_t temp;
11163 uint8_t temp_warning_threshold;
11164 uint8_t temp_critical_threshold;
11165 uint8_t temp_fatal_threshold;
11166 uint8_t reserved[4];
11167 } s0f0;
11168 } data;
11169 };
11170
11171 /* DNL Get Status command (indirect 0x0680)
11172 * Structure used for the response, the command uses the generic
11173 * ice_aqc_generic struct to pass a buffer address to the FW.
11174 */
11175 struct ice_aqc_dnl_get_status {
11176 uint8_t ctx;
11177 uint8_t status;
11178 #define ICE_AQ_DNL_STATUS_IDLE 0x0
11179 #define ICE_AQ_DNL_STATUS_RESERVED 0x1
11180 #define ICE_AQ_DNL_STATUS_STOPPED 0x2
11181 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */
11182 #define ICE_AQ_DNL_SRC_S 3
11183 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S)
11184 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S)
11185 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S)
11186 uint8_t stack_ptr;
11187 #define ICE_AQ_DNL_ST_PTR_S 0x0
11188 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S)
11189 uint8_t engine_flags;
11190 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2)
11191 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3)
11192 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4)
11193 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5)
11194 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6)
11195 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7)
11196 uint16_t pc;
11197 uint16_t activity_id;
11198 uint32_t addr_high;
11199 uint32_t addr_low;
11200 };
11201
11202 struct ice_aqc_dnl_get_status_data {
11203 uint16_t activity_err_code;
11204 uint16_t act_err_code;
11205 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */
11206 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */
11207 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */
11208 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */
11209 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */
11210 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */
11211 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */
11212 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */
11213 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */
11214 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */
11215 uint32_t execution_time; /* in nanoseconds */
11216 uint16_t lib_ver;
11217 uint8_t psto_local_sz;
11218 uint8_t psto_global_sz;
11219 uint8_t stack_sz;
11220 #define ICE_AQ_DNL_STACK_SZ_S 0
11221 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S)
11222 uint8_t port_count;
11223 #define ICE_AQ_DNL_PORT_CNT_S 0
11224 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S)
11225 uint16_t act_cache_cntr;
11226 uint32_t i2c_clk_cntr;
11227 uint32_t mdio_clk_cntr;
11228 uint32_t sb_iosf_clk_cntr;
11229 };
11230
11231 /* DNL run command (direct 0x0681) */
11232 struct ice_aqc_dnl_run_command {
11233 uint8_t reserved0;
11234 uint8_t command;
11235 #define ICE_AQ_DNL_CMD_S 0
11236 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S)
11237 #define ICE_AQ_DNL_CMD_RESET 0x0
11238 #define ICE_AQ_DNL_CMD_RUN 0x1
11239 #define ICE_AQ_DNL_CMD_STEP 0x3
11240 #define ICE_AQ_DNL_CMD_ABORT 0x4
11241 #define ICE_AQ_DNL_CMD_SET_PC 0x7
11242 #define ICE_AQ_DNL_CMD_SRC_S 3
11243 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S)
11244 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0
11245 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1
11246 uint16_t new_pc;
11247 uint8_t reserved1[12];
11248 };
11249
11250 /* DNL call command (indirect 0x0682)
11251 * Struct is used for both command and response
11252 */
11253 struct ice_aqc_dnl_call_command {
11254 uint8_t ctx; /* Used in command, reserved in response */
11255 uint8_t reserved;
11256 uint16_t activity_id;
11257 uint32_t reserved1;
11258 uint32_t addr_high;
11259 uint32_t addr_low;
11260 };
11261
11262 /* DNL call command/response buffer (indirect 0x0682) */
11263 struct ice_aqc_dnl_call {
11264 uint32_t stores[4];
11265 };
11266
11267 /* Used for both commands:
11268 * DNL read sto command (indirect 0x0683)
11269 * DNL write sto command (indirect 0x0684)
11270 */
11271 struct ice_aqc_dnl_read_write_command {
11272 uint8_t ctx;
11273 uint8_t sto_sel; /* STORE select */
11274 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0
11275 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1
11276 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2
11277 uint16_t offset;
11278 uint32_t data; /* Used for write sto only */
11279 uint32_t addr_high; /* Used for read sto only */
11280 uint32_t addr_low; /* Used for read sto only */
11281 };
11282
11283 /* Used for both command responses:
11284 * DNL read sto response (indirect 0x0683)
11285 * DNL write sto response (indirect 0x0684)
11286 */
11287 struct ice_aqc_dnl_read_write_response {
11288 uint8_t reserved;
11289 uint8_t status; /* Reserved for read command */
11290 uint16_t size; /* Reserved for write command */
11291 uint32_t data; /* Reserved for write command */
11292 uint32_t addr_high; /* Reserved for write command */
11293 uint32_t addr_low; /* Reserved for write command */
11294 };
11295
11296 /* DNL set breakpoints command (indirect 0x0686) */
11297 struct ice_aqc_dnl_set_breakpoints_command {
11298 uint32_t reserved[2];
11299 uint32_t addr_high;
11300 uint32_t addr_low;
11301 };
11302
11303 /* DNL set breakpoints data buffer structure (indirect 0x0686) */
11304 struct ice_aqc_dnl_set_breakpoints {
11305 uint8_t ctx;
11306 uint8_t ena; /* 0- disabled, 1- enabled */
11307 uint16_t offset;
11308 uint16_t activity_id;
11309 };
11310
11311 /* DNL read log data command(indirect 0x0687) */
11312 struct ice_aqc_dnl_read_log_command {
11313 uint16_t reserved0;
11314 uint16_t offset;
11315 uint32_t reserved1;
11316 uint32_t addr_high;
11317 uint32_t addr_low;
11318
11319 };
11320
11321 /* DNL read log data response(indirect 0x0687) */
11322 struct ice_aqc_dnl_read_log_response {
11323 uint16_t reserved;
11324 uint16_t size;
11325 uint32_t data;
11326 uint32_t addr_high;
11327 uint32_t addr_low;
11328
11329 };
11330
11331 struct ice_aqc_link_topo_params {
11332 uint8_t lport_num;
11333 uint8_t lport_num_valid;
11334 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
11335 uint8_t node_type_ctx;
11336 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
11337 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
11338 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
11339 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
11340 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
11341 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
11342 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
11343 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
11344 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
11345 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
11346 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
11347 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
11348 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
11349 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
11350 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
11351 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
11352 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
11353 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
11354 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
11355 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
11356 uint8_t index;
11357 };
11358
11359 struct ice_aqc_link_topo_addr {
11360 struct ice_aqc_link_topo_params topo_params;
11361 uint16_t handle;
11362 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
11363 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
11364 /* Used to decode the handle field */
11365 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
11366 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
11367 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
11368 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
11369 /* In case of a Mezzanine type */
11370 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
11371 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
11372 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
11373 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
11374 /* In case of a LOM type */
11375 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
11376 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
11377 };
11378
11379 /* Get Link Topology Handle (direct, 0x06E0) */
11380 struct ice_aqc_get_link_topo {
11381 struct ice_aqc_link_topo_addr addr;
11382 uint8_t node_part_num;
11383 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
11384 uint8_t rsvd[9];
11385 };
11386
11387 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
11388 struct ice_aqc_i2c {
11389 struct ice_aqc_link_topo_addr topo_addr;
11390 uint16_t i2c_addr;
11391 uint8_t i2c_params;
11392 #define ICE_AQC_I2C_DATA_SIZE_S 0
11393 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)
11394 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
11395 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0
11396 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M
11397 #define ICE_AQC_I2C_DATA_OFFSET_S 5
11398 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
11399 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
11400 uint8_t rsvd;
11401 uint16_t i2c_bus_addr;
11402 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F
11403 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF
11404 uint8_t i2c_data[4]; /* Used only by write command, reserved in read. */
11405 };
11406
11407 /* Read I2C Response (direct, 0x06E2) */
11408 struct ice_aqc_read_i2c_resp {
11409 uint8_t i2c_data[16];
11410 };
11411
11412 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */
11413 struct ice_aqc_mdio {
11414 struct ice_aqc_link_topo_addr topo_addr;
11415 uint8_t mdio_device_addr;
11416 #define ICE_AQC_MDIO_DEV_S 0
11417 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S)
11418 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5)
11419 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6)
11420 uint8_t mdio_bus_address;
11421 #define ICE_AQC_MDIO_BUS_ADDR_S 0
11422 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S)
11423 uint16_t offset;
11424 uint16_t data; /* Input in write cmd, output in read cmd. */
11425 uint8_t rsvd1[4];
11426 };
11427
11428 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */
11429 struct ice_aqc_gpio_by_func {
11430 struct ice_aqc_link_topo_addr topo_addr;
11431 uint8_t io_func_num;
11432 #define ICE_AQC_GPIO_FUNC_S 0
11433 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S)
11434 uint8_t io_value; /* Input in write cmd, output in read cmd. */
11435 #define ICE_AQC_GPIO_ON BIT(0)
11436 #define ICE_AQC_GPIO_OFF 0
11437 uint8_t rsvd[8];
11438 };
11439
11440 /* Set LED (direct, 0x06E8) */
11441 struct ice_aqc_set_led {
11442 struct ice_aqc_link_topo_addr topo_addr;
11443 uint8_t color_and_blink;
11444 #define ICE_AQC_LED_COLOR_S 0
11445 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S)
11446 #define ICE_AQC_LED_COLOR_SKIP 0
11447 #define ICE_AQC_LED_COLOR_RED 1
11448 #define ICE_AQC_LED_COLOR_ORANGE 2
11449 #define ICE_AQC_LED_COLOR_YELLOW 3
11450 #define ICE_AQC_LED_COLOR_GREEN 4
11451 #define ICE_AQC_LED_COLOR_BLUE 5
11452 #define ICE_AQC_LED_COLOR_PURPLE 6
11453 #define ICE_AQC_LED_BLINK_S 3
11454 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S)
11455 #define ICE_AQC_LED_BLINK_NONE 0
11456 #define ICE_AQC_LED_BLINK_SLOW 1
11457 #define ICE_AQC_LED_BLINK_SLOW_MAC 2
11458 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3
11459 #define ICE_AQC_LED_BLINK_FAST 5
11460 #define ICE_AQC_LED_BLINK_FAST_MAC 6
11461 #define ICE_AQC_LED_BLINK_FAST_FLTR 7
11462 uint8_t rsvd[9];
11463 };
11464
11465 /* Set Port Identification LED (direct, 0x06E9) */
11466 struct ice_aqc_set_port_id_led {
11467 uint8_t lport_num;
11468 uint8_t lport_num_valid;
11469 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
11470 uint8_t ident_mode;
11471 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
11472 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
11473 uint8_t rsvd[13];
11474 };
11475
11476 /* Get Port Options (indirect, 0x06EA) */
11477 struct ice_aqc_get_port_options {
11478 uint8_t lport_num;
11479 uint8_t lport_num_valid;
11480 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0)
11481 uint8_t port_options_count;
11482 #define ICE_AQC_PORT_OPT_COUNT_S 0
11483 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S)
11484 #define ICE_AQC_PORT_OPT_MAX 16
11485 uint8_t innermost_phy_index;
11486 uint8_t port_options;
11487 #define ICE_AQC_PORT_OPT_ACTIVE_S 0
11488 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S)
11489 #define ICE_AQC_PORT_OPT_FORCED BIT(6)
11490 #define ICE_AQC_PORT_OPT_VALID BIT(7)
11491 uint8_t pending_port_option_status;
11492 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0
11493 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S)
11494 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)
11495 uint8_t rsvd[2];
11496 uint32_t addr_high;
11497 uint32_t addr_low;
11498 };
11499
11500 struct ice_aqc_get_port_options_elem {
11501 uint8_t pmd;
11502 #define ICE_AQC_PORT_INV_PORT_OPT 4
11503 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0
11504 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S)
11505 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4
11506 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S)
11507 uint8_t max_lane_speed;
11508 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0
11509 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S)
11510 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0
11511 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1
11512 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2
11513 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3
11514 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4
11515 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5
11516 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6
11517 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7
11518 uint8_t global_scid[2];
11519 uint8_t phy_scid[2];
11520 uint8_t pf2port_cid[2];
11521 };
11522
11523 /* Set Port Option (direct, 0x06EB) */
11524 struct ice_aqc_set_port_option {
11525 uint8_t lport_num;
11526 uint8_t lport_num_valid;
11527 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0)
11528 uint8_t selected_port_option;
11529 uint8_t rsvd[13];
11530 };
11531
11532 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
11533 struct ice_aqc_gpio {
11534 uint16_t gpio_ctrl_handle;
11535 #define ICE_AQC_GPIO_HANDLE_S 0
11536 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
11537 uint8_t gpio_num;
11538 uint8_t gpio_val;
11539 uint8_t rsvd[12];
11540 };
11541
11542 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
11543 struct ice_aqc_sff_eeprom {
11544 uint8_t lport_num;
11545 uint8_t lport_num_valid;
11546 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
11547 uint16_t i2c_bus_addr;
11548 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
11549 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
11550 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
11551 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
11552 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
11553 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
11554 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
11555 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
11556 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
11557 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
11558 #define ICE_AQC_SFF_IS_WRITE BIT(15)
11559 uint16_t i2c_mem_addr;
11560 uint16_t eeprom_page;
11561 #define ICE_AQC_SFF_EEPROM_BANK_S 0
11562 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
11563 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
11564 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
11565 uint32_t addr_high;
11566 uint32_t addr_low;
11567 };
11568
11569 /* SW Set GPIO command (indirect 0x6EF)
11570 * SW Get GPIO command (indirect 0x6F0)
11571 */
11572 struct ice_aqc_sw_gpio {
11573 uint16_t gpio_ctrl_handle;
11574 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
11575 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
11576 uint8_t gpio_num;
11577 #define ICE_AQC_SW_GPIO_NUMBER_S 0
11578 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
11579 uint8_t gpio_params;
11580 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
11581 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
11582 uint8_t rsvd[12];
11583 };
11584
11585 /* Program Topology Device NVM (direct, 0x06F2) */
11586 struct ice_aqc_prog_topo_dev_nvm {
11587 struct ice_aqc_link_topo_params topo_params;
11588 uint8_t rsvd[12];
11589 };
11590
11591 /* Read Topology Device NVM (direct, 0x06F3) */
11592 struct ice_aqc_read_topo_dev_nvm {
11593 struct ice_aqc_link_topo_params topo_params;
11594 uint32_t start_address;
11595 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8
11596 uint8_t data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE];
11597 };
11598
11599 /* NVM Read command (indirect 0x0701)
11600 * NVM Erase commands (direct 0x0702)
11601 * NVM Write commands (indirect 0x0703)
11602 * NVM Write Activate commands (direct 0x0707)
11603 * NVM Shadow RAM Dump commands (direct 0x0707)
11604 */
11605 struct ice_aqc_nvm {
11606 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
11607 uint16_t offset_low;
11608 uint8_t offset_high; /* For Write Activate offset_high is used as flags2 */
11609 uint8_t cmd_flags;
11610 #define ICE_AQC_NVM_LAST_CMD BIT(0)
11611 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
11612 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
11613 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
11614 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
11615 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
11616 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
11617 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
11618 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
11619 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
11620 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
11621 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
11622 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
11623 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
11624 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
11625 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */
11626 #define ICE_AQC_NVM_POR_FLAG 0
11627 #define ICE_AQC_NVM_PERST_FLAG 1
11628 #define ICE_AQC_NVM_EMPR_FLAG 2
11629 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
11630 /* For Write Activate, several flags are sent as part of a separate
11631 * flags2 field using a separate byte. For simplicity of the software
11632 * interface, we pass the flags as a 16 bit value so these flags are
11633 * all offset by 8 bits
11634 */
11635 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
11636 uint16_t module_typeid;
11637 uint16_t length;
11638 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
11639 uint32_t addr_high;
11640 uint32_t addr_low;
11641 };
11642
11643 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
11644 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
11645 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
11646
11647 #define ICE_AQC_NVM_START_POINT 0
11648 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
11649 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
11650 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
11651 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
11652 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
11653 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
11654
11655 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
11656 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
11657 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
11658
11659 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
11660 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
11661 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
11662 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
11663 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
11664
11665 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130
11666 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B
11667 #define ICE_AQC_NVM_CMPO_MOD_ID 0x153
11668
11669 /* Cage Max Power override NVM module */
11670 struct ice_aqc_nvm_cmpo {
11671 uint16_t length;
11672 #define ICE_AQC_NVM_CMPO_ENABLE BIT(8)
11673 uint16_t cages_cfg[8];
11674 };
11675
11676 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
11677 * type field is excluded from the section when reading and writing from
11678 * a module using the module_typeid field with these AQ commands.
11679 */
11680 struct ice_aqc_nvm_minsrev {
11681 uint16_t length;
11682 uint16_t validity;
11683 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0)
11684 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1)
11685 uint16_t nvm_minsrev_l;
11686 uint16_t nvm_minsrev_h;
11687 uint16_t orom_minsrev_l;
11688 uint16_t orom_minsrev_h;
11689 };
11690
11691 struct ice_aqc_nvm_tx_topo_user_sel {
11692 uint16_t length;
11693 uint8_t data;
11694 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)
11695 uint8_t reserved;
11696 };
11697
11698 /* Used for 0x0704 as well as for 0x0705 commands */
11699 struct ice_aqc_nvm_cfg {
11700 uint8_t cmd_flags;
11701 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
11702 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
11703 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
11704 uint8_t reserved;
11705 uint16_t count;
11706 uint16_t id;
11707 uint8_t reserved1[2];
11708 uint32_t addr_high;
11709 uint32_t addr_low;
11710 };
11711
11712 struct ice_aqc_nvm_cfg_data {
11713 uint16_t field_id;
11714 uint16_t field_options;
11715 uint16_t field_value;
11716 };
11717
11718 /* NVM Checksum Command (direct, 0x0706) */
11719 struct ice_aqc_nvm_checksum {
11720 uint8_t flags;
11721 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
11722 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
11723 uint8_t rsvd;
11724 uint16_t checksum; /* Used only by response */
11725 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
11726 uint8_t rsvd2[12];
11727 };
11728
11729 /*
11730 * Send to PF command (indirect 0x0801) ID is only used by PF
11731 *
11732 * Send to VF command (indirect 0x0802) ID is only used by PF
11733 *
11734 */
11735 struct ice_aqc_pf_vf_msg {
11736 uint32_t id;
11737 uint32_t reserved;
11738 uint32_t addr_high;
11739 uint32_t addr_low;
11740 };
11741
11742 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */
11743 struct ice_aqc_read_write_alt_direct {
11744 uint32_t dword0_addr;
11745 uint32_t dword0_value;
11746 uint32_t dword1_addr;
11747 uint32_t dword1_value;
11748 };
11749
11750 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */
11751 struct ice_aqc_read_write_alt_indirect {
11752 uint32_t base_dword_addr;
11753 uint32_t num_dwords;
11754 uint32_t addr_high;
11755 uint32_t addr_low;
11756 };
11757
11758 /* Done Alternate Write (direct 0x0904) */
11759 struct ice_aqc_done_alt_write {
11760 uint8_t flags;
11761 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0)
11762 #define ICE_AQC_RESP_RESET_NEEDED BIT(1)
11763 uint8_t reserved[15];
11764 };
11765
11766 /* Clear Port Alternate Write (direct 0x0906) */
11767 struct ice_aqc_clear_port_alt_write {
11768 uint8_t reserved[16];
11769 };
11770
11771 /* Get LLDP MIB (indirect 0x0A00)
11772 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
11773 * as the format is the same.
11774 */
11775 struct ice_aqc_lldp_get_mib {
11776 uint8_t type;
11777 #define ICE_AQ_LLDP_MIB_TYPE_S 0
11778 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
11779 #define ICE_AQ_LLDP_MIB_LOCAL 0
11780 #define ICE_AQ_LLDP_MIB_REMOTE 1
11781 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
11782 #define ICE_AQ_LLDP_BRID_TYPE_S 2
11783 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
11784 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
11785 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
11786 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
11787 #define ICE_AQ_LLDP_TX_S 0x4
11788 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
11789 #define ICE_AQ_LLDP_TX_ACTIVE 0
11790 #define ICE_AQ_LLDP_TX_SUSPENDED 1
11791 #define ICE_AQ_LLDP_TX_FLUSHED 3
11792 /* DCBX mode */
11793 #define ICE_AQ_LLDP_DCBX_S 6
11794 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S)
11795 #define ICE_AQ_LLDP_DCBX_NA 0
11796 #define ICE_AQ_LLDP_DCBX_CEE 1
11797 #define ICE_AQ_LLDP_DCBX_IEEE 2
11798 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
11799 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
11800 * Get LLDP MIB (0x0A00) response only.
11801 */
11802 uint8_t state;
11803 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0
11804 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \
11805 (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S)
11806 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0
11807 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1
11808 uint16_t local_len;
11809 uint16_t remote_len;
11810 uint8_t reserved[2];
11811 uint32_t addr_high;
11812 uint32_t addr_low;
11813 };
11814
11815 /* Configure LLDP MIB Change Event (direct 0x0A01) */
11816 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
11817 struct ice_aqc_lldp_set_mib_change {
11818 uint8_t command;
11819 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
11820 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
11821 #define ICE_AQ_LLDP_MIB_PENDING_S 1
11822 #define ICE_AQ_LLDP_MIB_PENDING_M \
11823 (0x1 << ICE_AQ_LLDP_MIB_PENDING_S)
11824 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0
11825 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1
11826 uint8_t reserved[15];
11827 };
11828
11829 /* Add LLDP TLV (indirect 0x0A02)
11830 * Delete LLDP TLV (indirect 0x0A04)
11831 */
11832 struct ice_aqc_lldp_add_delete_tlv {
11833 uint8_t type; /* only nearest bridge and non-TPMR from 0x0A00 */
11834 uint8_t reserved1[1];
11835 uint16_t len;
11836 uint8_t reserved2[4];
11837 uint32_t addr_high;
11838 uint32_t addr_low;
11839 };
11840
11841 /* Update LLDP TLV (indirect 0x0A03) */
11842 struct ice_aqc_lldp_update_tlv {
11843 uint8_t type; /* only nearest bridge and non-TPMR from 0x0A00 */
11844 uint8_t reserved;
11845 uint16_t old_len;
11846 uint16_t new_offset;
11847 uint16_t new_len;
11848 uint32_t addr_high;
11849 uint32_t addr_low;
11850 };
11851
11852 /* Stop LLDP (direct 0x0A05) */
11853 struct ice_aqc_lldp_stop {
11854 uint8_t command;
11855 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
11856 #define ICE_AQ_LLDP_AGENT_STOP 0x0
11857 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
11858 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
11859 uint8_t reserved[15];
11860 };
11861
11862 /* Start LLDP (direct 0x0A06) */
11863 struct ice_aqc_lldp_start {
11864 uint8_t command;
11865 #define ICE_AQ_LLDP_AGENT_START BIT(0)
11866 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
11867 uint8_t reserved[15];
11868 };
11869
11870 /* Get CEE DCBX Oper Config (0x0A07)
11871 * The command uses the generic descriptor struct and
11872 * returns the struct below as an indirect response.
11873 */
11874 struct ice_aqc_get_cee_dcb_cfg_resp {
11875 uint8_t oper_num_tc;
11876 uint8_t oper_prio_tc[4];
11877 uint8_t oper_tc_bw[8];
11878 uint8_t oper_pfc_en;
11879 uint16_t oper_app_prio;
11880 #define ICE_AQC_CEE_APP_FCOE_S 0
11881 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
11882 #define ICE_AQC_CEE_APP_ISCSI_S 3
11883 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
11884 #define ICE_AQC_CEE_APP_FIP_S 8
11885 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
11886 uint32_t tlv_status;
11887 #define ICE_AQC_CEE_PG_STATUS_S 0
11888 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
11889 #define ICE_AQC_CEE_PFC_STATUS_S 3
11890 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
11891 #define ICE_AQC_CEE_FCOE_STATUS_S 8
11892 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
11893 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
11894 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
11895 #define ICE_AQC_CEE_FIP_STATUS_S 16
11896 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
11897 uint8_t reserved[12];
11898 };
11899
11900 /* Set Local LLDP MIB (indirect 0x0A08)
11901 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
11902 */
11903 struct ice_aqc_lldp_set_local_mib {
11904 uint8_t type;
11905 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
11906 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
11907 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
11908 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
11909 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
11910 uint8_t reserved0;
11911 uint16_t length;
11912 uint8_t reserved1[4];
11913 uint32_t addr_high;
11914 uint32_t addr_low;
11915 };
11916
11917 struct ice_aqc_lldp_set_local_mib_resp {
11918 uint8_t status;
11919 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
11920 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
11921 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
11922 uint8_t reserved[15];
11923 };
11924
11925 /* Stop/Start LLDP Agent (direct 0x0A09)
11926 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
11927 * The same structure is used for the response, with the command field
11928 * being used as the status field.
11929 */
11930 struct ice_aqc_lldp_stop_start_specific_agent {
11931 uint8_t command;
11932 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
11933 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
11934 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
11935 uint8_t reserved[15];
11936 };
11937
11938 /* LLDP Filter Control (direct 0x0A0A) */
11939 struct ice_aqc_lldp_filter_ctrl {
11940 uint8_t cmd_flags;
11941 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
11942 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
11943 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
11944 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
11945 uint8_t reserved1;
11946 uint16_t vsi_num;
11947 uint8_t reserved2[12];
11948 };
11949
11950 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
11951 struct ice_aqc_get_set_rss_key {
11952 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
11953 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
11954 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
11955 uint16_t vsi_id;
11956 uint8_t reserved[6];
11957 uint32_t addr_high;
11958 uint32_t addr_low;
11959 };
11960
11961 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
11962 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
11963 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
11964 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
11965 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
11966
11967 /**
11968 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
11969 * @standard_rss_key: 40 most significant bytes of hash key
11970 * @extended_hash_key: 12 least significant bytes of hash key
11971 *
11972 * Set/Get 40 byte hash key using standard_rss_key field, and set
11973 * extended_hash_key field to zero. Set/Get 52 byte hash key using
11974 * standard_rss_key field for 40 most significant bytes and the
11975 * extended_hash_key field for the 12 least significant bytes of hash key.
11976 */
11977 struct ice_aqc_get_set_rss_keys {
11978 uint8_t standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
11979 uint8_t extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
11980 };
11981
11982 enum ice_lut_type {
11983 ICE_LUT_VSI = 0,
11984 ICE_LUT_PF = 1,
11985 ICE_LUT_GLOBAL = 2,
11986 ICE_LUT_TYPE_MASK = 3,
11987 ICE_LUT_PF_SMALL = 5, /* yields ICE_LUT_PF when &= ICE_LUT_TYPE_MASK */
11988 };
11989
11990 enum ice_lut_size {
11991 ICE_LUT_VSI_SIZE = 64,
11992 ICE_LUT_PF_SMALL_SIZE = 128,
11993 ICE_LUT_GLOBAL_SIZE = 512,
11994 ICE_LUT_PF_SIZE = 2048,
11995 };
11996
11997 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
11998 struct ice_aqc_get_set_rss_lut {
11999 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
12000 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
12001 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
12002 uint16_t vsi_id;
12003 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
12004 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
12005 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
12006
12007 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
12008 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
12009 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
12010
12011 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
12012 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
12013
12014 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
12015 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
12016 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
12017
12018 uint16_t flags;
12019 uint32_t reserved;
12020 uint32_t addr_high;
12021 uint32_t addr_low;
12022 };
12023
12024 /* Add Tx LAN Queues (indirect 0x0C30) */
12025 struct ice_aqc_add_txqs {
12026 uint8_t num_qgrps;
12027 uint8_t reserved[3];
12028 uint32_t reserved1;
12029 uint32_t addr_high;
12030 uint32_t addr_low;
12031 };
12032
12033 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
12034 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
12035 */
12036 struct ice_aqc_add_txqs_perq {
12037 uint16_t txq_id;
12038 uint8_t rsvd[2];
12039 uint32_t q_teid;
12040 uint8_t txq_ctx[22];
12041 uint8_t rsvd2[2];
12042 struct ice_aqc_txsched_elem info;
12043 };
12044
12045 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
12046 * is an array of the following structs. Please note that the length of
12047 * each struct ice_aqc_add_tx_qgrp is variable due
12048 * to the variable number of queues in each group!
12049 */
12050 struct ice_aqc_add_tx_qgrp {
12051 uint32_t parent_teid;
12052 uint8_t num_txqs;
12053 uint8_t rsvd[3];
12054 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
12055 };
12056
12057 /* Disable Tx LAN Queues (indirect 0x0C31) */
12058 struct ice_aqc_dis_txqs {
12059 uint8_t cmd_type;
12060 #define ICE_AQC_Q_DIS_CMD_S 0
12061 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
12062 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
12063 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
12064 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
12065 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
12066 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
12067 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
12068 uint8_t num_entries;
12069 uint16_t vmvf_and_timeout;
12070 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
12071 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
12072 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
12073 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
12074 uint32_t blocked_cgds;
12075 uint32_t addr_high;
12076 uint32_t addr_low;
12077 };
12078
12079 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
12080 * contains the following structures, arrayed one after the
12081 * other.
12082 * Note: Since the q_id is 16 bits wide, if the
12083 * number of queues is even, then 2 bytes of alignment MUST be
12084 * added before the start of the next group, to allow correct
12085 * alignment of the parent_teid field.
12086 */
12087 struct ice_aqc_dis_txq_item {
12088 uint32_t parent_teid;
12089 uint8_t num_qs;
12090 uint8_t rsvd;
12091 /* The length of the q_id array varies according to num_qs */
12092 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
12093 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
12094 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
12095 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
12096 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
12097 uint16_t q_id[STRUCT_HACK_VAR_LEN];
12098 } __packed;
12099
12100 /* Tx LAN Queues Cleanup Event (0x0C31) */
12101 struct ice_aqc_txqs_cleanup {
12102 uint16_t caller_opc;
12103 uint16_t cmd_tag;
12104 uint8_t reserved[12];
12105 };
12106
12107 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
12108 struct ice_aqc_move_txqs {
12109 uint8_t cmd_type;
12110 #define ICE_AQC_Q_CMD_TYPE_S 0
12111 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
12112 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
12113 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
12114 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
12115 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
12116 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
12117 uint8_t num_qs;
12118 uint8_t rsvd;
12119 uint8_t timeout;
12120 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
12121 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
12122 uint32_t blocked_cgds;
12123 uint32_t addr_high;
12124 uint32_t addr_low;
12125 };
12126
12127 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
12128 struct ice_aqc_move_txqs_elem {
12129 uint16_t txq_id;
12130 uint8_t q_cgd;
12131 uint8_t rsvd;
12132 uint32_t q_teid;
12133 };
12134
12135 /* Indirect data buffer for the Move Tx LAN Queues command/response */
12136 struct ice_aqc_move_txqs_data {
12137 uint32_t src_teid;
12138 uint32_t dest_teid;
12139 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
12140 };
12141
12142 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
12143 struct ice_aqc_add_rdma_qset {
12144 uint8_t num_qset_grps;
12145 uint8_t reserved[7];
12146 uint32_t addr_high;
12147 uint32_t addr_low;
12148 };
12149
12150 /* This is the descriptor of each qset entry for the Add Tx RDMA Queue Set
12151 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
12152 */
12153 struct ice_aqc_add_tx_rdma_qset_entry {
12154 uint16_t tx_qset_id;
12155 uint8_t rsvd[2];
12156 uint32_t qset_teid;
12157 struct ice_aqc_txsched_elem info;
12158 };
12159
12160 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
12161 * is an array of the following structs. Please note that the length of
12162 * each struct ice_aqc_add_rdma_qset is variable due to the variable
12163 * number of queues in each group!
12164 */
12165 struct ice_aqc_add_rdma_qset_data {
12166 uint32_t parent_teid;
12167 uint16_t num_qsets;
12168 uint8_t rsvd[2];
12169 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[STRUCT_HACK_VAR_LEN];
12170 };
12171
12172 /* Move RDMA Queue Set (indirect 0x0C34) */
12173 struct ice_aqc_move_rdma_qset_cmd {
12174 uint8_t num_rdma_qset; /* Used by commands and response */
12175 #define ICE_AQC_PF_MODE_SAME_PF 0x0
12176 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1
12177 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2
12178 uint8_t flags;
12179 uint8_t reserved[6];
12180 uint32_t addr_high;
12181 uint32_t addr_low;
12182 };
12183
12184 /* Buffer */
12185 struct ice_aqc_move_rdma_qset_buffer_desc {
12186 uint16_t tx_qset_id;
12187 uint16_t qset_teid;
12188 };
12189
12190 struct ice_aqc_move_rdma_qset_buffer {
12191 uint32_t src_parent_teid;
12192 uint32_t dest_parent_teid;
12193 struct ice_aqc_move_rdma_qset_buffer_desc descs[STRUCT_HACK_VAR_LEN];
12194 };
12195
12196 /* Download Package (indirect 0x0C40) */
12197 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
12198 struct ice_aqc_download_pkg {
12199 uint8_t flags;
12200 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
12201 uint8_t reserved[3];
12202 uint32_t reserved1;
12203 uint32_t addr_high;
12204 uint32_t addr_low;
12205 };
12206
12207 struct ice_aqc_download_pkg_resp {
12208 uint32_t error_offset;
12209 uint32_t error_info;
12210 uint32_t addr_high;
12211 uint32_t addr_low;
12212 };
12213
12214 /* Get Package Info List (indirect 0x0C43) */
12215 struct ice_aqc_get_pkg_info_list {
12216 uint32_t reserved1;
12217 uint32_t reserved2;
12218 uint32_t addr_high;
12219 uint32_t addr_low;
12220 };
12221
12222 /* Version format for packages */
12223 struct ice_pkg_ver {
12224 uint8_t major;
12225 uint8_t minor;
12226 uint8_t update;
12227 uint8_t draft;
12228 };
12229
12230 #define ICE_PKG_NAME_SIZE 32
12231 #define ICE_SEG_ID_SIZE 28
12232 #define ICE_SEG_NAME_SIZE 28
12233
12234 struct ice_aqc_get_pkg_info {
12235 struct ice_pkg_ver ver;
12236 char name[ICE_SEG_NAME_SIZE];
12237 uint32_t track_id;
12238 uint8_t is_in_nvm;
12239 uint8_t is_active;
12240 uint8_t is_active_at_boot;
12241 uint8_t is_modified;
12242 };
12243
12244 /* Get Package Info List response buffer format (0x0C43) */
12245 struct ice_aqc_get_pkg_info_resp {
12246 uint32_t count;
12247 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
12248 };
12249
12250 /* Driver Shared Parameters (direct, 0x0C90) */
12251 struct ice_aqc_driver_shared_params {
12252 uint8_t set_or_get_op;
12253 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
12254 #define ICE_AQC_DRIVER_PARAM_SET ((uint8_t)0)
12255 #define ICE_AQC_DRIVER_PARAM_GET ((uint8_t)1)
12256 uint8_t param_indx;
12257 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
12258 uint8_t rsvd[2];
12259 uint32_t param_val;
12260 uint32_t addr_high;
12261 uint32_t addr_low;
12262 };
12263
12264 /* Lan Queue Overflow Event (direct, 0x1001) */
12265 struct ice_aqc_event_lan_overflow {
12266 uint32_t prtdcb_ruptq;
12267 uint32_t qtx_ctl;
12268 uint8_t reserved[8];
12269 };
12270
12271 /* Debug Dump Internal Data (indirect 0xFF08) */
12272 struct ice_aqc_debug_dump_internals {
12273 uint16_t cluster_id; /* Expresses next cluster ID in response */
12274 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
12275 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
12276 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
12277 /* EMP_DRAM only dumpable in device debug mode */
12278 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
12279 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
12280 /* AUX_REGS only dumpable in device debug mode */
12281 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
12282 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
12283 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
12284 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9
12285 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21
12286 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS 22
12287 uint16_t table_id; /* Used only for non-memory clusters */
12288 uint32_t idx; /* In table entries for tables, in bytes for memory */
12289 uint32_t addr_high;
12290 uint32_t addr_low;
12291 };
12292
12293 enum ice_aqc_fw_logging_mod {
12294 ICE_AQC_FW_LOG_ID_GENERAL = 0,
12295 ICE_AQC_FW_LOG_ID_CTRL,
12296 ICE_AQC_FW_LOG_ID_LINK,
12297 ICE_AQC_FW_LOG_ID_LINK_TOPO,
12298 ICE_AQC_FW_LOG_ID_DNL,
12299 ICE_AQC_FW_LOG_ID_I2C,
12300 ICE_AQC_FW_LOG_ID_SDP,
12301 ICE_AQC_FW_LOG_ID_MDIO,
12302 ICE_AQC_FW_LOG_ID_ADMINQ,
12303 ICE_AQC_FW_LOG_ID_HDMA,
12304 ICE_AQC_FW_LOG_ID_LLDP,
12305 ICE_AQC_FW_LOG_ID_DCBX,
12306 ICE_AQC_FW_LOG_ID_DCB,
12307 ICE_AQC_FW_LOG_ID_XLR,
12308 ICE_AQC_FW_LOG_ID_NVM,
12309 ICE_AQC_FW_LOG_ID_AUTH,
12310 ICE_AQC_FW_LOG_ID_VPD,
12311 ICE_AQC_FW_LOG_ID_IOSF,
12312 ICE_AQC_FW_LOG_ID_PARSER,
12313 ICE_AQC_FW_LOG_ID_SW,
12314 ICE_AQC_FW_LOG_ID_SCHEDULER,
12315 ICE_AQC_FW_LOG_ID_TXQ,
12316 ICE_AQC_FW_LOG_ID_RSVD,
12317 ICE_AQC_FW_LOG_ID_POST,
12318 ICE_AQC_FW_LOG_ID_WATCHDOG,
12319 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
12320 ICE_AQC_FW_LOG_ID_MNG,
12321 ICE_AQC_FW_LOG_ID_SYNCE,
12322 ICE_AQC_FW_LOG_ID_HEALTH,
12323 ICE_AQC_FW_LOG_ID_TSDRV,
12324 ICE_AQC_FW_LOG_ID_PFREG,
12325 ICE_AQC_FW_LOG_ID_MDLVER,
12326 ICE_AQC_FW_LOG_ID_MAX,
12327 };
12328
12329 /* Set Health Status (direct 0xFF20) */
12330 struct ice_aqc_set_health_status_config {
12331 uint8_t event_source;
12332 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
12333 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
12334 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
12335 uint8_t reserved[15];
12336 };
12337
12338 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
12339 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
12340 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
12341 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
12342 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
12343 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
12344 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
12345 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
12346 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109
12347 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
12348 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
12349 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
12350 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
12351 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
12352 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
12353 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
12354 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
12355 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
12356 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
12357 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
12358 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
12359 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120
12360 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121
12361 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
12362 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
12363 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
12364 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
12365 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
12366 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
12367 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
12368 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507
12369 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508
12370 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
12371 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A
12372 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B
12373 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C
12374 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D
12375 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000
12376 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001
12377 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002
12378
12379 /* Get Health Status codes (indirect 0xFF21) */
12380 struct ice_aqc_get_supported_health_status_codes {
12381 uint16_t health_code_count;
12382 uint8_t reserved[6];
12383 uint32_t addr_high;
12384 uint32_t addr_low;
12385 };
12386
12387 /* Get Health Status (indirect 0xFF22) */
12388 struct ice_aqc_get_health_status {
12389 uint16_t health_status_count;
12390 uint8_t reserved[6];
12391 uint32_t addr_high;
12392 uint32_t addr_low;
12393 };
12394
12395 /* Get Health Status event buffer entry, (0xFF22)
12396 * repeated per reported health status
12397 */
12398 struct ice_aqc_health_status_elem {
12399 uint16_t health_status_code;
12400 uint16_t event_source;
12401 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
12402 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
12403 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
12404 uint32_t internal_data1;
12405 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
12406 uint32_t internal_data2;
12407 };
12408
12409 /* Clear Health Status (direct 0xFF23) */
12410 struct ice_aqc_clear_health_status {
12411 uint32_t reserved[4];
12412 };
12413
12414 /* Set FW Logging configuration (indirect 0xFF30)
12415 * Register for FW Logging (indirect 0xFF31)
12416 * Query FW Logging (indirect 0xFF32)
12417 * FW Log Event (indirect 0xFF33)
12418 * Get FW Log (indirect 0xFF34)
12419 * Clear FW Log (indirect 0xFF35)
12420 */
12421 struct ice_aqc_fw_log {
12422 uint8_t cmd_flags;
12423 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
12424 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
12425 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)
12426 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
12427 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
12428 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
12429 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
12430 uint8_t rsp_flag;
12431 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
12432 uint16_t fw_rt_msb;
12433 union {
12434 struct {
12435 uint32_t fw_rt_lsb;
12436 } sync;
12437 struct {
12438 uint16_t log_resolution;
12439 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1)
12440 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128)
12441 uint16_t mdl_cnt;
12442 } cfg;
12443 } ops;
12444 uint32_t addr_high;
12445 uint32_t addr_low;
12446 };
12447
12448 /* Response Buffer for:
12449 * Set Firmware Logging Configuration (0xFF30)
12450 * Query FW Logging (0xFF32)
12451 */
12452 struct ice_aqc_fw_log_cfg_resp {
12453 uint16_t module_identifier;
12454 uint8_t log_level;
12455 uint8_t rsvd0;
12456 };
12457
12458 struct ice_aq_get_set_rss_lut_params {
12459 uint16_t vsi_handle; /* software VSI handle */
12460 uint16_t lut_size; /* size of the LUT buffer */
12461 uint8_t lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
12462 uint8_t *lut; /* input RSS LUT for set / output for get */
12463 uint8_t global_lut_id; /* only valid when lut_type is global */
12464 };
12465
12466 /**
12467 * struct ice_aq_desc - Admin Queue (AQ) descriptor
12468 * @flags: ICE_AQ_FLAG_* flags
12469 * @opcode: AQ command opcode
12470 * @datalen: length in bytes of indirect/external data buffer
12471 * @retval: return value from firmware
12472 * @cookie_high: opaque data high-half
12473 * @cookie_low: opaque data low-half
12474 * @params: command-specific parameters
12475 *
12476 * Descriptor format for commands the driver posts on the Admin Transmit Queue
12477 * (ATQ). The firmware writes back onto the command descriptor and returns
12478 * the result of the command. Asynchronous events that are not an immediate
12479 * result of the command are written to the Admin Receive Queue (ARQ) using
12480 * the same descriptor format. Descriptors are in little-endian notation with
12481 * 32-bit words.
12482 */
12483 struct ice_aq_desc {
12484 uint16_t flags;
12485 uint16_t opcode;
12486 uint16_t datalen;
12487 uint16_t retval;
12488 uint32_t cookie_high;
12489 uint32_t cookie_low;
12490 union {
12491 uint8_t raw[16];
12492 struct ice_aqc_generic generic;
12493 struct ice_aqc_get_ver get_ver;
12494 struct ice_aqc_driver_ver driver_ver;
12495 struct ice_aqc_q_shutdown q_shutdown;
12496 struct ice_aqc_get_exp_err exp_err;
12497 struct ice_aqc_req_res res_owner;
12498 struct ice_aqc_manage_mac_read mac_read;
12499 struct ice_aqc_manage_mac_write mac_write;
12500 struct ice_aqc_clear_pxe clear_pxe;
12501 struct ice_aqc_config_no_drop_policy no_drop;
12502 struct ice_aqc_add_update_mir_rule add_update_rule;
12503 struct ice_aqc_delete_mir_rule del_rule;
12504 struct ice_aqc_list_caps get_cap;
12505 struct ice_aqc_get_phy_caps get_phy;
12506 struct ice_aqc_set_phy_cfg set_phy;
12507 struct ice_aqc_restart_an restart_an;
12508 struct ice_aqc_get_sensor_reading get_sensor_reading;
12509 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
12510 struct ice_aqc_dnl_get_status get_status;
12511 struct ice_aqc_dnl_run_command dnl_run;
12512 struct ice_aqc_dnl_call_command dnl_call;
12513 struct ice_aqc_dnl_read_write_command dnl_read_write;
12514 struct ice_aqc_dnl_read_write_response dnl_read_write_resp;
12515 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk;
12516 struct ice_aqc_dnl_read_log_command dnl_read_log;
12517 struct ice_aqc_dnl_read_log_response dnl_read_log_resp;
12518 struct ice_aqc_i2c read_write_i2c;
12519 struct ice_aqc_read_i2c_resp read_i2c_resp;
12520 struct ice_aqc_mdio read_write_mdio;
12521 struct ice_aqc_gpio_by_func read_write_gpio_by_func;
12522 struct ice_aqc_gpio read_write_gpio;
12523 struct ice_aqc_sw_gpio sw_read_write_gpio;
12524 struct ice_aqc_set_led set_led;
12525 struct ice_aqc_mdio read_mdio;
12526 struct ice_aqc_mdio write_mdio;
12527 struct ice_aqc_sff_eeprom read_write_sff_param;
12528 struct ice_aqc_set_port_id_led set_port_id_led;
12529 struct ice_aqc_get_port_options get_port_options;
12530 struct ice_aqc_set_port_option set_port_option;
12531 struct ice_aqc_get_sw_cfg get_sw_conf;
12532 struct ice_aqc_set_port_params set_port_params;
12533 struct ice_aqc_sw_rules sw_rules;
12534 struct ice_aqc_storm_cfg storm_conf;
12535 struct ice_aqc_get_topo get_topo;
12536 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
12537 struct ice_aqc_query_txsched_res query_sched_res;
12538 struct ice_aqc_query_node_to_root query_node_to_root;
12539 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
12540 struct ice_aqc_query_port_ets port_ets;
12541 struct ice_aqc_rl_profile rl_profile;
12542 struct ice_aqc_node_attr node_attr;
12543 struct ice_aqc_nvm nvm;
12544 struct ice_aqc_nvm_cfg nvm_cfg;
12545 struct ice_aqc_nvm_checksum nvm_checksum;
12546 struct ice_aqc_pf_vf_msg virt;
12547 struct ice_aqc_read_write_alt_direct read_write_alt_direct;
12548 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect;
12549 struct ice_aqc_done_alt_write done_alt_write;
12550 struct ice_aqc_clear_port_alt_write clear_port_alt_write;
12551 struct ice_aqc_pfc_ignore pfc_ignore;
12552 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
12553 struct ice_aqc_set_dcb_params set_dcb_params;
12554 struct ice_aqc_lldp_get_mib lldp_get_mib;
12555 struct ice_aqc_lldp_set_mib_change lldp_set_event;
12556 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
12557 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
12558 struct ice_aqc_lldp_stop lldp_stop;
12559 struct ice_aqc_lldp_start lldp_start;
12560 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
12561 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
12562 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
12563 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
12564 struct ice_aqc_get_set_rss_key get_set_rss_key;
12565 struct ice_aqc_add_txqs add_txqs;
12566 struct ice_aqc_dis_txqs dis_txqs;
12567 struct ice_aqc_move_txqs move_txqs;
12568 struct ice_aqc_add_rdma_qset add_rdma_qset;
12569 struct ice_aqc_move_rdma_qset_cmd move_rdma_qset;
12570 struct ice_aqc_txqs_cleanup txqs_cleanup;
12571 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
12572 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
12573 struct ice_aqc_get_vsi_resp get_vsi_resp;
12574 struct ice_aqc_download_pkg download_pkg;
12575 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
12576 struct ice_aqc_driver_shared_params drv_shared_params;
12577 struct ice_aqc_fw_log fw_log;
12578 struct ice_aqc_debug_dump_internals debug_dump;
12579 struct ice_aqc_set_mac_lb set_mac_lb;
12580 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
12581 struct ice_aqc_get_res_alloc get_res;
12582 struct ice_aqc_get_allocd_res_desc get_res_desc;
12583 struct ice_aqc_set_mac_cfg set_mac_cfg;
12584 struct ice_aqc_set_event_mask set_event_mask;
12585 struct ice_aqc_get_link_status get_link_status;
12586 struct ice_aqc_event_lan_overflow lan_overflow;
12587 struct ice_aqc_get_link_topo get_link_topo;
12588 struct ice_aqc_set_health_status_config
12589 set_health_status_config;
12590 struct ice_aqc_get_supported_health_status_codes
12591 get_supported_health_status_codes;
12592 struct ice_aqc_get_health_status get_health_status;
12593 struct ice_aqc_clear_health_status clear_health_status;
12594 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
12595 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
12596 struct ice_aqc_get_set_tx_topo get_set_tx_topo;
12597 } params;
12598 };
12599
12600 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
12601 #define ICE_AQ_LG_BUF 512
12602
12603 /* Flags sub-structure
12604 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
12605 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
12606 */
12607
12608 /* command flags and offsets */
12609 #define ICE_AQ_FLAG_DD_S 0
12610 #define ICE_AQ_FLAG_CMP_S 1
12611 #define ICE_AQ_FLAG_ERR_S 2
12612 #define ICE_AQ_FLAG_VFE_S 3
12613 #define ICE_AQ_FLAG_LB_S 9
12614 #define ICE_AQ_FLAG_RD_S 10
12615 #define ICE_AQ_FLAG_VFC_S 11
12616 #define ICE_AQ_FLAG_BUF_S 12
12617 #define ICE_AQ_FLAG_SI_S 13
12618 #define ICE_AQ_FLAG_EI_S 14
12619 #define ICE_AQ_FLAG_FE_S 15
12620
12621 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
12622 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
12623 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
12624 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
12625 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
12626 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
12627 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
12628 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
12629 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
12630 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
12631 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
12632
12633 /* error codes */
12634 enum ice_aq_err {
12635 ICE_AQ_RC_OK = 0, /* Success */
12636 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
12637 ICE_AQ_RC_ENOENT = 2, /* No such element */
12638 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
12639 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
12640 ICE_AQ_RC_EIO = 5, /* I/O error */
12641 ICE_AQ_RC_ENXIO = 6, /* No such resource */
12642 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
12643 ICE_AQ_RC_EAGAIN = 8, /* Try again */
12644 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
12645 ICE_AQ_RC_EACCES = 10, /* Permission denied */
12646 ICE_AQ_RC_EFAULT = 11, /* Bad address */
12647 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
12648 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
12649 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
12650 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
12651 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
12652 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
12653 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
12654 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
12655 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
12656 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
12657 ICE_AQ_RC_EFBIG = 22, /* File too big */
12658 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
12659 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
12660 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
12661 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
12662 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
12663 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
12664 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
12665 };
12666
12667 /* Admin Queue command opcodes */
12668 enum ice_adminq_opc {
12669 /* AQ commands */
12670 ice_aqc_opc_get_ver = 0x0001,
12671 ice_aqc_opc_driver_ver = 0x0002,
12672 ice_aqc_opc_q_shutdown = 0x0003,
12673 ice_aqc_opc_get_exp_err = 0x0005,
12674
12675 /* resource ownership */
12676 ice_aqc_opc_req_res = 0x0008,
12677 ice_aqc_opc_release_res = 0x0009,
12678
12679 /* device/function capabilities */
12680 ice_aqc_opc_list_func_caps = 0x000A,
12681 ice_aqc_opc_list_dev_caps = 0x000B,
12682
12683 /* manage MAC address */
12684 ice_aqc_opc_manage_mac_read = 0x0107,
12685 ice_aqc_opc_manage_mac_write = 0x0108,
12686
12687 /* PXE */
12688 ice_aqc_opc_clear_pxe_mode = 0x0110,
12689
12690 ice_aqc_opc_config_no_drop_policy = 0x0112,
12691
12692 /* internal switch commands */
12693 ice_aqc_opc_get_sw_cfg = 0x0200,
12694 ice_aqc_opc_set_port_params = 0x0203,
12695
12696 /* Alloc/Free/Get Resources */
12697 ice_aqc_opc_get_res_alloc = 0x0204,
12698 ice_aqc_opc_alloc_res = 0x0208,
12699 ice_aqc_opc_free_res = 0x0209,
12700 ice_aqc_opc_get_allocd_res_desc = 0x020A,
12701 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
12702 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
12703
12704 /* VSI commands */
12705 ice_aqc_opc_add_vsi = 0x0210,
12706 ice_aqc_opc_update_vsi = 0x0211,
12707 ice_aqc_opc_get_vsi_params = 0x0212,
12708 ice_aqc_opc_free_vsi = 0x0213,
12709
12710 /* Mirroring rules - add/update, delete */
12711 ice_aqc_opc_add_update_mir_rule = 0x0260,
12712 ice_aqc_opc_del_mir_rule = 0x0261,
12713
12714 /* storm configuration */
12715 ice_aqc_opc_set_storm_cfg = 0x0280,
12716 ice_aqc_opc_get_storm_cfg = 0x0281,
12717
12718 /* switch rules population commands */
12719 ice_aqc_opc_add_sw_rules = 0x02A0,
12720 ice_aqc_opc_update_sw_rules = 0x02A1,
12721 ice_aqc_opc_remove_sw_rules = 0x02A2,
12722 ice_aqc_opc_get_sw_rules = 0x02A3,
12723 ice_aqc_opc_clear_pf_cfg = 0x02A4,
12724
12725 /* DCB commands */
12726 ice_aqc_opc_pfc_ignore = 0x0301,
12727 ice_aqc_opc_query_pfc_mode = 0x0302,
12728 ice_aqc_opc_set_pfc_mode = 0x0303,
12729 ice_aqc_opc_set_dcb_params = 0x0306,
12730
12731 /* transmit scheduler commands */
12732 ice_aqc_opc_get_dflt_topo = 0x0400,
12733 ice_aqc_opc_add_sched_elems = 0x0401,
12734 ice_aqc_opc_cfg_sched_elems = 0x0403,
12735 ice_aqc_opc_get_sched_elems = 0x0404,
12736 ice_aqc_opc_move_sched_elems = 0x0408,
12737 ice_aqc_opc_suspend_sched_elems = 0x0409,
12738 ice_aqc_opc_resume_sched_elems = 0x040A,
12739 ice_aqc_opc_query_port_ets = 0x040E,
12740 ice_aqc_opc_delete_sched_elems = 0x040F,
12741 ice_aqc_opc_add_rl_profiles = 0x0410,
12742 ice_aqc_opc_query_rl_profiles = 0x0411,
12743 ice_aqc_opc_query_sched_res = 0x0412,
12744 ice_aqc_opc_query_node_to_root = 0x0413,
12745 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
12746 ice_aqc_opc_remove_rl_profiles = 0x0415,
12747 ice_aqc_opc_set_tx_topo = 0x0417,
12748 ice_aqc_opc_get_tx_topo = 0x0418,
12749 ice_aqc_opc_cfg_node_attr = 0x0419,
12750 ice_aqc_opc_query_node_attr = 0x041A,
12751
12752 /* PHY commands */
12753 ice_aqc_opc_get_phy_caps = 0x0600,
12754 ice_aqc_opc_set_phy_cfg = 0x0601,
12755 ice_aqc_opc_set_mac_cfg = 0x0603,
12756 ice_aqc_opc_restart_an = 0x0605,
12757 ice_aqc_opc_get_link_status = 0x0607,
12758 ice_aqc_opc_set_event_mask = 0x0613,
12759 ice_aqc_opc_set_mac_lb = 0x0620,
12760 ice_aqc_opc_get_sensor_reading = 0x0632,
12761 ice_aqc_opc_dnl_get_status = 0x0680,
12762 ice_aqc_opc_dnl_run = 0x0681,
12763 ice_aqc_opc_dnl_call = 0x0682,
12764 ice_aqc_opc_dnl_read_sto = 0x0683,
12765 ice_aqc_opc_dnl_write_sto = 0x0684,
12766 ice_aqc_opc_dnl_set_breakpoints = 0x0686,
12767 ice_aqc_opc_dnl_read_log = 0x0687,
12768 ice_aqc_opc_get_link_topo = 0x06E0,
12769 ice_aqc_opc_read_i2c = 0x06E2,
12770 ice_aqc_opc_write_i2c = 0x06E3,
12771 ice_aqc_opc_read_mdio = 0x06E4,
12772 ice_aqc_opc_write_mdio = 0x06E5,
12773 ice_aqc_opc_set_gpio_by_func = 0x06E6,
12774 ice_aqc_opc_get_gpio_by_func = 0x06E7,
12775 ice_aqc_opc_set_led = 0x06E8,
12776 ice_aqc_opc_set_port_id_led = 0x06E9,
12777 ice_aqc_opc_get_port_options = 0x06EA,
12778 ice_aqc_opc_set_port_option = 0x06EB,
12779 ice_aqc_opc_set_gpio = 0x06EC,
12780 ice_aqc_opc_get_gpio = 0x06ED,
12781 ice_aqc_opc_sff_eeprom = 0x06EE,
12782 ice_aqc_opc_sw_set_gpio = 0x06EF,
12783 ice_aqc_opc_sw_get_gpio = 0x06F0,
12784 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2,
12785 ice_aqc_opc_read_topo_dev_nvm = 0x06F3,
12786
12787 /* NVM commands */
12788 ice_aqc_opc_nvm_read = 0x0701,
12789 ice_aqc_opc_nvm_erase = 0x0702,
12790 ice_aqc_opc_nvm_write = 0x0703,
12791 ice_aqc_opc_nvm_cfg_read = 0x0704,
12792 ice_aqc_opc_nvm_cfg_write = 0x0705,
12793 ice_aqc_opc_nvm_checksum = 0x0706,
12794 ice_aqc_opc_nvm_write_activate = 0x0707,
12795 ice_aqc_opc_nvm_sr_dump = 0x0707,
12796 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
12797 ice_aqc_opc_nvm_update_empr = 0x0709,
12798 ice_aqc_opc_nvm_pkg_data = 0x070A,
12799 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
12800
12801 /* PF/VF mailbox commands */
12802 ice_mbx_opc_send_msg_to_pf = 0x0801,
12803 ice_mbx_opc_send_msg_to_vf = 0x0802,
12804 /* Alternate Structure Commands */
12805 ice_aqc_opc_write_alt_direct = 0x0900,
12806 ice_aqc_opc_write_alt_indirect = 0x0901,
12807 ice_aqc_opc_read_alt_direct = 0x0902,
12808 ice_aqc_opc_read_alt_indirect = 0x0903,
12809 ice_aqc_opc_done_alt_write = 0x0904,
12810 ice_aqc_opc_clear_port_alt_write = 0x0906,
12811 /* LLDP commands */
12812 ice_aqc_opc_lldp_get_mib = 0x0A00,
12813 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
12814 ice_aqc_opc_lldp_add_tlv = 0x0A02,
12815 ice_aqc_opc_lldp_update_tlv = 0x0A03,
12816 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
12817 ice_aqc_opc_lldp_stop = 0x0A05,
12818 ice_aqc_opc_lldp_start = 0x0A06,
12819 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
12820 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
12821 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
12822 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
12823 ice_execute_pending_lldp_mib = 0x0A0B,
12824
12825 /* RSS commands */
12826 ice_aqc_opc_set_rss_key = 0x0B02,
12827 ice_aqc_opc_set_rss_lut = 0x0B03,
12828 ice_aqc_opc_get_rss_key = 0x0B04,
12829 ice_aqc_opc_get_rss_lut = 0x0B05,
12830
12831 /* Tx queue handling commands/events */
12832 ice_aqc_opc_add_txqs = 0x0C30,
12833 ice_aqc_opc_dis_txqs = 0x0C31,
12834 ice_aqc_opc_txqs_cleanup = 0x0C31,
12835 ice_aqc_opc_move_recfg_txqs = 0x0C32,
12836 ice_aqc_opc_add_rdma_qset = 0x0C33,
12837 ice_aqc_opc_move_rdma_qset = 0x0C34,
12838
12839 /* package commands */
12840 ice_aqc_opc_download_pkg = 0x0C40,
12841 ice_aqc_opc_upload_section = 0x0C41,
12842 ice_aqc_opc_update_pkg = 0x0C42,
12843 ice_aqc_opc_get_pkg_info_list = 0x0C43,
12844
12845 ice_aqc_opc_driver_shared_params = 0x0C90,
12846
12847 /* Standalone Commands/Events */
12848 ice_aqc_opc_event_lan_overflow = 0x1001,
12849
12850 /* debug commands */
12851 ice_aqc_opc_debug_dump_internals = 0xFF08,
12852
12853 /* SystemDiagnostic commands */
12854 ice_aqc_opc_set_health_status_config = 0xFF20,
12855 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
12856 ice_aqc_opc_get_health_status = 0xFF22,
12857 ice_aqc_opc_clear_health_status = 0xFF23,
12858
12859 /* FW Logging Commands */
12860 ice_aqc_opc_fw_logs_config = 0xFF30,
12861 ice_aqc_opc_fw_logs_register = 0xFF31,
12862 ice_aqc_opc_fw_logs_query = 0xFF32,
12863 ice_aqc_opc_fw_logs_event = 0xFF33,
12864 ice_aqc_opc_fw_logs_get = 0xFF34,
12865 ice_aqc_opc_fw_logs_clear = 0xFF35
12866 };
12867
12868 #endif /* _ICE_ADMINQ_CMD_H_ */
12869
12870 #ifndef _ICE_FWLOG_H_
12871 #define _ICE_FWLOG_H_
12872
12873 /* Only a single log level should be set and all log levels under the set value
12874 * are enabled, e.g. if log level is set to ICE_FW_LOG_LEVEL_VERBOSE, then all
12875 * other log levels are included (except ICE_FW_LOG_LEVEL_NONE)
12876 */
12877 enum ice_fwlog_level {
12878 ICE_FWLOG_LEVEL_NONE = 0,
12879 ICE_FWLOG_LEVEL_ERROR = 1,
12880 ICE_FWLOG_LEVEL_WARNING = 2,
12881 ICE_FWLOG_LEVEL_NORMAL = 3,
12882 ICE_FWLOG_LEVEL_VERBOSE = 4,
12883 ICE_FWLOG_LEVEL_INVALID, /* all values >= this entry are invalid */
12884 };
12885
12886 struct ice_fwlog_module_entry {
12887 /* module ID for the corresponding firmware logging event */
12888 uint16_t module_id;
12889 /* verbosity level for the module_id */
12890 uint8_t log_level;
12891 };
12892
12893 struct ice_fwlog_cfg {
12894 /* list of modules for configuring log level */
12895 struct ice_fwlog_module_entry module_entries[ICE_AQC_FW_LOG_ID_MAX];
12896 #define ICE_FWLOG_OPTION_ARQ_ENA BIT(0)
12897 #define ICE_FWLOG_OPTION_UART_ENA BIT(1)
12898 /* set before calling ice_fwlog_init() so the PF registers for firmware
12899 * logging on initialization
12900 */
12901 #define ICE_FWLOG_OPTION_REGISTER_ON_INIT BIT(2)
12902 /* set in the ice_fwlog_get() response if the PF is registered for FW
12903 * logging events over ARQ
12904 */
12905 #define ICE_FWLOG_OPTION_IS_REGISTERED BIT(3)
12906 /* options used to configure firmware logging */
12907 uint16_t options;
12908 /* minimum number of log events sent per Admin Receive Queue event */
12909 uint16_t log_resolution;
12910 };
12911
12912 #endif /* _ICE_FWLOG_H_ */
12913
12914 #ifndef _ICE_NVM_H_
12915 #define _ICE_NVM_H_
12916
12917 #define ICE_NVM_CMD_READ 0x0000000B
12918 #define ICE_NVM_CMD_WRITE 0x0000000C
12919
12920 /* NVM Access config bits */
12921 #define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
12922 #define ICE_NVM_CFG_MODULE_S 0
12923 #define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
12924 #define ICE_NVM_CFG_FLAGS_S 8
12925 #define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
12926 #define ICE_NVM_CFG_EXT_FLAGS_S 12
12927 #define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
12928 #define ICE_NVM_CFG_ADAPTER_INFO_S 16
12929
12930 /* NVM Read Get Driver Features */
12931 #define ICE_NVM_GET_FEATURES_MODULE 0xE
12932 #define ICE_NVM_GET_FEATURES_FLAGS 0xF
12933
12934 /* NVM Read/Write Mapped Space */
12935 #define ICE_NVM_REG_RW_MODULE 0x0
12936 #define ICE_NVM_REG_RW_FLAGS 0x1
12937
12938 struct ice_orom_civd_info {
12939 uint8_t signature[4]; /* Must match ASCII '$CIV' characters */
12940 uint8_t checksum; /* Simple modulo 256 sum of all structure bytes must equal 0 */
12941 uint32_t combo_ver; /* Combo Image Version number */
12942 uint8_t combo_name_len; /* Length of the unicode combo image version string, max of 32 */
12943 uint16_t combo_name[32]; /* Unicode string representing the Combo Image version */
12944 } __packed;
12945
12946 #define ICE_NVM_ACCESS_MAJOR_VER 0
12947 #define ICE_NVM_ACCESS_MINOR_VER 5
12948
12949 /* NVM Access feature flags. Other bits in the features field are reserved and
12950 * should be set to zero when reporting the ice_nvm_features structure.
12951 */
12952 #define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
12953
12954 /* NVM Access Features */
12955 struct ice_nvm_features {
12956 uint8_t major; /* Major version (informational only) */
12957 uint8_t minor; /* Minor version (informational only) */
12958 uint16_t size; /* size of ice_nvm_features structure */
12959 uint8_t features[12]; /* Array of feature bits */
12960 };
12961
12962 /* NVM Access command */
12963 struct ice_nvm_access_cmd {
12964 uint32_t command; /* NVM command: READ or WRITE */
12965 uint32_t config; /* NVM command configuration */
12966 uint32_t offset; /* offset to read/write, in bytes */
12967 uint32_t data_size; /* size of data field, in bytes */
12968 };
12969
12970 /* NVM Access data */
12971 union ice_nvm_access_data {
12972 uint32_t regval; /* Storage for register value */
12973 struct ice_nvm_features drv_features; /* NVM features */
12974 };
12975
12976 #endif /* _ICE_NVM_H_ */
12977
12978 /* Switch recipe ID enum values are specific to hardware */
12979 enum ice_sw_lkup_type {
12980 ICE_SW_LKUP_ETHERTYPE = 0,
12981 ICE_SW_LKUP_MAC = 1,
12982 ICE_SW_LKUP_MAC_VLAN = 2,
12983 ICE_SW_LKUP_PROMISC = 3,
12984 ICE_SW_LKUP_VLAN = 4,
12985 ICE_SW_LKUP_DFLT = 5,
12986 ICE_SW_LKUP_ETHERTYPE_MAC = 8,
12987 ICE_SW_LKUP_PROMISC_VLAN = 9,
12988 ICE_SW_LKUP_LAST
12989 };
12990
12991 #ifndef _ICE_LAN_TX_RX_H_
12992 #define _ICE_LAN_TX_RX_H_
12993
12994 /* Rx Descriptors */
12995 union ice_16byte_rx_desc {
12996 struct {
12997 uint64_t pkt_addr; /* Packet buffer address */
12998 uint64_t hdr_addr; /* Header buffer address */
12999 } read;
13000 struct {
13001 struct {
13002 struct {
13003 uint16_t mirroring_status;
13004 uint16_t l2tag1;
13005 } lo_dword;
13006 union {
13007 uint32_t rss; /* RSS Hash */
13008 uint32_t fd_id; /* Flow Director filter ID */
13009 } hi_dword;
13010 } qword0;
13011 struct {
13012 /* ext status/error/PTYPE/length */
13013 uint64_t status_error_len;
13014 } qword1;
13015 } wb; /* writeback */
13016 };
13017
13018 union ice_32byte_rx_desc {
13019 struct {
13020 uint64_t pkt_addr; /* Packet buffer address */
13021 uint64_t hdr_addr; /* Header buffer address */
13022 /* bit 0 of hdr_addr is DD bit */
13023 uint64_t rsvd1;
13024 uint64_t rsvd2;
13025 } read;
13026 struct {
13027 struct {
13028 struct {
13029 uint16_t mirroring_status;
13030 uint16_t l2tag1;
13031 } lo_dword;
13032 union {
13033 uint32_t rss; /* RSS Hash */
13034 uint32_t fd_id; /* Flow Director filter ID */
13035 } hi_dword;
13036 } qword0;
13037 struct {
13038 /* status/error/PTYPE/length */
13039 uint64_t status_error_len;
13040 } qword1;
13041 struct {
13042 uint16_t ext_status; /* extended status */
13043 uint16_t rsvd;
13044 uint16_t l2tag2_1;
13045 uint16_t l2tag2_2;
13046 } qword2;
13047 struct {
13048 uint32_t reserved;
13049 uint32_t fd_id;
13050 } qword3;
13051 } wb; /* writeback */
13052 };
13053
13054 struct ice_fltr_desc {
13055 uint64_t qidx_compq_space_stat;
13056 uint64_t dtype_cmd_vsi_fdid;
13057 };
13058
13059 #define ICE_FXD_FLTR_QW0_QINDEX_S 0
13060 #define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)
13061 #define ICE_FXD_FLTR_QW0_COMP_Q_S 11
13062 #define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
13063 #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL
13064 #define ICE_FXD_FLTR_QW0_COMP_Q_QINDX 0x1ULL
13065
13066 #define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12
13067 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M \
13068 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)
13069 #define ICE_FXD_FLTR_QW0_COMP_REPORT_NONE 0x0ULL
13070 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL
13071 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW 0x2ULL
13072
13073 #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14
13074 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)
13075 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR 0x0ULL
13076 #define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_EFFORT 0x1ULL
13077 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL
13078 #define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_GUAR 0x3ULL
13079
13080 #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16
13081 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \
13082 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)
13083 #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29
13084 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)
13085 #define ICE_FXD_FLTR_QW0_STAT_ENA_NONE 0x0ULL
13086 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL
13087 #define ICE_FXD_FLTR_QW0_STAT_ENA_BYTES 0x2ULL
13088 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS_BYTES 0x3ULL
13089
13090 #define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31
13091 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
13092 #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL
13093 #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL
13094
13095 #define ICE_FXD_FLTR_QW0_TO_Q_S 32
13096 #define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)
13097 #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL
13098
13099 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35
13100 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)
13101 #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL
13102
13103 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38
13104 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \
13105 (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)
13106 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL
13107
13108 #define ICE_FXD_FLTR_QW0_DROP_S 40
13109 #define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
13110 #define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL
13111 #define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL
13112
13113 #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41
13114 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)
13115 #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL
13116
13117 #define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44
13118 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)
13119 #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL
13120
13121 #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48
13122 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \
13123 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)
13124 #define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL
13125
13126 #define ICE_FXD_FLTR_QW1_DTYPE_S 0
13127 #define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)
13128 #define ICE_FXD_FLTR_QW1_PCMD_S 4
13129 #define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
13130 #define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL
13131 #define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL
13132
13133 #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5
13134 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)
13135 #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL
13136
13137 #define ICE_FXD_FLTR_QW1_PROF_S 8
13138 #define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)
13139 #define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL
13140
13141 #define ICE_FXD_FLTR_QW1_FD_VSI_S 14
13142 #define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)
13143 #define ICE_FXD_FLTR_QW1_SWAP_S 24
13144 #define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
13145 #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL
13146 #define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL
13147
13148 #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25
13149 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
13150 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL
13151 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL
13152
13153 #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28
13154 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
13155 #define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL
13156
13157 #define ICE_FXD_FLTR_QW1_FDID_S 32
13158 #define ICE_FXD_FLTR_QW1_FDID_M \
13159 (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
13160 #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL
13161
13162 enum ice_rx_desc_status_bits {
13163 /* Note: These are predefined bit offsets */
13164 ICE_RX_DESC_STATUS_DD_S = 0,
13165 ICE_RX_DESC_STATUS_EOF_S = 1,
13166 ICE_RX_DESC_STATUS_L2TAG1P_S = 2,
13167 ICE_RX_DESC_STATUS_L3L4P_S = 3,
13168 ICE_RX_DESC_STATUS_CRCP_S = 4,
13169 ICE_RX_DESC_STATUS_TSYNINDX_S = 5,
13170 ICE_RX_DESC_STATUS_TSYNVALID_S = 7,
13171 ICE_RX_DESC_STATUS_EXT_UDP_0_S = 8,
13172 ICE_RX_DESC_STATUS_UMBCAST_S = 9,
13173 ICE_RX_DESC_STATUS_FLM_S = 11,
13174 ICE_RX_DESC_STATUS_FLTSTAT_S = 12,
13175 ICE_RX_DESC_STATUS_LPBK_S = 14,
13176 ICE_RX_DESC_STATUS_IPV6EXADD_S = 15,
13177 ICE_RX_DESC_STATUS_RESERVED2_S = 16,
13178 ICE_RX_DESC_STATUS_INT_UDP_0_S = 18,
13179 ICE_RX_DESC_STATUS_LAST /* this entry must be last!!! */
13180 };
13181
13182 #define ICE_RXD_QW1_STATUS_S 0
13183 #define ICE_RXD_QW1_STATUS_M ((BIT(ICE_RX_DESC_STATUS_LAST) - 1) << \
13184 ICE_RXD_QW1_STATUS_S)
13185
13186 #define ICE_RXD_QW1_STATUS_TSYNINDX_S ICE_RX_DESC_STATUS_TSYNINDX_S
13187 #define ICE_RXD_QW1_STATUS_TSYNINDX_M (0x3UL << ICE_RXD_QW1_STATUS_TSYNINDX_S)
13188
13189 #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S
13190 #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
13191
13192 enum ice_rx_desc_fltstat_values {
13193 ICE_RX_DESC_FLTSTAT_NO_DATA = 0,
13194 ICE_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
13195 ICE_RX_DESC_FLTSTAT_RSV = 2,
13196 ICE_RX_DESC_FLTSTAT_RSS_HASH = 3,
13197 };
13198
13199 #define ICE_RXD_QW1_ERROR_S 19
13200 #define ICE_RXD_QW1_ERROR_M (0xFFUL << ICE_RXD_QW1_ERROR_S)
13201
13202 enum ice_rx_desc_error_bits {
13203 /* Note: These are predefined bit offsets */
13204 ICE_RX_DESC_ERROR_RXE_S = 0,
13205 ICE_RX_DESC_ERROR_RECIPE_S = 1,
13206 ICE_RX_DESC_ERROR_HBO_S = 2,
13207 ICE_RX_DESC_ERROR_L3L4E_S = 3, /* 3 BITS */
13208 ICE_RX_DESC_ERROR_IPE_S = 3,
13209 ICE_RX_DESC_ERROR_L4E_S = 4,
13210 ICE_RX_DESC_ERROR_EIPE_S = 5,
13211 ICE_RX_DESC_ERROR_OVERSIZE_S = 6,
13212 ICE_RX_DESC_ERROR_PPRS_S = 7
13213 };
13214
13215 enum ice_rx_desc_error_l3l4e_masks {
13216 ICE_RX_DESC_ERROR_L3L4E_NONE = 0,
13217 ICE_RX_DESC_ERROR_L3L4E_PROT = 1,
13218 };
13219
13220 #define ICE_RXD_QW1_PTYPE_S 30
13221 #define ICE_RXD_QW1_PTYPE_M (0xFFULL << ICE_RXD_QW1_PTYPE_S)
13222
13223 /* Packet type non-ip values */
13224 enum ice_rx_l2_ptype {
13225 ICE_RX_PTYPE_L2_RESERVED = 0,
13226 ICE_RX_PTYPE_L2_MAC_PAY2 = 1,
13227 ICE_RX_PTYPE_L2_FIP_PAY2 = 3,
13228 ICE_RX_PTYPE_L2_OUI_PAY2 = 4,
13229 ICE_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
13230 ICE_RX_PTYPE_L2_LLDP_PAY2 = 6,
13231 ICE_RX_PTYPE_L2_ECP_PAY2 = 7,
13232 ICE_RX_PTYPE_L2_EVB_PAY2 = 8,
13233 ICE_RX_PTYPE_L2_QCN_PAY2 = 9,
13234 ICE_RX_PTYPE_L2_EAPOL_PAY2 = 10,
13235 ICE_RX_PTYPE_L2_ARP = 11,
13236 };
13237
13238 struct ice_rx_ptype_decoded {
13239 uint32_t known:1;
13240 uint32_t outer_ip:1;
13241 uint32_t outer_ip_ver:2;
13242 uint32_t outer_frag:1;
13243 uint32_t tunnel_type:3;
13244 uint32_t tunnel_end_prot:2;
13245 uint32_t tunnel_end_frag:1;
13246 uint32_t inner_prot:4;
13247 uint32_t payload_layer:3;
13248 };
13249
13250 enum ice_rx_ptype_outer_ip {
13251 ICE_RX_PTYPE_OUTER_L2 = 0,
13252 ICE_RX_PTYPE_OUTER_IP = 1,
13253 };
13254
13255 enum ice_rx_ptype_outer_ip_ver {
13256 ICE_RX_PTYPE_OUTER_NONE = 0,
13257 ICE_RX_PTYPE_OUTER_IPV4 = 1,
13258 ICE_RX_PTYPE_OUTER_IPV6 = 2,
13259 };
13260
13261 enum ice_rx_ptype_outer_fragmented {
13262 ICE_RX_PTYPE_NOT_FRAG = 0,
13263 ICE_RX_PTYPE_FRAG = 1,
13264 };
13265
13266 enum ice_rx_ptype_tunnel_type {
13267 ICE_RX_PTYPE_TUNNEL_NONE = 0,
13268 ICE_RX_PTYPE_TUNNEL_IP_IP = 1,
13269 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
13270 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
13271 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
13272 };
13273
13274 enum ice_rx_ptype_tunnel_end_prot {
13275 ICE_RX_PTYPE_TUNNEL_END_NONE = 0,
13276 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1,
13277 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2,
13278 };
13279
13280 enum ice_rx_ptype_inner_prot {
13281 ICE_RX_PTYPE_INNER_PROT_NONE = 0,
13282 ICE_RX_PTYPE_INNER_PROT_UDP = 1,
13283 ICE_RX_PTYPE_INNER_PROT_TCP = 2,
13284 ICE_RX_PTYPE_INNER_PROT_SCTP = 3,
13285 ICE_RX_PTYPE_INNER_PROT_ICMP = 4,
13286 };
13287
13288 enum ice_rx_ptype_payload_layer {
13289 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
13290 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
13291 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
13292 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
13293 };
13294
13295 #define ICE_RXD_QW1_LEN_PBUF_S 38
13296 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)
13297
13298 #define ICE_RXD_QW1_LEN_HBUF_S 52
13299 #define ICE_RXD_QW1_LEN_HBUF_M (0x7FFULL << ICE_RXD_QW1_LEN_HBUF_S)
13300
13301 #define ICE_RXD_QW1_LEN_SPH_S 63
13302 #define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
13303
13304 enum ice_rx_desc_ext_status_bits {
13305 /* Note: These are predefined bit offsets */
13306 ICE_RX_DESC_EXT_STATUS_L2TAG2P_S = 0,
13307 ICE_RX_DESC_EXT_STATUS_L2TAG3P_S = 1,
13308 ICE_RX_DESC_EXT_STATUS_FLEXBL_S = 2,
13309 ICE_RX_DESC_EXT_STATUS_FLEXBH_S = 4,
13310 ICE_RX_DESC_EXT_STATUS_FDLONGB_S = 9,
13311 ICE_RX_DESC_EXT_STATUS_PELONGB_S = 11,
13312 };
13313
13314 enum ice_rx_desc_pe_status_bits {
13315 /* Note: These are predefined bit offsets */
13316 ICE_RX_DESC_PE_STATUS_QPID_S = 0, /* 18 BITS */
13317 ICE_RX_DESC_PE_STATUS_L4PORT_S = 0, /* 16 BITS */
13318 ICE_RX_DESC_PE_STATUS_IPINDEX_S = 16, /* 8 BITS */
13319 ICE_RX_DESC_PE_STATUS_QPIDHIT_S = 24,
13320 ICE_RX_DESC_PE_STATUS_APBVTHIT_S = 25,
13321 ICE_RX_DESC_PE_STATUS_PORTV_S = 26,
13322 ICE_RX_DESC_PE_STATUS_URG_S = 27,
13323 ICE_RX_DESC_PE_STATUS_IPFRAG_S = 28,
13324 ICE_RX_DESC_PE_STATUS_IPOPT_S = 29
13325 };
13326
13327 #define ICE_RX_PROG_STATUS_DESC_LEN_S 38
13328 #define ICE_RX_PROG_STATUS_DESC_LEN 0x2000000
13329
13330 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S 2
13331 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M \
13332 (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)
13333
13334 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S 19
13335 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M \
13336 (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)
13337
13338 enum ice_rx_prog_status_desc_status_bits {
13339 /* Note: These are predefined bit offsets */
13340 ICE_RX_PROG_STATUS_DESC_DD_S = 0,
13341 ICE_RX_PROG_STATUS_DESC_PROG_ID_S = 2 /* 3 BITS */
13342 };
13343
13344 enum ice_rx_prog_status_desc_prog_id_masks {
13345 ICE_RX_PROG_STATUS_DESC_FD_FLTR_STATUS = 1,
13346 };
13347
13348 enum ice_rx_prog_status_desc_error_bits {
13349 /* Note: These are predefined bit offsets */
13350 ICE_RX_PROG_STATUS_DESC_FD_TBL_FULL_S = 0,
13351 ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S = 1,
13352 };
13353
13354 /* Rx Flex Descriptors
13355 * These descriptors are used instead of the legacy version descriptors when
13356 * ice_rlan_ctx.adv_desc is set
13357 */
13358
13359 union ice_32b_rx_flex_desc {
13360 struct {
13361 uint64_t pkt_addr; /* Packet buffer address */
13362 uint64_t hdr_addr; /* Header buffer address */
13363 /* bit 0 of hdr_addr is DD bit */
13364 uint64_t rsvd1;
13365 uint64_t rsvd2;
13366 } read;
13367 struct {
13368 /* Qword 0 */
13369 uint8_t rxdid; /* descriptor builder profile ID */
13370 uint8_t mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
13371 uint16_t ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
13372 uint16_t pkt_len; /* [15:14] are reserved */
13373 uint16_t hdr_len_sph_flex_flags1; /* header=[10:0] */
13374 /* sph=[11:11] */
13375 /* ff1/ext=[15:12] */
13376
13377 /* Qword 1 */
13378 uint16_t status_error0;
13379 uint16_t l2tag1;
13380 uint16_t flex_meta0;
13381 uint16_t flex_meta1;
13382
13383 /* Qword 2 */
13384 uint16_t status_error1;
13385 uint8_t flex_flags2;
13386 uint8_t time_stamp_low;
13387 uint16_t l2tag2_1st;
13388 uint16_t l2tag2_2nd;
13389
13390 /* Qword 3 */
13391 uint16_t flex_meta2;
13392 uint16_t flex_meta3;
13393 union {
13394 struct {
13395 uint16_t flex_meta4;
13396 uint16_t flex_meta5;
13397 } flex;
13398 uint32_t ts_high;
13399 } flex_ts;
13400 } wb; /* writeback */
13401 };
13402
13403 /* Rx Flex Descriptor NIC Profile
13404 * RxDID Profile ID 2
13405 * Flex-field 0: RSS hash lower 16-bits
13406 * Flex-field 1: RSS hash upper 16-bits
13407 * Flex-field 2: Flow ID lower 16-bits
13408 * Flex-field 3: Flow ID higher 16-bits
13409 * Flex-field 4: reserved, VLAN ID taken from L2Tag
13410 */
13411 struct ice_32b_rx_flex_desc_nic {
13412 /* Qword 0 */
13413 uint8_t rxdid;
13414 uint8_t mir_id_umb_cast;
13415 uint16_t ptype_flexi_flags0;
13416 uint16_t pkt_len;
13417 uint16_t hdr_len_sph_flex_flags1;
13418
13419 /* Qword 1 */
13420 uint16_t status_error0;
13421 uint16_t l2tag1;
13422 uint32_t rss_hash;
13423
13424 /* Qword 2 */
13425 uint16_t status_error1;
13426 uint8_t flexi_flags2;
13427 uint8_t ts_low;
13428 uint16_t l2tag2_1st;
13429 uint16_t l2tag2_2nd;
13430
13431 /* Qword 3 */
13432 uint32_t flow_id;
13433 union {
13434 struct {
13435 uint16_t rsvd;
13436 uint16_t flow_id_ipv6;
13437 } flex;
13438 uint32_t ts_high;
13439 } flex_ts;
13440 };
13441
13442 /* Rx Flex Descriptor Switch Profile
13443 * RxDID Profile ID 3
13444 * Flex-field 0: Source VSI
13445 */
13446 struct ice_32b_rx_flex_desc_sw {
13447 /* Qword 0 */
13448 uint8_t rxdid;
13449 uint8_t mir_id_umb_cast;
13450 uint16_t ptype_flexi_flags0;
13451 uint16_t pkt_len;
13452 uint16_t hdr_len_sph_flex_flags1;
13453
13454 /* Qword 1 */
13455 uint16_t status_error0;
13456 uint16_t l2tag1;
13457 uint16_t src_vsi; /* [10:15] are reserved */
13458 uint16_t flex_md1_rsvd;
13459
13460 /* Qword 2 */
13461 uint16_t status_error1;
13462 uint8_t flex_flags2;
13463 uint8_t ts_low;
13464 uint16_t l2tag2_1st;
13465 uint16_t l2tag2_2nd;
13466
13467 /* Qword 3 */
13468 uint32_t rsvd; /* flex words 2-3 are reserved */
13469 uint32_t ts_high;
13470 };
13471
13472 /* Rx Flex Descriptor NIC VEB Profile
13473 * RxDID Profile ID 4
13474 * Flex-field 0: Destination VSI
13475 */
13476 struct ice_32b_rx_flex_desc_nic_veb_dbg {
13477 /* Qword 0 */
13478 uint8_t rxdid;
13479 uint8_t mir_id_umb_cast;
13480 uint16_t ptype_flexi_flags0;
13481 uint16_t pkt_len;
13482 uint16_t hdr_len_sph_flex_flags1;
13483
13484 /* Qword 1 */
13485 uint16_t status_error0;
13486 uint16_t l2tag1;
13487 uint16_t dst_vsi; /* [0:12]: destination VSI */
13488 /* 13: VSI valid bit */
13489 /* [14:15] are reserved */
13490 uint16_t flex_field_1;
13491
13492 /* Qword 2 */
13493 uint16_t status_error1;
13494 uint8_t flex_flags2;
13495 uint8_t ts_low;
13496 uint16_t l2tag2_1st;
13497 uint16_t l2tag2_2nd;
13498
13499 /* Qword 3 */
13500 uint32_t rsvd; /* flex words 2-3 are reserved */
13501 uint32_t ts_high;
13502 };
13503
13504 /* Rx Flex Descriptor NIC ACL Profile
13505 * RxDID Profile ID 5
13506 * Flex-field 0: ACL Counter 0
13507 * Flex-field 1: ACL Counter 1
13508 * Flex-field 2: ACL Counter 2
13509 */
13510 struct ice_32b_rx_flex_desc_nic_acl_dbg {
13511 /* Qword 0 */
13512 uint8_t rxdid;
13513 uint8_t mir_id_umb_cast;
13514 uint16_t ptype_flexi_flags0;
13515 uint16_t pkt_len;
13516 uint16_t hdr_len_sph_flex_flags1;
13517
13518 /* Qword 1 */
13519 uint16_t status_error0;
13520 uint16_t l2tag1;
13521 uint16_t acl_ctr0;
13522 uint16_t acl_ctr1;
13523
13524 /* Qword 2 */
13525 uint16_t status_error1;
13526 uint8_t flex_flags2;
13527 uint8_t ts_low;
13528 uint16_t l2tag2_1st;
13529 uint16_t l2tag2_2nd;
13530
13531 /* Qword 3 */
13532 uint16_t acl_ctr2;
13533 uint16_t rsvd; /* flex words 2-3 are reserved */
13534 uint32_t ts_high;
13535 };
13536
13537 /* Rx Flex Descriptor NIC Profile
13538 * RxDID Profile ID 6
13539 * Flex-field 0: RSS hash lower 16-bits
13540 * Flex-field 1: RSS hash upper 16-bits
13541 * Flex-field 2: Flow ID lower 16-bits
13542 * Flex-field 3: Source VSI
13543 * Flex-field 4: reserved, VLAN ID taken from L2Tag
13544 */
13545 struct ice_32b_rx_flex_desc_nic_2 {
13546 /* Qword 0 */
13547 uint8_t rxdid;
13548 uint8_t mir_id_umb_cast;
13549 uint16_t ptype_flexi_flags0;
13550 uint16_t pkt_len;
13551 uint16_t hdr_len_sph_flex_flags1;
13552
13553 /* Qword 1 */
13554 uint16_t status_error0;
13555 uint16_t l2tag1;
13556 uint32_t rss_hash;
13557
13558 /* Qword 2 */
13559 uint16_t status_error1;
13560 uint8_t flexi_flags2;
13561 uint8_t ts_low;
13562 uint16_t l2tag2_1st;
13563 uint16_t l2tag2_2nd;
13564
13565 /* Qword 3 */
13566 uint16_t flow_id;
13567 uint16_t src_vsi;
13568 union {
13569 struct {
13570 uint16_t rsvd;
13571 uint16_t flow_id_ipv6;
13572 } flex;
13573 uint32_t ts_high;
13574 } flex_ts;
13575 };
13576
13577 /* Receive Flex Descriptor profile IDs: There are a total
13578 * of 64 profiles where profile IDs 0/1 are for legacy; and
13579 * profiles 2-63 are flex profiles that can be programmed
13580 * with a specific metadata (profile 7 reserved for HW)
13581 */
13582 enum ice_rxdid {
13583 ICE_RXDID_LEGACY_0 = 0,
13584 ICE_RXDID_LEGACY_1 = 1,
13585 ICE_RXDID_FLEX_NIC = 2,
13586 ICE_RXDID_FLEX_NIC_2 = 6,
13587 ICE_RXDID_HW = 7,
13588 ICE_RXDID_LAST = 63,
13589 };
13590
13591 /* Recceive Flex descriptor Dword Index */
13592 enum ice_flex_word {
13593 ICE_RX_FLEX_DWORD_0 = 0,
13594 ICE_RX_FLEX_DWORD_1,
13595 ICE_RX_FLEX_DWORD_2,
13596 ICE_RX_FLEX_DWORD_3,
13597 ICE_RX_FLEX_DWORD_4,
13598 ICE_RX_FLEX_DWORD_5
13599 };
13600
13601 /* Receive Flex Descriptor Rx opcode values */
13602 enum ice_flex_opcode {
13603 ICE_RX_OPC_DEBUG = 0,
13604 ICE_RX_OPC_MDID,
13605 ICE_RX_OPC_EXTRACT,
13606 ICE_RX_OPC_PROTID
13607 };
13608
13609 /* Receive Descriptor MDID values that access packet flags */
13610 enum ice_flex_mdid_pkt_flags {
13611 ICE_RX_MDID_PKT_FLAGS_15_0 = 20,
13612 ICE_RX_MDID_PKT_FLAGS_31_16,
13613 ICE_RX_MDID_PKT_FLAGS_47_32,
13614 ICE_RX_MDID_PKT_FLAGS_63_48,
13615 };
13616
13617 /* Generic descriptor MDID values */
13618 enum ice_flex_mdid {
13619 ICE_MDID_GENERIC_WORD_0,
13620 ICE_MDID_GENERIC_WORD_1,
13621 ICE_MDID_GENERIC_WORD_2,
13622 ICE_MDID_GENERIC_WORD_3,
13623 ICE_MDID_GENERIC_WORD_4,
13624 ICE_MDID_FLOW_ID_LOWER,
13625 ICE_MDID_FLOW_ID_HIGH,
13626 ICE_MDID_RX_DESCR_PROF_IDX,
13627 ICE_MDID_RX_PKT_DROP,
13628 ICE_MDID_RX_DST_Q = 12,
13629 ICE_MDID_RX_DST_VSI,
13630 ICE_MDID_SRC_VSI = 19,
13631 ICE_MDID_ACL_NOP = 55,
13632 /* Entry 56 */
13633 ICE_MDID_RX_HASH_LOW,
13634 ICE_MDID_ACL_CNTR_PKT = ICE_MDID_RX_HASH_LOW,
13635 /* Entry 57 */
13636 ICE_MDID_RX_HASH_HIGH,
13637 ICE_MDID_ACL_CNTR_BYTES = ICE_MDID_RX_HASH_HIGH,
13638 ICE_MDID_ACL_CNTR_PKT_BYTES
13639 };
13640
13641 /* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */
13642 #define ICE_RX_FLEX_DESC_MIRROR_M (0x3F) /* 6-bits */
13643
13644 /* Rx/Tx Flag64 packet flag bits */
13645 enum ice_flg64_bits {
13646 ICE_FLG_PKT_DSI = 0,
13647 /* If there is a 1 in this bit position then that means Rx packet */
13648 ICE_FLG_PKT_DIR = 4,
13649 ICE_FLG_EVLAN_x8100 = 14,
13650 ICE_FLG_EVLAN_x9100,
13651 ICE_FLG_VLAN_x8100,
13652 ICE_FLG_TNL_MAC = 22,
13653 ICE_FLG_TNL_VLAN,
13654 ICE_FLG_PKT_FRG,
13655 ICE_FLG_FIN = 32,
13656 ICE_FLG_SYN,
13657 ICE_FLG_RST,
13658 ICE_FLG_TNL0 = 38,
13659 ICE_FLG_TNL1,
13660 ICE_FLG_TNL2,
13661 ICE_FLG_UDP_GRE,
13662 ICE_FLG_RSVD = 63
13663 };
13664
13665 enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */
13666 ICE_RX_FLEX_DESC_UMB_CAST_S = 6,
13667 ICE_RX_FLEX_DESC_UMB_CAST_LAST /* this entry must be last!!! */
13668 };
13669
13670 enum ice_umbcast_dest_addr_types {
13671 ICE_DEST_UNICAST = 0,
13672 ICE_DEST_MULTICAST,
13673 ICE_DEST_BROADCAST,
13674 ICE_DEST_MIRRORED,
13675 };
13676
13677 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
13678 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
13679
13680 enum ice_rx_flex_desc_flexi_flags0_bits { /* field is 6 bits long */
13681 ICE_RX_FLEX_DESC_FLEXI_FLAGS0_S = 10,
13682 ICE_RX_FLEX_DESC_FLEXI_FLAGS0_LAST /* this entry must be last!!! */
13683 };
13684
13685 /* for ice_32byte_rx_flex_desc.pkt_length member */
13686 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
13687
13688 /* for ice_32byte_rx_flex_desc.header_length_sph_flexi_flags1 member */
13689 #define ICE_RX_FLEX_DESC_HEADER_LEN_M (0x7FF) /* 11-bits */
13690
13691 enum ice_rx_flex_desc_sph_bits { /* field is 1 bit long */
13692 ICE_RX_FLEX_DESC_SPH_S = 11,
13693 ICE_RX_FLEX_DESC_SPH_LAST /* this entry must be last!!! */
13694 };
13695
13696 enum ice_rx_flex_desc_flexi_flags1_bits { /* field is 4 bits long */
13697 ICE_RX_FLEX_DESC_FLEXI_FLAGS1_S = 12,
13698 ICE_RX_FLEX_DESC_FLEXI_FLAGS1_LAST /* this entry must be last!!! */
13699 };
13700
13701 enum ice_rx_flex_desc_ext_status_bits { /* field is 4 bits long */
13702 ICE_RX_FLEX_DESC_EXT_STATUS_EXT_UDP_S = 12,
13703 ICE_RX_FLEX_DESC_EXT_STATUS_INT_UDP_S = 13,
13704 ICE_RX_FLEX_DESC_EXT_STATUS_RECIPE_S = 14,
13705 ICE_RX_FLEX_DESC_EXT_STATUS_OVERSIZE_S = 15,
13706 ICE_RX_FLEX_DESC_EXT_STATUS_LAST /* entry must be last!!! */
13707 };
13708
13709 enum ice_rx_flex_desc_status_error_0_bits {
13710 /* Note: These are predefined bit offsets */
13711 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
13712 ICE_RX_FLEX_DESC_STATUS0_EOF_S,
13713 ICE_RX_FLEX_DESC_STATUS0_HBO_S,
13714 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
13715 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
13716 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
13717 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
13718 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
13719 ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
13720 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
13721 ICE_RX_FLEX_DESC_STATUS0_RXE_S,
13722 ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
13723 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
13724 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
13725 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
13726 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
13727 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
13728 };
13729
13730 enum ice_rx_flex_desc_status_error_1_bits {
13731 /* Note: These are predefined bit offsets */
13732 ICE_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */
13733 ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,
13734 ICE_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,
13735 /* [10:6] reserved */
13736 ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
13737 ICE_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
13738 ICE_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
13739 ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
13740 ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
13741 ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
13742 };
13743
13744 enum ice_rx_flex_desc_exstat_bits {
13745 /* Note: These are predefined bit offsets */
13746 ICE_RX_FLEX_DESC_EXSTAT_EXTUDP_S = 0,
13747 ICE_RX_FLEX_DESC_EXSTAT_INTUDP_S = 1,
13748 ICE_RX_FLEX_DESC_EXSTAT_RECIPE_S = 2,
13749 ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
13750 };
13751
13752 /*
13753 * For ice_32b_rx_flex_desc.ts_low:
13754 * [0]: Timestamp-low validity bit
13755 * [1:7]: Timestamp-low value
13756 */
13757 #define ICE_RX_FLEX_DESC_TS_L_VALID_S 0x01
13758 #define ICE_RX_FLEX_DESC_TS_L_VALID_M ICE_RX_FLEX_DESC_TS_L_VALID_S
13759 #define ICE_RX_FLEX_DESC_TS_L_M 0xFE
13760
13761 #define ICE_RXQ_CTX_SIZE_DWORDS 8
13762 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(uint32_t))
13763 #define ICE_TXQ_CTX_SIZE_DWORDS 10
13764 #define ICE_TXQ_CTX_SZ (ICE_TXQ_CTX_SIZE_DWORDS * sizeof(uint32_t))
13765 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
13766 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
13767 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
13768
13769 /* RLAN Rx queue context data
13770 *
13771 * The sizes of the variables may be larger than needed due to crossing byte
13772 * boundaries. If we do not have the width of the variable set to the correct
13773 * size then we could end up shifting bits off the top of the variable when the
13774 * variable is at the top of a byte and crosses over into the next byte.
13775 */
13776 struct ice_rlan_ctx {
13777 uint16_t head;
13778 uint16_t cpuid; /* bigger than needed, see above for reason */
13779 #define ICE_RLAN_BASE_S 7
13780 uint64_t base;
13781 uint16_t qlen;
13782 #define ICE_RLAN_CTX_DBUF_S 7
13783 uint16_t dbuf; /* bigger than needed, see above for reason */
13784 #define ICE_RLAN_CTX_HBUF_S 6
13785 uint16_t hbuf; /* bigger than needed, see above for reason */
13786 uint8_t dtype;
13787 uint8_t dsize;
13788 uint8_t crcstrip;
13789 uint8_t l2tsel;
13790 uint8_t hsplit_0;
13791 uint8_t hsplit_1;
13792 uint8_t showiv;
13793 uint32_t rxmax; /* bigger than needed, see above for reason */
13794 uint8_t tphrdesc_ena;
13795 uint8_t tphwdesc_ena;
13796 uint8_t tphdata_ena;
13797 uint8_t tphhead_ena;
13798 uint16_t lrxqthresh; /* bigger than needed, see above for reason */
13799 uint8_t prefena; /* NOTE: normally must be set to 1 at init */
13800 };
13801
13802 struct ice_ctx_ele {
13803 uint16_t offset;
13804 uint16_t size_of;
13805 uint16_t width;
13806 uint16_t lsb;
13807 };
13808
13809 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \
13810 .offset = offsetof(struct _struct, _ele), \
13811 .size_of = sizeof(((struct _struct *)0)->_ele), \
13812 .width = _width, \
13813 .lsb = _lsb, \
13814 }
13815
13816 /* for hsplit_0 field of Rx RLAN context */
13817 enum ice_rlan_ctx_rx_hsplit_0 {
13818 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0,
13819 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1,
13820 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2,
13821 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
13822 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8,
13823 };
13824
13825 /* for hsplit_1 field of Rx RLAN context */
13826 enum ice_rlan_ctx_rx_hsplit_1 {
13827 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0,
13828 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1,
13829 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2,
13830 };
13831
13832 /* Tx Descriptor */
13833 struct ice_tx_desc {
13834 uint64_t buf_addr; /* Address of descriptor's data buf */
13835 uint64_t cmd_type_offset_bsz;
13836 };
13837
13838 #define ICE_TXD_QW1_DTYPE_S 0
13839 #define ICE_TXD_QW1_DTYPE_M (0xFUL << ICE_TXD_QW1_DTYPE_S)
13840
13841 enum ice_tx_desc_dtype_value {
13842 ICE_TX_DESC_DTYPE_DATA = 0x0,
13843 ICE_TX_DESC_DTYPE_CTX = 0x1,
13844 ICE_TX_DESC_DTYPE_IPSEC = 0x3,
13845 ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8,
13846 ICE_TX_DESC_DTYPE_HLP_META = 0x9,
13847 /* DESC_DONE - HW has completed write-back of descriptor */
13848 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
13849 };
13850
13851 #define ICE_TXD_QW1_CMD_S 4
13852 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S)
13853
13854 enum ice_tx_desc_cmd_bits {
13855 ICE_TX_DESC_CMD_EOP = 0x0001,
13856 ICE_TX_DESC_CMD_RS = 0x0002,
13857 ICE_TX_DESC_CMD_RSVD = 0x0004,
13858 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008,
13859 ICE_TX_DESC_CMD_DUMMY = 0x0010,
13860 ICE_TX_DESC_CMD_IIPT_NONIP = 0x0000,
13861 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
13862 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
13863 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
13864 ICE_TX_DESC_CMD_RSVD2 = 0x0080,
13865 ICE_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000,
13866 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
13867 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
13868 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
13869 ICE_TX_DESC_CMD_RE = 0x0400,
13870 ICE_TX_DESC_CMD_RSVD3 = 0x0800,
13871 };
13872
13873 #define ICE_TXD_QW1_OFFSET_S 16
13874 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
13875
13876 enum ice_tx_desc_len_fields {
13877 /* Note: These are predefined bit offsets */
13878 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
13879 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
13880 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
13881 };
13882
13883 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
13884 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
13885 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
13886
13887 /* Tx descriptor field limits in bytes */
13888 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
13889 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
13890 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
13891 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
13892 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
13893 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
13894
13895 #define ICE_TXD_QW1_TX_BUF_SZ_S 34
13896 #define ICE_TXD_QW1_TX_BUF_SZ_M (0x3FFFULL << ICE_TXD_QW1_TX_BUF_SZ_S)
13897
13898 #define ICE_TXD_QW1_L2TAG1_S 48
13899 #define ICE_TXD_QW1_L2TAG1_M (0xFFFFULL << ICE_TXD_QW1_L2TAG1_S)
13900
13901 /* Context descriptors */
13902 struct ice_tx_ctx_desc {
13903 uint32_t tunneling_params;
13904 uint16_t l2tag2;
13905 uint16_t rsvd;
13906 uint64_t qw1;
13907 };
13908
13909 #define ICE_TX_GCS_DESC_START 0 /* 7 BITS */
13910 #define ICE_TX_GCS_DESC_OFFSET 7 /* 4 BITS */
13911 #define ICE_TX_GCS_DESC_TYPE 11 /* 2 BITS */
13912 #define ICE_TX_GCS_DESC_ENA 13 /* 1 BIT */
13913
13914 #define ICE_TXD_CTX_QW1_DTYPE_S 0
13915 #define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)
13916
13917 #define ICE_TXD_CTX_QW1_CMD_S 4
13918 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
13919
13920 #define ICE_TXD_CTX_QW1_IPSEC_S 11
13921 #define ICE_TXD_CTX_QW1_IPSEC_M (0x7FUL << ICE_TXD_CTX_QW1_IPSEC_S)
13922
13923 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30
13924 #define ICE_TXD_CTX_QW1_TSO_LEN_M \
13925 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
13926
13927 #define ICE_TXD_CTX_QW1_TSYN_S ICE_TXD_CTX_QW1_TSO_LEN_S
13928 #define ICE_TXD_CTX_QW1_TSYN_M ICE_TXD_CTX_QW1_TSO_LEN_M
13929
13930 #define ICE_TXD_CTX_QW1_MSS_S 50
13931 #define ICE_TXD_CTX_QW1_MSS_M (0x3FFFULL << ICE_TXD_CTX_QW1_MSS_S)
13932 #define ICE_TXD_CTX_MIN_MSS 64
13933 #define ICE_TXD_CTX_MAX_MSS 9668
13934
13935 #define ICE_TXD_CTX_QW1_VSI_S 50
13936 #define ICE_TXD_CTX_QW1_VSI_M (0x3FFULL << ICE_TXD_CTX_QW1_VSI_S)
13937
13938 enum ice_tx_ctx_desc_cmd_bits {
13939 ICE_TX_CTX_DESC_TSO = 0x01,
13940 ICE_TX_CTX_DESC_TSYN = 0x02,
13941 ICE_TX_CTX_DESC_IL2TAG2 = 0x04,
13942 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
13943 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
13944 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
13945 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
13946 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30,
13947 ICE_TX_CTX_DESC_RESERVED = 0x40
13948 };
13949
13950 enum ice_tx_ctx_desc_eipt_offload {
13951 ICE_TX_CTX_EIPT_NONE = 0x0,
13952 ICE_TX_CTX_EIPT_IPV6 = 0x1,
13953 ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2,
13954 ICE_TX_CTX_EIPT_IPV4 = 0x3
13955 };
13956
13957 #define ICE_TXD_CTX_QW0_EIPT_S 0
13958 #define ICE_TXD_CTX_QW0_EIPT_M (0x3ULL << ICE_TXD_CTX_QW0_EIPT_S)
13959
13960 #define ICE_TXD_CTX_QW0_EIPLEN_S 2
13961 #define ICE_TXD_CTX_QW0_EIPLEN_M (0x7FUL << ICE_TXD_CTX_QW0_EIPLEN_S)
13962
13963 #define ICE_TXD_CTX_QW0_L4TUNT_S 9
13964 #define ICE_TXD_CTX_QW0_L4TUNT_M (0x3ULL << ICE_TXD_CTX_QW0_L4TUNT_S)
13965
13966 #define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
13967 #define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)
13968
13969 #define ICE_TXD_CTX_QW0_EIP_NOINC_S 11
13970 #define ICE_TXD_CTX_QW0_EIP_NOINC_M BIT_ULL(ICE_TXD_CTX_QW0_EIP_NOINC_S)
13971
13972 #define ICE_TXD_CTX_EIP_NOINC_IPID_CONST ICE_TXD_CTX_QW0_EIP_NOINC_M
13973
13974 #define ICE_TXD_CTX_QW0_NATLEN_S 12
13975 #define ICE_TXD_CTX_QW0_NATLEN_M (0X7FULL << ICE_TXD_CTX_QW0_NATLEN_S)
13976
13977 #define ICE_TXD_CTX_QW0_DECTTL_S 19
13978 #define ICE_TXD_CTX_QW0_DECTTL_M (0xFULL << ICE_TXD_CTX_QW0_DECTTL_S)
13979
13980 #define ICE_TXD_CTX_QW0_L4T_CS_S 23
13981 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
13982
13983 #define ICE_LAN_TXQ_MAX_QGRPS 127
13984 #define ICE_LAN_TXQ_MAX_QDIS 1023
13985
13986 /* Tx queue context data
13987 *
13988 * The sizes of the variables may be larger than needed due to crossing byte
13989 * boundaries. If we do not have the width of the variable set to the correct
13990 * size then we could end up shifting bits off the top of the variable when the
13991 * variable is at the top of a byte and crosses over into the next byte.
13992 */
13993 struct ice_tlan_ctx {
13994 #define ICE_TLAN_CTX_BASE_S 7
13995 uint64_t base; /* base is defined in 128-byte units */
13996 uint8_t port_num;
13997 uint16_t cgd_num; /* bigger than needed, see above for reason */
13998 uint8_t pf_num;
13999 uint16_t vmvf_num;
14000 uint8_t vmvf_type;
14001 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0
14002 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1
14003 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2
14004 uint16_t src_vsi;
14005 uint8_t tsyn_ena;
14006 uint8_t internal_usage_flag;
14007 uint8_t alt_vlan;
14008 uint16_t cpuid; /* bigger than needed, see above for reason */
14009 uint8_t wb_mode;
14010 uint8_t tphrd_desc;
14011 uint8_t tphrd;
14012 uint8_t tphwr_desc;
14013 uint16_t cmpq_id;
14014 uint16_t qnum_in_func;
14015 uint8_t itr_notification_mode;
14016 uint8_t adjust_prof_id;
14017 uint32_t qlen; /* bigger than needed, see above for reason */
14018 uint8_t quanta_prof_idx;
14019 uint8_t tso_ena;
14020 uint16_t tso_qnum;
14021 uint8_t legacy_int;
14022 uint8_t drop_ena;
14023 uint8_t cache_prof_idx;
14024 uint8_t pkt_shaper_prof_idx;
14025 uint8_t int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
14026 uint16_t tail;
14027 };
14028
14029 /* LAN Tx Completion Queue data */
14030 struct ice_tx_cmpltnq {
14031 uint16_t txq_id;
14032 uint8_t generation;
14033 uint16_t tx_head;
14034 uint8_t cmpl_type;
14035 } __packed;
14036
14037 /* FIXME: move to a .c file that references this variable */
14038 /* LAN Tx Completion Queue data info */
14039 static const struct ice_ctx_ele ice_tx_cmpltnq_info[] = {
14040 /* Field Width LSB */
14041 ICE_CTX_STORE(ice_tx_cmpltnq, txq_id, 14, 0),
14042 ICE_CTX_STORE(ice_tx_cmpltnq, generation, 1, 15),
14043 ICE_CTX_STORE(ice_tx_cmpltnq, tx_head, 13, 16),
14044 ICE_CTX_STORE(ice_tx_cmpltnq, cmpl_type, 3, 29),
14045 { 0 }
14046 };
14047
14048 /* LAN Tx Completion Queue Context */
14049 struct ice_tx_cmpltnq_ctx {
14050 uint64_t base;
14051 #define ICE_TX_CMPLTNQ_CTX_BASE_S 7
14052 uint32_t q_len;
14053 #define ICE_TX_CMPLTNQ_CTX_Q_LEN_S 4
14054 uint8_t generation;
14055 uint32_t wrt_ptr;
14056 uint8_t pf_num;
14057 uint16_t vmvf_num;
14058 uint8_t vmvf_type;
14059 #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VF 0
14060 #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VMQ 1
14061 #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_PF 2
14062 uint8_t tph_desc_wr;
14063 uint8_t cpuid;
14064 uint32_t cmpltn_cache[16];
14065 } __packed;
14066
14067 /* LAN Tx Doorbell Descriptor Format */
14068 struct ice_tx_drbell_fmt {
14069 uint16_t txq_id;
14070 uint8_t dd;
14071 uint8_t rs;
14072 uint32_t db;
14073 };
14074
14075 /* FIXME: move to a .c file that references this variable */
14076 /* LAN Tx Doorbell Descriptor format info */
14077 static const struct ice_ctx_ele ice_tx_drbell_fmt_info[] = {
14078 /* Field Width LSB */
14079 ICE_CTX_STORE(ice_tx_drbell_fmt, txq_id, 14, 0),
14080 ICE_CTX_STORE(ice_tx_drbell_fmt, dd, 1, 14),
14081 ICE_CTX_STORE(ice_tx_drbell_fmt, rs, 1, 15),
14082 ICE_CTX_STORE(ice_tx_drbell_fmt, db, 32, 32),
14083 { 0 }
14084 };
14085
14086 /* LAN Tx Doorbell Queue Context */
14087 struct ice_tx_drbell_q_ctx {
14088 uint64_t base;
14089 #define ICE_TX_DRBELL_Q_CTX_BASE_S 7
14090 uint16_t ring_len;
14091 #define ICE_TX_DRBELL_Q_CTX_RING_LEN_S 4
14092 uint8_t pf_num;
14093 uint16_t vf_num;
14094 uint8_t vmvf_type;
14095 #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VF 0
14096 #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VMQ 1
14097 #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_PF 2
14098 uint8_t cpuid;
14099 uint8_t tph_desc_rd;
14100 uint8_t tph_desc_wr;
14101 uint8_t db_q_en;
14102 uint16_t rd_head;
14103 uint16_t rd_tail;
14104 } __packed;
14105
14106 /* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the
14107 * hardware to a bit-field that can be used by SW to more easily determine the
14108 * packet type.
14109 *
14110 * Macros are used to shorten the table lines and make this table human
14111 * readable.
14112 *
14113 * We store the PTYPE in the top byte of the bit field - this is just so that
14114 * we can check that the table doesn't have a row missing, as the index into
14115 * the table should be the PTYPE.
14116 *
14117 * Typical work flow:
14118 *
14119 * IF NOT ice_ptype_lkup[ptype].known
14120 * THEN
14121 * Packet is unknown
14122 * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP
14123 * Use the rest of the fields to look at the tunnels, inner protocols, etc
14124 * ELSE
14125 * Use the enum ice_rx_l2_ptype to decode the packet type
14126 * ENDIF
14127 */
14128
14129 /* macro to make the table lines short */
14130 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
14131 { 1, \
14132 ICE_RX_PTYPE_OUTER_##OUTER_IP, \
14133 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
14134 ICE_RX_PTYPE_##OUTER_FRAG, \
14135 ICE_RX_PTYPE_TUNNEL_##T, \
14136 ICE_RX_PTYPE_TUNNEL_END_##TE, \
14137 ICE_RX_PTYPE_##TEF, \
14138 ICE_RX_PTYPE_INNER_PROT_##I, \
14139 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
14140
14141 #define ICE_PTT_UNUSED_ENTRY(PTYPE) { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
14142
14143 /* shorter macros makes the table fit but are terse */
14144 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
14145 #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG
14146
14147 /* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */
14148 static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = {
14149 /* L2 Packet types */
14150 ICE_PTT_UNUSED_ENTRY(0),
14151 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
14152 ICE_PTT_UNUSED_ENTRY(2),
14153 ICE_PTT_UNUSED_ENTRY(3),
14154 ICE_PTT_UNUSED_ENTRY(4),
14155 ICE_PTT_UNUSED_ENTRY(5),
14156 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
14157 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
14158 ICE_PTT_UNUSED_ENTRY(8),
14159 ICE_PTT_UNUSED_ENTRY(9),
14160 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
14161 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
14162 ICE_PTT_UNUSED_ENTRY(12),
14163 ICE_PTT_UNUSED_ENTRY(13),
14164 ICE_PTT_UNUSED_ENTRY(14),
14165 ICE_PTT_UNUSED_ENTRY(15),
14166 ICE_PTT_UNUSED_ENTRY(16),
14167 ICE_PTT_UNUSED_ENTRY(17),
14168 ICE_PTT_UNUSED_ENTRY(18),
14169 ICE_PTT_UNUSED_ENTRY(19),
14170 ICE_PTT_UNUSED_ENTRY(20),
14171 ICE_PTT_UNUSED_ENTRY(21),
14172
14173 /* Non Tunneled IPv4 */
14174 ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
14175 ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
14176 ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
14177 ICE_PTT_UNUSED_ENTRY(25),
14178 ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
14179 ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
14180 ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
14181
14182 /* IPv4 --> IPv4 */
14183 ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
14184 ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
14185 ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
14186 ICE_PTT_UNUSED_ENTRY(32),
14187 ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
14188 ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
14189 ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
14190
14191 /* IPv4 --> IPv6 */
14192 ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
14193 ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
14194 ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
14195 ICE_PTT_UNUSED_ENTRY(39),
14196 ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
14197 ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
14198 ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
14199
14200 /* IPv4 --> GRE/NAT */
14201 ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
14202
14203 /* IPv4 --> GRE/NAT --> IPv4 */
14204 ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
14205 ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
14206 ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
14207 ICE_PTT_UNUSED_ENTRY(47),
14208 ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
14209 ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
14210 ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
14211
14212 /* IPv4 --> GRE/NAT --> IPv6 */
14213 ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
14214 ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
14215 ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
14216 ICE_PTT_UNUSED_ENTRY(54),
14217 ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
14218 ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
14219 ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
14220
14221 /* IPv4 --> GRE/NAT --> MAC */
14222 ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
14223
14224 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
14225 ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
14226 ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
14227 ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
14228 ICE_PTT_UNUSED_ENTRY(62),
14229 ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
14230 ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
14231 ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
14232
14233 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
14234 ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
14235 ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
14236 ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
14237 ICE_PTT_UNUSED_ENTRY(69),
14238 ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
14239 ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
14240 ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
14241
14242 /* IPv4 --> GRE/NAT --> MAC/VLAN */
14243 ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
14244
14245 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
14246 ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
14247 ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
14248 ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
14249 ICE_PTT_UNUSED_ENTRY(77),
14250 ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
14251 ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
14252 ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
14253
14254 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
14255 ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
14256 ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
14257 ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
14258 ICE_PTT_UNUSED_ENTRY(84),
14259 ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
14260 ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
14261 ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
14262
14263 /* Non Tunneled IPv6 */
14264 ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
14265 ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
14266 ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
14267 ICE_PTT_UNUSED_ENTRY(91),
14268 ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
14269 ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
14270 ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
14271
14272 /* IPv6 --> IPv4 */
14273 ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
14274 ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
14275 ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
14276 ICE_PTT_UNUSED_ENTRY(98),
14277 ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
14278 ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
14279 ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
14280
14281 /* IPv6 --> IPv6 */
14282 ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
14283 ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
14284 ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
14285 ICE_PTT_UNUSED_ENTRY(105),
14286 ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
14287 ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
14288 ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
14289
14290 /* IPv6 --> GRE/NAT */
14291 ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
14292
14293 /* IPv6 --> GRE/NAT -> IPv4 */
14294 ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
14295 ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
14296 ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
14297 ICE_PTT_UNUSED_ENTRY(113),
14298 ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
14299 ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
14300 ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
14301
14302 /* IPv6 --> GRE/NAT -> IPv6 */
14303 ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
14304 ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
14305 ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
14306 ICE_PTT_UNUSED_ENTRY(120),
14307 ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
14308 ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
14309 ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
14310
14311 /* IPv6 --> GRE/NAT -> MAC */
14312 ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
14313
14314 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
14315 ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
14316 ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
14317 ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
14318 ICE_PTT_UNUSED_ENTRY(128),
14319 ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
14320 ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
14321 ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
14322
14323 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
14324 ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
14325 ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
14326 ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
14327 ICE_PTT_UNUSED_ENTRY(135),
14328 ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
14329 ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
14330 ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
14331
14332 /* IPv6 --> GRE/NAT -> MAC/VLAN */
14333 ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
14334
14335 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
14336 ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
14337 ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
14338 ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
14339 ICE_PTT_UNUSED_ENTRY(143),
14340 ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
14341 ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
14342 ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
14343
14344 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
14345 ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
14346 ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
14347 ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
14348 ICE_PTT_UNUSED_ENTRY(150),
14349 ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
14350 ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
14351 ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
14352
14353 /* unused entries */
14354 ICE_PTT_UNUSED_ENTRY(154),
14355 ICE_PTT_UNUSED_ENTRY(155),
14356 ICE_PTT_UNUSED_ENTRY(156),
14357 ICE_PTT_UNUSED_ENTRY(157),
14358 ICE_PTT_UNUSED_ENTRY(158),
14359 ICE_PTT_UNUSED_ENTRY(159),
14360
14361 ICE_PTT_UNUSED_ENTRY(160),
14362 ICE_PTT_UNUSED_ENTRY(161),
14363 ICE_PTT_UNUSED_ENTRY(162),
14364 ICE_PTT_UNUSED_ENTRY(163),
14365 ICE_PTT_UNUSED_ENTRY(164),
14366 ICE_PTT_UNUSED_ENTRY(165),
14367 ICE_PTT_UNUSED_ENTRY(166),
14368 ICE_PTT_UNUSED_ENTRY(167),
14369 ICE_PTT_UNUSED_ENTRY(168),
14370 ICE_PTT_UNUSED_ENTRY(169),
14371
14372 ICE_PTT_UNUSED_ENTRY(170),
14373 ICE_PTT_UNUSED_ENTRY(171),
14374 ICE_PTT_UNUSED_ENTRY(172),
14375 ICE_PTT_UNUSED_ENTRY(173),
14376 ICE_PTT_UNUSED_ENTRY(174),
14377 ICE_PTT_UNUSED_ENTRY(175),
14378 ICE_PTT_UNUSED_ENTRY(176),
14379 ICE_PTT_UNUSED_ENTRY(177),
14380 ICE_PTT_UNUSED_ENTRY(178),
14381 ICE_PTT_UNUSED_ENTRY(179),
14382
14383 ICE_PTT_UNUSED_ENTRY(180),
14384 ICE_PTT_UNUSED_ENTRY(181),
14385 ICE_PTT_UNUSED_ENTRY(182),
14386 ICE_PTT_UNUSED_ENTRY(183),
14387 ICE_PTT_UNUSED_ENTRY(184),
14388 ICE_PTT_UNUSED_ENTRY(185),
14389 ICE_PTT_UNUSED_ENTRY(186),
14390 ICE_PTT_UNUSED_ENTRY(187),
14391 ICE_PTT_UNUSED_ENTRY(188),
14392 ICE_PTT_UNUSED_ENTRY(189),
14393
14394 ICE_PTT_UNUSED_ENTRY(190),
14395 ICE_PTT_UNUSED_ENTRY(191),
14396 ICE_PTT_UNUSED_ENTRY(192),
14397 ICE_PTT_UNUSED_ENTRY(193),
14398 ICE_PTT_UNUSED_ENTRY(194),
14399 ICE_PTT_UNUSED_ENTRY(195),
14400 ICE_PTT_UNUSED_ENTRY(196),
14401 ICE_PTT_UNUSED_ENTRY(197),
14402 ICE_PTT_UNUSED_ENTRY(198),
14403 ICE_PTT_UNUSED_ENTRY(199),
14404
14405 ICE_PTT_UNUSED_ENTRY(200),
14406 ICE_PTT_UNUSED_ENTRY(201),
14407 ICE_PTT_UNUSED_ENTRY(202),
14408 ICE_PTT_UNUSED_ENTRY(203),
14409 ICE_PTT_UNUSED_ENTRY(204),
14410 ICE_PTT_UNUSED_ENTRY(205),
14411 ICE_PTT_UNUSED_ENTRY(206),
14412 ICE_PTT_UNUSED_ENTRY(207),
14413 ICE_PTT_UNUSED_ENTRY(208),
14414 ICE_PTT_UNUSED_ENTRY(209),
14415
14416 ICE_PTT_UNUSED_ENTRY(210),
14417 ICE_PTT_UNUSED_ENTRY(211),
14418 ICE_PTT_UNUSED_ENTRY(212),
14419 ICE_PTT_UNUSED_ENTRY(213),
14420 ICE_PTT_UNUSED_ENTRY(214),
14421 ICE_PTT_UNUSED_ENTRY(215),
14422 ICE_PTT_UNUSED_ENTRY(216),
14423 ICE_PTT_UNUSED_ENTRY(217),
14424 ICE_PTT_UNUSED_ENTRY(218),
14425 ICE_PTT_UNUSED_ENTRY(219),
14426
14427 ICE_PTT_UNUSED_ENTRY(220),
14428 ICE_PTT_UNUSED_ENTRY(221),
14429 ICE_PTT_UNUSED_ENTRY(222),
14430 ICE_PTT_UNUSED_ENTRY(223),
14431 ICE_PTT_UNUSED_ENTRY(224),
14432 ICE_PTT_UNUSED_ENTRY(225),
14433 ICE_PTT_UNUSED_ENTRY(226),
14434 ICE_PTT_UNUSED_ENTRY(227),
14435 ICE_PTT_UNUSED_ENTRY(228),
14436 ICE_PTT_UNUSED_ENTRY(229),
14437
14438 ICE_PTT_UNUSED_ENTRY(230),
14439 ICE_PTT_UNUSED_ENTRY(231),
14440 ICE_PTT_UNUSED_ENTRY(232),
14441 ICE_PTT_UNUSED_ENTRY(233),
14442 ICE_PTT_UNUSED_ENTRY(234),
14443 ICE_PTT_UNUSED_ENTRY(235),
14444 ICE_PTT_UNUSED_ENTRY(236),
14445 ICE_PTT_UNUSED_ENTRY(237),
14446 ICE_PTT_UNUSED_ENTRY(238),
14447 ICE_PTT_UNUSED_ENTRY(239),
14448
14449 ICE_PTT_UNUSED_ENTRY(240),
14450 ICE_PTT_UNUSED_ENTRY(241),
14451 ICE_PTT_UNUSED_ENTRY(242),
14452 ICE_PTT_UNUSED_ENTRY(243),
14453 ICE_PTT_UNUSED_ENTRY(244),
14454 ICE_PTT_UNUSED_ENTRY(245),
14455 ICE_PTT_UNUSED_ENTRY(246),
14456 ICE_PTT_UNUSED_ENTRY(247),
14457 ICE_PTT_UNUSED_ENTRY(248),
14458 ICE_PTT_UNUSED_ENTRY(249),
14459
14460 ICE_PTT_UNUSED_ENTRY(250),
14461 ICE_PTT_UNUSED_ENTRY(251),
14462 ICE_PTT_UNUSED_ENTRY(252),
14463 ICE_PTT_UNUSED_ENTRY(253),
14464 ICE_PTT_UNUSED_ENTRY(254),
14465 ICE_PTT_UNUSED_ENTRY(255),
14466 ICE_PTT_UNUSED_ENTRY(256),
14467 ICE_PTT_UNUSED_ENTRY(257),
14468 ICE_PTT_UNUSED_ENTRY(258),
14469 ICE_PTT_UNUSED_ENTRY(259),
14470
14471 ICE_PTT_UNUSED_ENTRY(260),
14472 ICE_PTT_UNUSED_ENTRY(261),
14473 ICE_PTT_UNUSED_ENTRY(262),
14474 ICE_PTT_UNUSED_ENTRY(263),
14475 ICE_PTT_UNUSED_ENTRY(264),
14476 ICE_PTT_UNUSED_ENTRY(265),
14477 ICE_PTT_UNUSED_ENTRY(266),
14478 ICE_PTT_UNUSED_ENTRY(267),
14479 ICE_PTT_UNUSED_ENTRY(268),
14480 ICE_PTT_UNUSED_ENTRY(269),
14481
14482 ICE_PTT_UNUSED_ENTRY(270),
14483 ICE_PTT_UNUSED_ENTRY(271),
14484 ICE_PTT_UNUSED_ENTRY(272),
14485 ICE_PTT_UNUSED_ENTRY(273),
14486 ICE_PTT_UNUSED_ENTRY(274),
14487 ICE_PTT_UNUSED_ENTRY(275),
14488 ICE_PTT_UNUSED_ENTRY(276),
14489 ICE_PTT_UNUSED_ENTRY(277),
14490 ICE_PTT_UNUSED_ENTRY(278),
14491 ICE_PTT_UNUSED_ENTRY(279),
14492
14493 ICE_PTT_UNUSED_ENTRY(280),
14494 ICE_PTT_UNUSED_ENTRY(281),
14495 ICE_PTT_UNUSED_ENTRY(282),
14496 ICE_PTT_UNUSED_ENTRY(283),
14497 ICE_PTT_UNUSED_ENTRY(284),
14498 ICE_PTT_UNUSED_ENTRY(285),
14499 ICE_PTT_UNUSED_ENTRY(286),
14500 ICE_PTT_UNUSED_ENTRY(287),
14501 ICE_PTT_UNUSED_ENTRY(288),
14502 ICE_PTT_UNUSED_ENTRY(289),
14503
14504 ICE_PTT_UNUSED_ENTRY(290),
14505 ICE_PTT_UNUSED_ENTRY(291),
14506 ICE_PTT_UNUSED_ENTRY(292),
14507 ICE_PTT_UNUSED_ENTRY(293),
14508 ICE_PTT_UNUSED_ENTRY(294),
14509 ICE_PTT_UNUSED_ENTRY(295),
14510 ICE_PTT_UNUSED_ENTRY(296),
14511 ICE_PTT_UNUSED_ENTRY(297),
14512 ICE_PTT_UNUSED_ENTRY(298),
14513 ICE_PTT_UNUSED_ENTRY(299),
14514
14515 ICE_PTT_UNUSED_ENTRY(300),
14516 ICE_PTT_UNUSED_ENTRY(301),
14517 ICE_PTT_UNUSED_ENTRY(302),
14518 ICE_PTT_UNUSED_ENTRY(303),
14519 ICE_PTT_UNUSED_ENTRY(304),
14520 ICE_PTT_UNUSED_ENTRY(305),
14521 ICE_PTT_UNUSED_ENTRY(306),
14522 ICE_PTT_UNUSED_ENTRY(307),
14523 ICE_PTT_UNUSED_ENTRY(308),
14524 ICE_PTT_UNUSED_ENTRY(309),
14525
14526 ICE_PTT_UNUSED_ENTRY(310),
14527 ICE_PTT_UNUSED_ENTRY(311),
14528 ICE_PTT_UNUSED_ENTRY(312),
14529 ICE_PTT_UNUSED_ENTRY(313),
14530 ICE_PTT_UNUSED_ENTRY(314),
14531 ICE_PTT_UNUSED_ENTRY(315),
14532 ICE_PTT_UNUSED_ENTRY(316),
14533 ICE_PTT_UNUSED_ENTRY(317),
14534 ICE_PTT_UNUSED_ENTRY(318),
14535 ICE_PTT_UNUSED_ENTRY(319),
14536
14537 ICE_PTT_UNUSED_ENTRY(320),
14538 ICE_PTT_UNUSED_ENTRY(321),
14539 ICE_PTT_UNUSED_ENTRY(322),
14540 ICE_PTT_UNUSED_ENTRY(323),
14541 ICE_PTT_UNUSED_ENTRY(324),
14542 ICE_PTT_UNUSED_ENTRY(325),
14543 ICE_PTT_UNUSED_ENTRY(326),
14544 ICE_PTT_UNUSED_ENTRY(327),
14545 ICE_PTT_UNUSED_ENTRY(328),
14546 ICE_PTT_UNUSED_ENTRY(329),
14547
14548 ICE_PTT_UNUSED_ENTRY(330),
14549 ICE_PTT_UNUSED_ENTRY(331),
14550 ICE_PTT_UNUSED_ENTRY(332),
14551 ICE_PTT_UNUSED_ENTRY(333),
14552 ICE_PTT_UNUSED_ENTRY(334),
14553 ICE_PTT_UNUSED_ENTRY(335),
14554 ICE_PTT_UNUSED_ENTRY(336),
14555 ICE_PTT_UNUSED_ENTRY(337),
14556 ICE_PTT_UNUSED_ENTRY(338),
14557 ICE_PTT_UNUSED_ENTRY(339),
14558
14559 ICE_PTT_UNUSED_ENTRY(340),
14560 ICE_PTT_UNUSED_ENTRY(341),
14561 ICE_PTT_UNUSED_ENTRY(342),
14562 ICE_PTT_UNUSED_ENTRY(343),
14563 ICE_PTT_UNUSED_ENTRY(344),
14564 ICE_PTT_UNUSED_ENTRY(345),
14565 ICE_PTT_UNUSED_ENTRY(346),
14566 ICE_PTT_UNUSED_ENTRY(347),
14567 ICE_PTT_UNUSED_ENTRY(348),
14568 ICE_PTT_UNUSED_ENTRY(349),
14569
14570 ICE_PTT_UNUSED_ENTRY(350),
14571 ICE_PTT_UNUSED_ENTRY(351),
14572 ICE_PTT_UNUSED_ENTRY(352),
14573 ICE_PTT_UNUSED_ENTRY(353),
14574 ICE_PTT_UNUSED_ENTRY(354),
14575 ICE_PTT_UNUSED_ENTRY(355),
14576 ICE_PTT_UNUSED_ENTRY(356),
14577 ICE_PTT_UNUSED_ENTRY(357),
14578 ICE_PTT_UNUSED_ENTRY(358),
14579 ICE_PTT_UNUSED_ENTRY(359),
14580
14581 ICE_PTT_UNUSED_ENTRY(360),
14582 ICE_PTT_UNUSED_ENTRY(361),
14583 ICE_PTT_UNUSED_ENTRY(362),
14584 ICE_PTT_UNUSED_ENTRY(363),
14585 ICE_PTT_UNUSED_ENTRY(364),
14586 ICE_PTT_UNUSED_ENTRY(365),
14587 ICE_PTT_UNUSED_ENTRY(366),
14588 ICE_PTT_UNUSED_ENTRY(367),
14589 ICE_PTT_UNUSED_ENTRY(368),
14590 ICE_PTT_UNUSED_ENTRY(369),
14591
14592 ICE_PTT_UNUSED_ENTRY(370),
14593 ICE_PTT_UNUSED_ENTRY(371),
14594 ICE_PTT_UNUSED_ENTRY(372),
14595 ICE_PTT_UNUSED_ENTRY(373),
14596 ICE_PTT_UNUSED_ENTRY(374),
14597 ICE_PTT_UNUSED_ENTRY(375),
14598 ICE_PTT_UNUSED_ENTRY(376),
14599 ICE_PTT_UNUSED_ENTRY(377),
14600 ICE_PTT_UNUSED_ENTRY(378),
14601 ICE_PTT_UNUSED_ENTRY(379),
14602
14603 ICE_PTT_UNUSED_ENTRY(380),
14604 ICE_PTT_UNUSED_ENTRY(381),
14605 ICE_PTT_UNUSED_ENTRY(382),
14606 ICE_PTT_UNUSED_ENTRY(383),
14607 ICE_PTT_UNUSED_ENTRY(384),
14608 ICE_PTT_UNUSED_ENTRY(385),
14609 ICE_PTT_UNUSED_ENTRY(386),
14610 ICE_PTT_UNUSED_ENTRY(387),
14611 ICE_PTT_UNUSED_ENTRY(388),
14612 ICE_PTT_UNUSED_ENTRY(389),
14613
14614 ICE_PTT_UNUSED_ENTRY(390),
14615 ICE_PTT_UNUSED_ENTRY(391),
14616 ICE_PTT_UNUSED_ENTRY(392),
14617 ICE_PTT_UNUSED_ENTRY(393),
14618 ICE_PTT_UNUSED_ENTRY(394),
14619 ICE_PTT_UNUSED_ENTRY(395),
14620 ICE_PTT_UNUSED_ENTRY(396),
14621 ICE_PTT_UNUSED_ENTRY(397),
14622 ICE_PTT_UNUSED_ENTRY(398),
14623 ICE_PTT_UNUSED_ENTRY(399),
14624
14625 ICE_PTT_UNUSED_ENTRY(400),
14626 ICE_PTT_UNUSED_ENTRY(401),
14627 ICE_PTT_UNUSED_ENTRY(402),
14628 ICE_PTT_UNUSED_ENTRY(403),
14629 ICE_PTT_UNUSED_ENTRY(404),
14630 ICE_PTT_UNUSED_ENTRY(405),
14631 ICE_PTT_UNUSED_ENTRY(406),
14632 ICE_PTT_UNUSED_ENTRY(407),
14633 ICE_PTT_UNUSED_ENTRY(408),
14634 ICE_PTT_UNUSED_ENTRY(409),
14635
14636 ICE_PTT_UNUSED_ENTRY(410),
14637 ICE_PTT_UNUSED_ENTRY(411),
14638 ICE_PTT_UNUSED_ENTRY(412),
14639 ICE_PTT_UNUSED_ENTRY(413),
14640 ICE_PTT_UNUSED_ENTRY(414),
14641 ICE_PTT_UNUSED_ENTRY(415),
14642 ICE_PTT_UNUSED_ENTRY(416),
14643 ICE_PTT_UNUSED_ENTRY(417),
14644 ICE_PTT_UNUSED_ENTRY(418),
14645 ICE_PTT_UNUSED_ENTRY(419),
14646
14647 ICE_PTT_UNUSED_ENTRY(420),
14648 ICE_PTT_UNUSED_ENTRY(421),
14649 ICE_PTT_UNUSED_ENTRY(422),
14650 ICE_PTT_UNUSED_ENTRY(423),
14651 ICE_PTT_UNUSED_ENTRY(424),
14652 ICE_PTT_UNUSED_ENTRY(425),
14653 ICE_PTT_UNUSED_ENTRY(426),
14654 ICE_PTT_UNUSED_ENTRY(427),
14655 ICE_PTT_UNUSED_ENTRY(428),
14656 ICE_PTT_UNUSED_ENTRY(429),
14657
14658 ICE_PTT_UNUSED_ENTRY(430),
14659 ICE_PTT_UNUSED_ENTRY(431),
14660 ICE_PTT_UNUSED_ENTRY(432),
14661 ICE_PTT_UNUSED_ENTRY(433),
14662 ICE_PTT_UNUSED_ENTRY(434),
14663 ICE_PTT_UNUSED_ENTRY(435),
14664 ICE_PTT_UNUSED_ENTRY(436),
14665 ICE_PTT_UNUSED_ENTRY(437),
14666 ICE_PTT_UNUSED_ENTRY(438),
14667 ICE_PTT_UNUSED_ENTRY(439),
14668
14669 ICE_PTT_UNUSED_ENTRY(440),
14670 ICE_PTT_UNUSED_ENTRY(441),
14671 ICE_PTT_UNUSED_ENTRY(442),
14672 ICE_PTT_UNUSED_ENTRY(443),
14673 ICE_PTT_UNUSED_ENTRY(444),
14674 ICE_PTT_UNUSED_ENTRY(445),
14675 ICE_PTT_UNUSED_ENTRY(446),
14676 ICE_PTT_UNUSED_ENTRY(447),
14677 ICE_PTT_UNUSED_ENTRY(448),
14678 ICE_PTT_UNUSED_ENTRY(449),
14679
14680 ICE_PTT_UNUSED_ENTRY(450),
14681 ICE_PTT_UNUSED_ENTRY(451),
14682 ICE_PTT_UNUSED_ENTRY(452),
14683 ICE_PTT_UNUSED_ENTRY(453),
14684 ICE_PTT_UNUSED_ENTRY(454),
14685 ICE_PTT_UNUSED_ENTRY(455),
14686 ICE_PTT_UNUSED_ENTRY(456),
14687 ICE_PTT_UNUSED_ENTRY(457),
14688 ICE_PTT_UNUSED_ENTRY(458),
14689 ICE_PTT_UNUSED_ENTRY(459),
14690
14691 ICE_PTT_UNUSED_ENTRY(460),
14692 ICE_PTT_UNUSED_ENTRY(461),
14693 ICE_PTT_UNUSED_ENTRY(462),
14694 ICE_PTT_UNUSED_ENTRY(463),
14695 ICE_PTT_UNUSED_ENTRY(464),
14696 ICE_PTT_UNUSED_ENTRY(465),
14697 ICE_PTT_UNUSED_ENTRY(466),
14698 ICE_PTT_UNUSED_ENTRY(467),
14699 ICE_PTT_UNUSED_ENTRY(468),
14700 ICE_PTT_UNUSED_ENTRY(469),
14701
14702 ICE_PTT_UNUSED_ENTRY(470),
14703 ICE_PTT_UNUSED_ENTRY(471),
14704 ICE_PTT_UNUSED_ENTRY(472),
14705 ICE_PTT_UNUSED_ENTRY(473),
14706 ICE_PTT_UNUSED_ENTRY(474),
14707 ICE_PTT_UNUSED_ENTRY(475),
14708 ICE_PTT_UNUSED_ENTRY(476),
14709 ICE_PTT_UNUSED_ENTRY(477),
14710 ICE_PTT_UNUSED_ENTRY(478),
14711 ICE_PTT_UNUSED_ENTRY(479),
14712
14713 ICE_PTT_UNUSED_ENTRY(480),
14714 ICE_PTT_UNUSED_ENTRY(481),
14715 ICE_PTT_UNUSED_ENTRY(482),
14716 ICE_PTT_UNUSED_ENTRY(483),
14717 ICE_PTT_UNUSED_ENTRY(484),
14718 ICE_PTT_UNUSED_ENTRY(485),
14719 ICE_PTT_UNUSED_ENTRY(486),
14720 ICE_PTT_UNUSED_ENTRY(487),
14721 ICE_PTT_UNUSED_ENTRY(488),
14722 ICE_PTT_UNUSED_ENTRY(489),
14723
14724 ICE_PTT_UNUSED_ENTRY(490),
14725 ICE_PTT_UNUSED_ENTRY(491),
14726 ICE_PTT_UNUSED_ENTRY(492),
14727 ICE_PTT_UNUSED_ENTRY(493),
14728 ICE_PTT_UNUSED_ENTRY(494),
14729 ICE_PTT_UNUSED_ENTRY(495),
14730 ICE_PTT_UNUSED_ENTRY(496),
14731 ICE_PTT_UNUSED_ENTRY(497),
14732 ICE_PTT_UNUSED_ENTRY(498),
14733 ICE_PTT_UNUSED_ENTRY(499),
14734
14735 ICE_PTT_UNUSED_ENTRY(500),
14736 ICE_PTT_UNUSED_ENTRY(501),
14737 ICE_PTT_UNUSED_ENTRY(502),
14738 ICE_PTT_UNUSED_ENTRY(503),
14739 ICE_PTT_UNUSED_ENTRY(504),
14740 ICE_PTT_UNUSED_ENTRY(505),
14741 ICE_PTT_UNUSED_ENTRY(506),
14742 ICE_PTT_UNUSED_ENTRY(507),
14743 ICE_PTT_UNUSED_ENTRY(508),
14744 ICE_PTT_UNUSED_ENTRY(509),
14745
14746 ICE_PTT_UNUSED_ENTRY(510),
14747 ICE_PTT_UNUSED_ENTRY(511),
14748 ICE_PTT_UNUSED_ENTRY(512),
14749 ICE_PTT_UNUSED_ENTRY(513),
14750 ICE_PTT_UNUSED_ENTRY(514),
14751 ICE_PTT_UNUSED_ENTRY(515),
14752 ICE_PTT_UNUSED_ENTRY(516),
14753 ICE_PTT_UNUSED_ENTRY(517),
14754 ICE_PTT_UNUSED_ENTRY(518),
14755 ICE_PTT_UNUSED_ENTRY(519),
14756
14757 ICE_PTT_UNUSED_ENTRY(520),
14758 ICE_PTT_UNUSED_ENTRY(521),
14759 ICE_PTT_UNUSED_ENTRY(522),
14760 ICE_PTT_UNUSED_ENTRY(523),
14761 ICE_PTT_UNUSED_ENTRY(524),
14762 ICE_PTT_UNUSED_ENTRY(525),
14763 ICE_PTT_UNUSED_ENTRY(526),
14764 ICE_PTT_UNUSED_ENTRY(527),
14765 ICE_PTT_UNUSED_ENTRY(528),
14766 ICE_PTT_UNUSED_ENTRY(529),
14767
14768 ICE_PTT_UNUSED_ENTRY(530),
14769 ICE_PTT_UNUSED_ENTRY(531),
14770 ICE_PTT_UNUSED_ENTRY(532),
14771 ICE_PTT_UNUSED_ENTRY(533),
14772 ICE_PTT_UNUSED_ENTRY(534),
14773 ICE_PTT_UNUSED_ENTRY(535),
14774 ICE_PTT_UNUSED_ENTRY(536),
14775 ICE_PTT_UNUSED_ENTRY(537),
14776 ICE_PTT_UNUSED_ENTRY(538),
14777 ICE_PTT_UNUSED_ENTRY(539),
14778
14779 ICE_PTT_UNUSED_ENTRY(540),
14780 ICE_PTT_UNUSED_ENTRY(541),
14781 ICE_PTT_UNUSED_ENTRY(542),
14782 ICE_PTT_UNUSED_ENTRY(543),
14783 ICE_PTT_UNUSED_ENTRY(544),
14784 ICE_PTT_UNUSED_ENTRY(545),
14785 ICE_PTT_UNUSED_ENTRY(546),
14786 ICE_PTT_UNUSED_ENTRY(547),
14787 ICE_PTT_UNUSED_ENTRY(548),
14788 ICE_PTT_UNUSED_ENTRY(549),
14789
14790 ICE_PTT_UNUSED_ENTRY(550),
14791 ICE_PTT_UNUSED_ENTRY(551),
14792 ICE_PTT_UNUSED_ENTRY(552),
14793 ICE_PTT_UNUSED_ENTRY(553),
14794 ICE_PTT_UNUSED_ENTRY(554),
14795 ICE_PTT_UNUSED_ENTRY(555),
14796 ICE_PTT_UNUSED_ENTRY(556),
14797 ICE_PTT_UNUSED_ENTRY(557),
14798 ICE_PTT_UNUSED_ENTRY(558),
14799 ICE_PTT_UNUSED_ENTRY(559),
14800
14801 ICE_PTT_UNUSED_ENTRY(560),
14802 ICE_PTT_UNUSED_ENTRY(561),
14803 ICE_PTT_UNUSED_ENTRY(562),
14804 ICE_PTT_UNUSED_ENTRY(563),
14805 ICE_PTT_UNUSED_ENTRY(564),
14806 ICE_PTT_UNUSED_ENTRY(565),
14807 ICE_PTT_UNUSED_ENTRY(566),
14808 ICE_PTT_UNUSED_ENTRY(567),
14809 ICE_PTT_UNUSED_ENTRY(568),
14810 ICE_PTT_UNUSED_ENTRY(569),
14811
14812 ICE_PTT_UNUSED_ENTRY(570),
14813 ICE_PTT_UNUSED_ENTRY(571),
14814 ICE_PTT_UNUSED_ENTRY(572),
14815 ICE_PTT_UNUSED_ENTRY(573),
14816 ICE_PTT_UNUSED_ENTRY(574),
14817 ICE_PTT_UNUSED_ENTRY(575),
14818 ICE_PTT_UNUSED_ENTRY(576),
14819 ICE_PTT_UNUSED_ENTRY(577),
14820 ICE_PTT_UNUSED_ENTRY(578),
14821 ICE_PTT_UNUSED_ENTRY(579),
14822
14823 ICE_PTT_UNUSED_ENTRY(580),
14824 ICE_PTT_UNUSED_ENTRY(581),
14825 ICE_PTT_UNUSED_ENTRY(582),
14826 ICE_PTT_UNUSED_ENTRY(583),
14827 ICE_PTT_UNUSED_ENTRY(584),
14828 ICE_PTT_UNUSED_ENTRY(585),
14829 ICE_PTT_UNUSED_ENTRY(586),
14830 ICE_PTT_UNUSED_ENTRY(587),
14831 ICE_PTT_UNUSED_ENTRY(588),
14832 ICE_PTT_UNUSED_ENTRY(589),
14833
14834 ICE_PTT_UNUSED_ENTRY(590),
14835 ICE_PTT_UNUSED_ENTRY(591),
14836 ICE_PTT_UNUSED_ENTRY(592),
14837 ICE_PTT_UNUSED_ENTRY(593),
14838 ICE_PTT_UNUSED_ENTRY(594),
14839 ICE_PTT_UNUSED_ENTRY(595),
14840 ICE_PTT_UNUSED_ENTRY(596),
14841 ICE_PTT_UNUSED_ENTRY(597),
14842 ICE_PTT_UNUSED_ENTRY(598),
14843 ICE_PTT_UNUSED_ENTRY(599),
14844
14845 ICE_PTT_UNUSED_ENTRY(600),
14846 ICE_PTT_UNUSED_ENTRY(601),
14847 ICE_PTT_UNUSED_ENTRY(602),
14848 ICE_PTT_UNUSED_ENTRY(603),
14849 ICE_PTT_UNUSED_ENTRY(604),
14850 ICE_PTT_UNUSED_ENTRY(605),
14851 ICE_PTT_UNUSED_ENTRY(606),
14852 ICE_PTT_UNUSED_ENTRY(607),
14853 ICE_PTT_UNUSED_ENTRY(608),
14854 ICE_PTT_UNUSED_ENTRY(609),
14855
14856 ICE_PTT_UNUSED_ENTRY(610),
14857 ICE_PTT_UNUSED_ENTRY(611),
14858 ICE_PTT_UNUSED_ENTRY(612),
14859 ICE_PTT_UNUSED_ENTRY(613),
14860 ICE_PTT_UNUSED_ENTRY(614),
14861 ICE_PTT_UNUSED_ENTRY(615),
14862 ICE_PTT_UNUSED_ENTRY(616),
14863 ICE_PTT_UNUSED_ENTRY(617),
14864 ICE_PTT_UNUSED_ENTRY(618),
14865 ICE_PTT_UNUSED_ENTRY(619),
14866
14867 ICE_PTT_UNUSED_ENTRY(620),
14868 ICE_PTT_UNUSED_ENTRY(621),
14869 ICE_PTT_UNUSED_ENTRY(622),
14870 ICE_PTT_UNUSED_ENTRY(623),
14871 ICE_PTT_UNUSED_ENTRY(624),
14872 ICE_PTT_UNUSED_ENTRY(625),
14873 ICE_PTT_UNUSED_ENTRY(626),
14874 ICE_PTT_UNUSED_ENTRY(627),
14875 ICE_PTT_UNUSED_ENTRY(628),
14876 ICE_PTT_UNUSED_ENTRY(629),
14877
14878 ICE_PTT_UNUSED_ENTRY(630),
14879 ICE_PTT_UNUSED_ENTRY(631),
14880 ICE_PTT_UNUSED_ENTRY(632),
14881 ICE_PTT_UNUSED_ENTRY(633),
14882 ICE_PTT_UNUSED_ENTRY(634),
14883 ICE_PTT_UNUSED_ENTRY(635),
14884 ICE_PTT_UNUSED_ENTRY(636),
14885 ICE_PTT_UNUSED_ENTRY(637),
14886 ICE_PTT_UNUSED_ENTRY(638),
14887 ICE_PTT_UNUSED_ENTRY(639),
14888
14889 ICE_PTT_UNUSED_ENTRY(640),
14890 ICE_PTT_UNUSED_ENTRY(641),
14891 ICE_PTT_UNUSED_ENTRY(642),
14892 ICE_PTT_UNUSED_ENTRY(643),
14893 ICE_PTT_UNUSED_ENTRY(644),
14894 ICE_PTT_UNUSED_ENTRY(645),
14895 ICE_PTT_UNUSED_ENTRY(646),
14896 ICE_PTT_UNUSED_ENTRY(647),
14897 ICE_PTT_UNUSED_ENTRY(648),
14898 ICE_PTT_UNUSED_ENTRY(649),
14899
14900 ICE_PTT_UNUSED_ENTRY(650),
14901 ICE_PTT_UNUSED_ENTRY(651),
14902 ICE_PTT_UNUSED_ENTRY(652),
14903 ICE_PTT_UNUSED_ENTRY(653),
14904 ICE_PTT_UNUSED_ENTRY(654),
14905 ICE_PTT_UNUSED_ENTRY(655),
14906 ICE_PTT_UNUSED_ENTRY(656),
14907 ICE_PTT_UNUSED_ENTRY(657),
14908 ICE_PTT_UNUSED_ENTRY(658),
14909 ICE_PTT_UNUSED_ENTRY(659),
14910
14911 ICE_PTT_UNUSED_ENTRY(660),
14912 ICE_PTT_UNUSED_ENTRY(661),
14913 ICE_PTT_UNUSED_ENTRY(662),
14914 ICE_PTT_UNUSED_ENTRY(663),
14915 ICE_PTT_UNUSED_ENTRY(664),
14916 ICE_PTT_UNUSED_ENTRY(665),
14917 ICE_PTT_UNUSED_ENTRY(666),
14918 ICE_PTT_UNUSED_ENTRY(667),
14919 ICE_PTT_UNUSED_ENTRY(668),
14920 ICE_PTT_UNUSED_ENTRY(669),
14921
14922 ICE_PTT_UNUSED_ENTRY(670),
14923 ICE_PTT_UNUSED_ENTRY(671),
14924 ICE_PTT_UNUSED_ENTRY(672),
14925 ICE_PTT_UNUSED_ENTRY(673),
14926 ICE_PTT_UNUSED_ENTRY(674),
14927 ICE_PTT_UNUSED_ENTRY(675),
14928 ICE_PTT_UNUSED_ENTRY(676),
14929 ICE_PTT_UNUSED_ENTRY(677),
14930 ICE_PTT_UNUSED_ENTRY(678),
14931 ICE_PTT_UNUSED_ENTRY(679),
14932
14933 ICE_PTT_UNUSED_ENTRY(680),
14934 ICE_PTT_UNUSED_ENTRY(681),
14935 ICE_PTT_UNUSED_ENTRY(682),
14936 ICE_PTT_UNUSED_ENTRY(683),
14937 ICE_PTT_UNUSED_ENTRY(684),
14938 ICE_PTT_UNUSED_ENTRY(685),
14939 ICE_PTT_UNUSED_ENTRY(686),
14940 ICE_PTT_UNUSED_ENTRY(687),
14941 ICE_PTT_UNUSED_ENTRY(688),
14942 ICE_PTT_UNUSED_ENTRY(689),
14943
14944 ICE_PTT_UNUSED_ENTRY(690),
14945 ICE_PTT_UNUSED_ENTRY(691),
14946 ICE_PTT_UNUSED_ENTRY(692),
14947 ICE_PTT_UNUSED_ENTRY(693),
14948 ICE_PTT_UNUSED_ENTRY(694),
14949 ICE_PTT_UNUSED_ENTRY(695),
14950 ICE_PTT_UNUSED_ENTRY(696),
14951 ICE_PTT_UNUSED_ENTRY(697),
14952 ICE_PTT_UNUSED_ENTRY(698),
14953 ICE_PTT_UNUSED_ENTRY(699),
14954
14955 ICE_PTT_UNUSED_ENTRY(700),
14956 ICE_PTT_UNUSED_ENTRY(701),
14957 ICE_PTT_UNUSED_ENTRY(702),
14958 ICE_PTT_UNUSED_ENTRY(703),
14959 ICE_PTT_UNUSED_ENTRY(704),
14960 ICE_PTT_UNUSED_ENTRY(705),
14961 ICE_PTT_UNUSED_ENTRY(706),
14962 ICE_PTT_UNUSED_ENTRY(707),
14963 ICE_PTT_UNUSED_ENTRY(708),
14964 ICE_PTT_UNUSED_ENTRY(709),
14965
14966 ICE_PTT_UNUSED_ENTRY(710),
14967 ICE_PTT_UNUSED_ENTRY(711),
14968 ICE_PTT_UNUSED_ENTRY(712),
14969 ICE_PTT_UNUSED_ENTRY(713),
14970 ICE_PTT_UNUSED_ENTRY(714),
14971 ICE_PTT_UNUSED_ENTRY(715),
14972 ICE_PTT_UNUSED_ENTRY(716),
14973 ICE_PTT_UNUSED_ENTRY(717),
14974 ICE_PTT_UNUSED_ENTRY(718),
14975 ICE_PTT_UNUSED_ENTRY(719),
14976
14977 ICE_PTT_UNUSED_ENTRY(720),
14978 ICE_PTT_UNUSED_ENTRY(721),
14979 ICE_PTT_UNUSED_ENTRY(722),
14980 ICE_PTT_UNUSED_ENTRY(723),
14981 ICE_PTT_UNUSED_ENTRY(724),
14982 ICE_PTT_UNUSED_ENTRY(725),
14983 ICE_PTT_UNUSED_ENTRY(726),
14984 ICE_PTT_UNUSED_ENTRY(727),
14985 ICE_PTT_UNUSED_ENTRY(728),
14986 ICE_PTT_UNUSED_ENTRY(729),
14987
14988 ICE_PTT_UNUSED_ENTRY(730),
14989 ICE_PTT_UNUSED_ENTRY(731),
14990 ICE_PTT_UNUSED_ENTRY(732),
14991 ICE_PTT_UNUSED_ENTRY(733),
14992 ICE_PTT_UNUSED_ENTRY(734),
14993 ICE_PTT_UNUSED_ENTRY(735),
14994 ICE_PTT_UNUSED_ENTRY(736),
14995 ICE_PTT_UNUSED_ENTRY(737),
14996 ICE_PTT_UNUSED_ENTRY(738),
14997 ICE_PTT_UNUSED_ENTRY(739),
14998
14999 ICE_PTT_UNUSED_ENTRY(740),
15000 ICE_PTT_UNUSED_ENTRY(741),
15001 ICE_PTT_UNUSED_ENTRY(742),
15002 ICE_PTT_UNUSED_ENTRY(743),
15003 ICE_PTT_UNUSED_ENTRY(744),
15004 ICE_PTT_UNUSED_ENTRY(745),
15005 ICE_PTT_UNUSED_ENTRY(746),
15006 ICE_PTT_UNUSED_ENTRY(747),
15007 ICE_PTT_UNUSED_ENTRY(748),
15008 ICE_PTT_UNUSED_ENTRY(749),
15009
15010 ICE_PTT_UNUSED_ENTRY(750),
15011 ICE_PTT_UNUSED_ENTRY(751),
15012 ICE_PTT_UNUSED_ENTRY(752),
15013 ICE_PTT_UNUSED_ENTRY(753),
15014 ICE_PTT_UNUSED_ENTRY(754),
15015 ICE_PTT_UNUSED_ENTRY(755),
15016 ICE_PTT_UNUSED_ENTRY(756),
15017 ICE_PTT_UNUSED_ENTRY(757),
15018 ICE_PTT_UNUSED_ENTRY(758),
15019 ICE_PTT_UNUSED_ENTRY(759),
15020
15021 ICE_PTT_UNUSED_ENTRY(760),
15022 ICE_PTT_UNUSED_ENTRY(761),
15023 ICE_PTT_UNUSED_ENTRY(762),
15024 ICE_PTT_UNUSED_ENTRY(763),
15025 ICE_PTT_UNUSED_ENTRY(764),
15026 ICE_PTT_UNUSED_ENTRY(765),
15027 ICE_PTT_UNUSED_ENTRY(766),
15028 ICE_PTT_UNUSED_ENTRY(767),
15029 ICE_PTT_UNUSED_ENTRY(768),
15030 ICE_PTT_UNUSED_ENTRY(769),
15031
15032 ICE_PTT_UNUSED_ENTRY(770),
15033 ICE_PTT_UNUSED_ENTRY(771),
15034 ICE_PTT_UNUSED_ENTRY(772),
15035 ICE_PTT_UNUSED_ENTRY(773),
15036 ICE_PTT_UNUSED_ENTRY(774),
15037 ICE_PTT_UNUSED_ENTRY(775),
15038 ICE_PTT_UNUSED_ENTRY(776),
15039 ICE_PTT_UNUSED_ENTRY(777),
15040 ICE_PTT_UNUSED_ENTRY(778),
15041 ICE_PTT_UNUSED_ENTRY(779),
15042
15043 ICE_PTT_UNUSED_ENTRY(780),
15044 ICE_PTT_UNUSED_ENTRY(781),
15045 ICE_PTT_UNUSED_ENTRY(782),
15046 ICE_PTT_UNUSED_ENTRY(783),
15047 ICE_PTT_UNUSED_ENTRY(784),
15048 ICE_PTT_UNUSED_ENTRY(785),
15049 ICE_PTT_UNUSED_ENTRY(786),
15050 ICE_PTT_UNUSED_ENTRY(787),
15051 ICE_PTT_UNUSED_ENTRY(788),
15052 ICE_PTT_UNUSED_ENTRY(789),
15053
15054 ICE_PTT_UNUSED_ENTRY(790),
15055 ICE_PTT_UNUSED_ENTRY(791),
15056 ICE_PTT_UNUSED_ENTRY(792),
15057 ICE_PTT_UNUSED_ENTRY(793),
15058 ICE_PTT_UNUSED_ENTRY(794),
15059 ICE_PTT_UNUSED_ENTRY(795),
15060 ICE_PTT_UNUSED_ENTRY(796),
15061 ICE_PTT_UNUSED_ENTRY(797),
15062 ICE_PTT_UNUSED_ENTRY(798),
15063 ICE_PTT_UNUSED_ENTRY(799),
15064
15065 ICE_PTT_UNUSED_ENTRY(800),
15066 ICE_PTT_UNUSED_ENTRY(801),
15067 ICE_PTT_UNUSED_ENTRY(802),
15068 ICE_PTT_UNUSED_ENTRY(803),
15069 ICE_PTT_UNUSED_ENTRY(804),
15070 ICE_PTT_UNUSED_ENTRY(805),
15071 ICE_PTT_UNUSED_ENTRY(806),
15072 ICE_PTT_UNUSED_ENTRY(807),
15073 ICE_PTT_UNUSED_ENTRY(808),
15074 ICE_PTT_UNUSED_ENTRY(809),
15075
15076 ICE_PTT_UNUSED_ENTRY(810),
15077 ICE_PTT_UNUSED_ENTRY(811),
15078 ICE_PTT_UNUSED_ENTRY(812),
15079 ICE_PTT_UNUSED_ENTRY(813),
15080 ICE_PTT_UNUSED_ENTRY(814),
15081 ICE_PTT_UNUSED_ENTRY(815),
15082 ICE_PTT_UNUSED_ENTRY(816),
15083 ICE_PTT_UNUSED_ENTRY(817),
15084 ICE_PTT_UNUSED_ENTRY(818),
15085 ICE_PTT_UNUSED_ENTRY(819),
15086
15087 ICE_PTT_UNUSED_ENTRY(820),
15088 ICE_PTT_UNUSED_ENTRY(821),
15089 ICE_PTT_UNUSED_ENTRY(822),
15090 ICE_PTT_UNUSED_ENTRY(823),
15091 ICE_PTT_UNUSED_ENTRY(824),
15092 ICE_PTT_UNUSED_ENTRY(825),
15093 ICE_PTT_UNUSED_ENTRY(826),
15094 ICE_PTT_UNUSED_ENTRY(827),
15095 ICE_PTT_UNUSED_ENTRY(828),
15096 ICE_PTT_UNUSED_ENTRY(829),
15097
15098 ICE_PTT_UNUSED_ENTRY(830),
15099 ICE_PTT_UNUSED_ENTRY(831),
15100 ICE_PTT_UNUSED_ENTRY(832),
15101 ICE_PTT_UNUSED_ENTRY(833),
15102 ICE_PTT_UNUSED_ENTRY(834),
15103 ICE_PTT_UNUSED_ENTRY(835),
15104 ICE_PTT_UNUSED_ENTRY(836),
15105 ICE_PTT_UNUSED_ENTRY(837),
15106 ICE_PTT_UNUSED_ENTRY(838),
15107 ICE_PTT_UNUSED_ENTRY(839),
15108
15109 ICE_PTT_UNUSED_ENTRY(840),
15110 ICE_PTT_UNUSED_ENTRY(841),
15111 ICE_PTT_UNUSED_ENTRY(842),
15112 ICE_PTT_UNUSED_ENTRY(843),
15113 ICE_PTT_UNUSED_ENTRY(844),
15114 ICE_PTT_UNUSED_ENTRY(845),
15115 ICE_PTT_UNUSED_ENTRY(846),
15116 ICE_PTT_UNUSED_ENTRY(847),
15117 ICE_PTT_UNUSED_ENTRY(848),
15118 ICE_PTT_UNUSED_ENTRY(849),
15119
15120 ICE_PTT_UNUSED_ENTRY(850),
15121 ICE_PTT_UNUSED_ENTRY(851),
15122 ICE_PTT_UNUSED_ENTRY(852),
15123 ICE_PTT_UNUSED_ENTRY(853),
15124 ICE_PTT_UNUSED_ENTRY(854),
15125 ICE_PTT_UNUSED_ENTRY(855),
15126 ICE_PTT_UNUSED_ENTRY(856),
15127 ICE_PTT_UNUSED_ENTRY(857),
15128 ICE_PTT_UNUSED_ENTRY(858),
15129 ICE_PTT_UNUSED_ENTRY(859),
15130
15131 ICE_PTT_UNUSED_ENTRY(860),
15132 ICE_PTT_UNUSED_ENTRY(861),
15133 ICE_PTT_UNUSED_ENTRY(862),
15134 ICE_PTT_UNUSED_ENTRY(863),
15135 ICE_PTT_UNUSED_ENTRY(864),
15136 ICE_PTT_UNUSED_ENTRY(865),
15137 ICE_PTT_UNUSED_ENTRY(866),
15138 ICE_PTT_UNUSED_ENTRY(867),
15139 ICE_PTT_UNUSED_ENTRY(868),
15140 ICE_PTT_UNUSED_ENTRY(869),
15141
15142 ICE_PTT_UNUSED_ENTRY(870),
15143 ICE_PTT_UNUSED_ENTRY(871),
15144 ICE_PTT_UNUSED_ENTRY(872),
15145 ICE_PTT_UNUSED_ENTRY(873),
15146 ICE_PTT_UNUSED_ENTRY(874),
15147 ICE_PTT_UNUSED_ENTRY(875),
15148 ICE_PTT_UNUSED_ENTRY(876),
15149 ICE_PTT_UNUSED_ENTRY(877),
15150 ICE_PTT_UNUSED_ENTRY(878),
15151 ICE_PTT_UNUSED_ENTRY(879),
15152
15153 ICE_PTT_UNUSED_ENTRY(880),
15154 ICE_PTT_UNUSED_ENTRY(881),
15155 ICE_PTT_UNUSED_ENTRY(882),
15156 ICE_PTT_UNUSED_ENTRY(883),
15157 ICE_PTT_UNUSED_ENTRY(884),
15158 ICE_PTT_UNUSED_ENTRY(885),
15159 ICE_PTT_UNUSED_ENTRY(886),
15160 ICE_PTT_UNUSED_ENTRY(887),
15161 ICE_PTT_UNUSED_ENTRY(888),
15162 ICE_PTT_UNUSED_ENTRY(889),
15163
15164 ICE_PTT_UNUSED_ENTRY(890),
15165 ICE_PTT_UNUSED_ENTRY(891),
15166 ICE_PTT_UNUSED_ENTRY(892),
15167 ICE_PTT_UNUSED_ENTRY(893),
15168 ICE_PTT_UNUSED_ENTRY(894),
15169 ICE_PTT_UNUSED_ENTRY(895),
15170 ICE_PTT_UNUSED_ENTRY(896),
15171 ICE_PTT_UNUSED_ENTRY(897),
15172 ICE_PTT_UNUSED_ENTRY(898),
15173 ICE_PTT_UNUSED_ENTRY(899),
15174
15175 ICE_PTT_UNUSED_ENTRY(900),
15176 ICE_PTT_UNUSED_ENTRY(901),
15177 ICE_PTT_UNUSED_ENTRY(902),
15178 ICE_PTT_UNUSED_ENTRY(903),
15179 ICE_PTT_UNUSED_ENTRY(904),
15180 ICE_PTT_UNUSED_ENTRY(905),
15181 ICE_PTT_UNUSED_ENTRY(906),
15182 ICE_PTT_UNUSED_ENTRY(907),
15183 ICE_PTT_UNUSED_ENTRY(908),
15184 ICE_PTT_UNUSED_ENTRY(909),
15185
15186 ICE_PTT_UNUSED_ENTRY(910),
15187 ICE_PTT_UNUSED_ENTRY(911),
15188 ICE_PTT_UNUSED_ENTRY(912),
15189 ICE_PTT_UNUSED_ENTRY(913),
15190 ICE_PTT_UNUSED_ENTRY(914),
15191 ICE_PTT_UNUSED_ENTRY(915),
15192 ICE_PTT_UNUSED_ENTRY(916),
15193 ICE_PTT_UNUSED_ENTRY(917),
15194 ICE_PTT_UNUSED_ENTRY(918),
15195 ICE_PTT_UNUSED_ENTRY(919),
15196
15197 ICE_PTT_UNUSED_ENTRY(920),
15198 ICE_PTT_UNUSED_ENTRY(921),
15199 ICE_PTT_UNUSED_ENTRY(922),
15200 ICE_PTT_UNUSED_ENTRY(923),
15201 ICE_PTT_UNUSED_ENTRY(924),
15202 ICE_PTT_UNUSED_ENTRY(925),
15203 ICE_PTT_UNUSED_ENTRY(926),
15204 ICE_PTT_UNUSED_ENTRY(927),
15205 ICE_PTT_UNUSED_ENTRY(928),
15206 ICE_PTT_UNUSED_ENTRY(929),
15207
15208 ICE_PTT_UNUSED_ENTRY(930),
15209 ICE_PTT_UNUSED_ENTRY(931),
15210 ICE_PTT_UNUSED_ENTRY(932),
15211 ICE_PTT_UNUSED_ENTRY(933),
15212 ICE_PTT_UNUSED_ENTRY(934),
15213 ICE_PTT_UNUSED_ENTRY(935),
15214 ICE_PTT_UNUSED_ENTRY(936),
15215 ICE_PTT_UNUSED_ENTRY(937),
15216 ICE_PTT_UNUSED_ENTRY(938),
15217 ICE_PTT_UNUSED_ENTRY(939),
15218
15219 ICE_PTT_UNUSED_ENTRY(940),
15220 ICE_PTT_UNUSED_ENTRY(941),
15221 ICE_PTT_UNUSED_ENTRY(942),
15222 ICE_PTT_UNUSED_ENTRY(943),
15223 ICE_PTT_UNUSED_ENTRY(944),
15224 ICE_PTT_UNUSED_ENTRY(945),
15225 ICE_PTT_UNUSED_ENTRY(946),
15226 ICE_PTT_UNUSED_ENTRY(947),
15227 ICE_PTT_UNUSED_ENTRY(948),
15228 ICE_PTT_UNUSED_ENTRY(949),
15229
15230 ICE_PTT_UNUSED_ENTRY(950),
15231 ICE_PTT_UNUSED_ENTRY(951),
15232 ICE_PTT_UNUSED_ENTRY(952),
15233 ICE_PTT_UNUSED_ENTRY(953),
15234 ICE_PTT_UNUSED_ENTRY(954),
15235 ICE_PTT_UNUSED_ENTRY(955),
15236 ICE_PTT_UNUSED_ENTRY(956),
15237 ICE_PTT_UNUSED_ENTRY(957),
15238 ICE_PTT_UNUSED_ENTRY(958),
15239 ICE_PTT_UNUSED_ENTRY(959),
15240
15241 ICE_PTT_UNUSED_ENTRY(960),
15242 ICE_PTT_UNUSED_ENTRY(961),
15243 ICE_PTT_UNUSED_ENTRY(962),
15244 ICE_PTT_UNUSED_ENTRY(963),
15245 ICE_PTT_UNUSED_ENTRY(964),
15246 ICE_PTT_UNUSED_ENTRY(965),
15247 ICE_PTT_UNUSED_ENTRY(966),
15248 ICE_PTT_UNUSED_ENTRY(967),
15249 ICE_PTT_UNUSED_ENTRY(968),
15250 ICE_PTT_UNUSED_ENTRY(969),
15251
15252 ICE_PTT_UNUSED_ENTRY(970),
15253 ICE_PTT_UNUSED_ENTRY(971),
15254 ICE_PTT_UNUSED_ENTRY(972),
15255 ICE_PTT_UNUSED_ENTRY(973),
15256 ICE_PTT_UNUSED_ENTRY(974),
15257 ICE_PTT_UNUSED_ENTRY(975),
15258 ICE_PTT_UNUSED_ENTRY(976),
15259 ICE_PTT_UNUSED_ENTRY(977),
15260 ICE_PTT_UNUSED_ENTRY(978),
15261 ICE_PTT_UNUSED_ENTRY(979),
15262
15263 ICE_PTT_UNUSED_ENTRY(980),
15264 ICE_PTT_UNUSED_ENTRY(981),
15265 ICE_PTT_UNUSED_ENTRY(982),
15266 ICE_PTT_UNUSED_ENTRY(983),
15267 ICE_PTT_UNUSED_ENTRY(984),
15268 ICE_PTT_UNUSED_ENTRY(985),
15269 ICE_PTT_UNUSED_ENTRY(986),
15270 ICE_PTT_UNUSED_ENTRY(987),
15271 ICE_PTT_UNUSED_ENTRY(988),
15272 ICE_PTT_UNUSED_ENTRY(989),
15273
15274 ICE_PTT_UNUSED_ENTRY(990),
15275 ICE_PTT_UNUSED_ENTRY(991),
15276 ICE_PTT_UNUSED_ENTRY(992),
15277 ICE_PTT_UNUSED_ENTRY(993),
15278 ICE_PTT_UNUSED_ENTRY(994),
15279 ICE_PTT_UNUSED_ENTRY(995),
15280 ICE_PTT_UNUSED_ENTRY(996),
15281 ICE_PTT_UNUSED_ENTRY(997),
15282 ICE_PTT_UNUSED_ENTRY(998),
15283 ICE_PTT_UNUSED_ENTRY(999),
15284
15285 ICE_PTT_UNUSED_ENTRY(1000),
15286 ICE_PTT_UNUSED_ENTRY(1001),
15287 ICE_PTT_UNUSED_ENTRY(1002),
15288 ICE_PTT_UNUSED_ENTRY(1003),
15289 ICE_PTT_UNUSED_ENTRY(1004),
15290 ICE_PTT_UNUSED_ENTRY(1005),
15291 ICE_PTT_UNUSED_ENTRY(1006),
15292 ICE_PTT_UNUSED_ENTRY(1007),
15293 ICE_PTT_UNUSED_ENTRY(1008),
15294 ICE_PTT_UNUSED_ENTRY(1009),
15295
15296 ICE_PTT_UNUSED_ENTRY(1010),
15297 ICE_PTT_UNUSED_ENTRY(1011),
15298 ICE_PTT_UNUSED_ENTRY(1012),
15299 ICE_PTT_UNUSED_ENTRY(1013),
15300 ICE_PTT_UNUSED_ENTRY(1014),
15301 ICE_PTT_UNUSED_ENTRY(1015),
15302 ICE_PTT_UNUSED_ENTRY(1016),
15303 ICE_PTT_UNUSED_ENTRY(1017),
15304 ICE_PTT_UNUSED_ENTRY(1018),
15305 ICE_PTT_UNUSED_ENTRY(1019),
15306
15307 ICE_PTT_UNUSED_ENTRY(1020),
15308 ICE_PTT_UNUSED_ENTRY(1021),
15309 ICE_PTT_UNUSED_ENTRY(1022),
15310 ICE_PTT_UNUSED_ENTRY(1023)
15311 };
15312
ice_decode_rx_desc_ptype(uint16_t ptype)15313 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(uint16_t ptype)
15314 {
15315 return ice_ptype_lkup[ptype];
15316 }
15317
15318 #define ICE_LINK_SPEED_UNKNOWN 0
15319 #define ICE_LINK_SPEED_10MBPS 10
15320 #define ICE_LINK_SPEED_100MBPS 100
15321 #define ICE_LINK_SPEED_1000MBPS 1000
15322 #define ICE_LINK_SPEED_2500MBPS 2500
15323 #define ICE_LINK_SPEED_5000MBPS 5000
15324 #define ICE_LINK_SPEED_10000MBPS 10000
15325 #define ICE_LINK_SPEED_20000MBPS 20000
15326 #define ICE_LINK_SPEED_25000MBPS 25000
15327 #define ICE_LINK_SPEED_40000MBPS 40000
15328 #define ICE_LINK_SPEED_50000MBPS 50000
15329 #define ICE_LINK_SPEED_100000MBPS 100000
15330 #endif /* _ICE_LAN_TX_RX_H_ */
15331