1 /* $OpenBSD: adwlib.h,v 1.17 2020/08/08 12:40:55 krw Exp $ */ 2 /* $NetBSD: adwlib.h,v 1.14 2000/07/03 18:14:18 dante Exp $ */ 3 4 /* 5 * Definitions for low level routines and data structures 6 * for the Advanced Systems Inc. SCSI controllers chips. 7 * 8 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 9 * All rights reserved. 10 * 11 * Author: Baldassare Dante Profeta <dante@mclink.it> 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * Ported from: 36 */ 37 /* 38 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 39 * 40 * Copyright (c) 1995-2000 Advanced System Products, Inc. 41 * All Rights Reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that redistributions of source 45 * code retain the above copyright notice and this comment without 46 * modification. 47 */ 48 49 #ifndef _ADVANSYS_WIDE_LIBRARY_H_ 50 #define _ADVANSYS_WIDE_LIBRARY_H_ 51 52 53 /* 54 * --- Adw Library Constants and Macros 55 */ 56 57 #define ADW_LIB_VERSION_MAJOR 5 58 #define ADW_LIB_VERSION_MINOR 8 59 60 61 /* If the result wraps when calculating tenths, return 0. */ 62 #define ADW_TENTHS(num, den) \ 63 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 64 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 65 66 67 /* 68 * Define Adw Reset Hold Time grater than 25 uSec. 69 * See AdwResetSCSIBus() for more info. 70 */ 71 #define ADW_SCSI_RESET_HOLD_TIME_US 60 72 73 /* 74 * Define Adw EEPROM constants. 75 */ 76 77 #define ADW_EEP_DVC_CFG_BEGIN (0x00) 78 #define ADW_EEP_DVC_CFG_END (0x15) 79 #define ADW_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 80 #define ADW_EEP_MAX_WORD_ADDR (0x1E) 81 82 #define ADW_EEP_DELAY_MS 100 83 84 /* 85 * EEPROM bits reference by the RISC after initialization. 86 */ 87 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 88 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 89 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 90 91 /* 92 * EEPROM configuration format 93 * 94 * Field naming convention: 95 * 96 * *_enable indicates the field enables or disables the feature. The 97 * value is never reset. 98 * 99 * *_able indicates both whether a feature should be enabled or disabled 100 * and whether a device isi capable of the feature. At initialization 101 * this field may be set, but later if a device is found to be incapable 102 * of the feature, the field is cleared. 103 * 104 * Default values are maintained in the structure Default_EEPROM_Config. 105 */ 106 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 107 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 108 /* 109 * For the ASC3550 Bit 13 is Termination Polarity control bit. 110 * For later ICs Bit 13 controls whether the CIS (Card Information 111 * Service Section) is loaded from EEPROM. 112 */ 113 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 114 #define ADW_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 115 116 /* 117 * ASC38C1600 Bit 11 118 * 119 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 120 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 121 * Function 0 will specify INT B. 122 * 123 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 124 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 125 * Function 1 will specify INT A. 126 */ 127 #define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 128 129 typedef struct adw_eeprom 130 { 131 /* Word Offset, Description */ 132 133 u_int16_t cfg_lsw; /* 00 power up initialization */ 134 /* bit 13 set - Term Polarity Control */ 135 /* bit 14 set - BIOS Enable */ 136 /* bit 15 set - Big Endian Mode */ 137 u_int16_t cfg_msw; /* 01 unused */ 138 u_int16_t disc_enable; /* 02 disconnect enable */ 139 u_int16_t wdtr_able; /* 03 Wide DTR able */ 140 union { 141 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 142 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 143 } sdtr1; 144 u_int16_t start_motor; /* 05 send start up motor */ 145 u_int16_t tagqng_able; /* 06 tag queuing able */ 146 u_int16_t bios_scan; /* 07 BIOS device control */ 147 u_int16_t scam_tolerant; /* 08 no scam */ 148 149 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 150 u_int8_t bios_boot_delay; /* power up wait */ 151 152 u_int8_t scsi_reset_delay; /* 10 reset delay */ 153 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 154 /* high nibble is lun */ 155 /* low nibble is scsi id */ 156 157 u_int8_t termination_se; /* 11 0 - automatic */ 158 /* 1 - low off / high off */ 159 /* 2 - low off / high on */ 160 /* 3 - low on / high on */ 161 /* There is no low on / high off */ 162 163 u_int8_t termination_lvd; /* 11 0 - automatic */ 164 /* 1 - low off / high off */ 165 /* 2 - low off / high on */ 166 /* 3 - low on / high on */ 167 /* There is no low on / high off */ 168 169 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 170 /* bit 0 BIOS don't act as initiator. */ 171 /* bit 1 BIOS > 1 GB support */ 172 /* bit 2 BIOS > 2 Disk Support */ 173 /* bit 3 BIOS don't support removables */ 174 /* bit 4 BIOS support bootable CD */ 175 /* bit 5 BIOS scan enabled */ 176 /* bit 6 BIOS support multiple LUNs */ 177 /* bit 7 BIOS display of message */ 178 /* bit 8 SCAM disabled */ 179 /* bit 9 Reset SCSI bus during init. */ 180 /* bit 10 */ 181 /* bit 11 No verbose initialization. */ 182 /* bit 12 SCSI parity enabled */ 183 /* bit 13 */ 184 /* bit 14 */ 185 /* bit 15 */ 186 union { 187 u_int16_t ultra_able; /* 13 ULTRA speed able */ 188 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 189 } sdtr2; 190 union { 191 u_int16_t reserved2; /* 14 reserved */ 192 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 193 } sdtr3; 194 u_int8_t max_host_qng; /* 15 maximum host queuing */ 195 u_int8_t max_dvc_qng; /* maximum per device queuing */ 196 u_int16_t dvc_cntl; /* 16 control bit for driver */ 197 union { 198 u_int16_t bug_fix; /* 17 control bit for bug fix */ 199 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 200 } sdtr4; 201 u_int16_t serial_number[3]; /* 18 - 20 Board serial number */ 202 u_int16_t check_sum; /* 21 EEP check sum */ 203 u_int8_t oem_name[16]; /* 22 OEM name */ 204 u_int16_t dvc_err_code; /* 30 last device driver error code */ 205 u_int16_t adw_err_code; /* 31 last uc and Adw Lib error code */ 206 u_int16_t adw_err_addr; /* 32 last uc error address */ 207 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 208 u_int16_t saved_adw_err_code; /* 34 saved last uc and Adw Lib error code */ 209 u_int16_t saved_adw_err_addr; /* 35 saved last uc error address */ 210 u_int16_t reserved1[20]; /* 36 - 55 reserved */ 211 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 212 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 213 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 214 u_int16_t subsysid; /* 59 SubSystem ID */ 215 u_int16_t reserved2[4]; /* 60 - 63 reserved */ 216 } ADW_EEPROM; 217 218 219 /* 220 * EEPROM Commands 221 */ 222 #define ADW_EEP_CMD_READ 0x80 223 #define ADW_EEP_CMD_WRITE 0x40 224 #define ADW_EEP_CMD_WRITE_ABLE 0x30 225 #define ADW_EEP_CMD_WRITE_DISABLE 0x00 226 227 #define ADW_EEP_CMD_DONE 0x0200 228 #define ADW_EEP_CMD_DONE_ERR 0x0001 229 230 /* cfg_word */ 231 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000 232 233 /* bios_ctrl */ 234 #define BIOS_CTRL_BIOS 0x0001 235 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 236 #define BIOS_CTRL_GT_2_DISK 0x0004 237 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 238 #define BIOS_CTRL_BOOTABLE_CD 0x0010 239 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 240 #define BIOS_CTRL_DISPLAY_MSG 0x0080 241 #define BIOS_CTRL_NO_SCAM 0x0100 242 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 243 #define BIOS_CTRL_INIT_VERBOSE 0x0800 244 #define BIOS_CTRL_SCSI_PARITY 0x1000 245 #define BIOS_CTRL_AIPP_DIS 0x2000 246 247 #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 248 #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 249 250 #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 251 #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 252 253 #define ADW_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */ 254 #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ 255 #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ 256 257 /* 258 * Byte I/O register address from base of 'iop_base'. 259 */ 260 #define IOPB_INTR_STATUS_REG 0x00 261 #define IOPB_CHIP_ID_1 0x01 262 #define IOPB_INTR_ENABLES 0x02 263 #define IOPB_CHIP_TYPE_REV 0x03 264 #define IOPB_RES_ADDR_4 0x04 265 #define IOPB_RES_ADDR_5 0x05 266 #define IOPB_RAM_DATA 0x06 267 #define IOPB_RES_ADDR_7 0x07 268 #define IOPB_FLAG_REG 0x08 269 #define IOPB_RES_ADDR_9 0x09 270 #define IOPB_RISC_CSR 0x0A 271 #define IOPB_RES_ADDR_B 0x0B 272 #define IOPB_RES_ADDR_C 0x0C 273 #define IOPB_RES_ADDR_D 0x0D 274 #define IOPB_SOFT_OVER_WR 0x0E 275 #define IOPB_RES_ADDR_F 0x0F 276 #define IOPB_MEM_CFG 0x10 277 #define IOPB_RES_ADDR_11 0x11 278 #define IOPB_GPIO_DATA 0x12 279 #define IOPB_RES_ADDR_13 0x13 280 #define IOPB_FLASH_PAGE 0x14 281 #define IOPB_RES_ADDR_15 0x15 282 #define IOPB_GPIO_CNTL 0x16 283 #define IOPB_RES_ADDR_17 0x17 284 #define IOPB_FLASH_DATA 0x18 285 #define IOPB_RES_ADDR_19 0x19 286 #define IOPB_RES_ADDR_1A 0x1A 287 #define IOPB_RES_ADDR_1B 0x1B 288 #define IOPB_RES_ADDR_1C 0x1C 289 #define IOPB_RES_ADDR_1D 0x1D 290 #define IOPB_RES_ADDR_1E 0x1E 291 #define IOPB_RES_ADDR_1F 0x1F 292 #define IOPB_DMA_CFG0 0x20 293 #define IOPB_DMA_CFG1 0x21 294 #define IOPB_TICKLE 0x22 295 #define IOPB_DMA_REG_WR 0x23 296 #define IOPB_SDMA_STATUS 0x24 297 #define IOPB_SCSI_BYTE_CNT 0x25 298 #define IOPB_HOST_BYTE_CNT 0x26 299 #define IOPB_BYTE_LEFT_TO_XFER 0x27 300 #define IOPB_BYTE_TO_XFER_0 0x28 301 #define IOPB_BYTE_TO_XFER_1 0x29 302 #define IOPB_BYTE_TO_XFER_2 0x2A 303 #define IOPB_BYTE_TO_XFER_3 0x2B 304 #define IOPB_ACC_GRP 0x2C 305 #define IOPB_RES_ADDR_2D 0x2D 306 #define IOPB_DEV_ID 0x2E 307 #define IOPB_RES_ADDR_2F 0x2F 308 #define IOPB_SCSI_DATA 0x30 309 #define IOPB_RES_ADDR_31 0x31 310 #define IOPB_RES_ADDR_32 0x32 311 #define IOPB_SCSI_DATA_HSHK 0x33 312 #define IOPB_SCSI_CTRL 0x34 313 #define IOPB_RES_ADDR_35 0x35 314 #define IOPB_RES_ADDR_36 0x36 315 #define IOPB_RES_ADDR_37 0x37 316 #define IOPB_RAM_BIST 0x38 317 #define IOPB_PLL_TEST 0x39 318 #define IOPB_PCI_INT_CFG 0x3A 319 #define IOPB_RES_ADDR_3B 0x3B 320 #define IOPB_RFIFO_CNT 0x3C 321 #define IOPB_RES_ADDR_3D 0x3D 322 #define IOPB_RES_ADDR_3E 0x3E 323 #define IOPB_RES_ADDR_3F 0x3F 324 325 /* 326 * Word I/O register address from base of 'iop_base'. 327 */ 328 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 329 #define IOPW_CTRL_REG 0x02 /* CC */ 330 #define IOPW_RAM_ADDR 0x04 /* LA */ 331 #define IOPW_RAM_DATA 0x06 /* LD */ 332 #define IOPW_RES_ADDR_08 0x08 333 #define IOPW_RISC_CSR 0x0A /* CSR */ 334 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 335 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 336 #define IOPW_RES_ADDR_10 0x10 337 #define IOPW_SEL_MASK 0x12 /* SM */ 338 #define IOPW_RES_ADDR_14 0x14 339 #define IOPW_FLASH_ADDR 0x16 /* FA */ 340 #define IOPW_RES_ADDR_18 0x18 341 #define IOPW_EE_CMD 0x1A /* EC */ 342 #define IOPW_EE_DATA 0x1C /* ED */ 343 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 344 #define IOPW_RES_ADDR_20 0x20 345 #define IOPW_Q_BASE 0x22 /* QB */ 346 #define IOPW_QP 0x24 /* QP */ 347 #define IOPW_IX 0x26 /* IX */ 348 #define IOPW_SP 0x28 /* SP */ 349 #define IOPW_PC 0x2A /* PC */ 350 #define IOPW_RES_ADDR_2C 0x2C 351 #define IOPW_RES_ADDR_2E 0x2E 352 #define IOPW_SCSI_DATA 0x30 /* SD */ 353 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 354 #define IOPW_SCSI_CTRL 0x34 /* SC */ 355 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 356 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 357 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 358 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 359 #define IOPW_RES_ADDR_3C 0x3C 360 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 361 362 /* 363 * Doubleword I/O register address from base of 'iop_base'. 364 */ 365 #define IOPDW_RES_ADDR_0 0x00 366 #define IOPDW_RAM_DATA 0x04 367 #define IOPDW_RES_ADDR_8 0x08 368 #define IOPDW_RES_ADDR_C 0x0C 369 #define IOPDW_RES_ADDR_10 0x10 370 #define IOPDW_COMMA 0x14 371 #define IOPDW_COMMB 0x18 372 #define IOPDW_RES_ADDR_1C 0x1C 373 #define IOPDW_SDMA_ADDR0 0x20 374 #define IOPDW_SDMA_ADDR1 0x24 375 #define IOPDW_SDMA_COUNT 0x28 376 #define IOPDW_SDMA_ERROR 0x2C 377 #define IOPDW_RDMA_ADDR0 0x30 378 #define IOPDW_RDMA_ADDR1 0x34 379 #define IOPDW_RDMA_COUNT 0x38 380 #define IOPDW_RDMA_ERROR 0x3C 381 382 #define ADW_CHIP_ID_BYTE 0x25 383 #define ADW_CHIP_ID_WORD 0x04C1 384 385 #define ADW_SC_SCSI_BUS_RESET 0x2000 386 387 #define ADW_INTR_ENABLE_HOST_INTR 0x01 388 #define ADW_INTR_ENABLE_SEL_INTR 0x02 389 #define ADW_INTR_ENABLE_DPR_INTR 0x04 390 #define ADW_INTR_ENABLE_RTA_INTR 0x08 391 #define ADW_INTR_ENABLE_RMA_INTR 0x10 392 #define ADW_INTR_ENABLE_RST_INTR 0x20 393 #define ADW_INTR_ENABLE_DPE_INTR 0x40 394 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 395 396 #define ADW_INTR_STATUS_INTRA 0x01 397 #define ADW_INTR_STATUS_INTRB 0x02 398 #define ADW_INTR_STATUS_INTRC 0x04 399 400 #define ADW_RISC_CSR_STOP (0x0000) 401 #define ADW_RISC_TEST_COND (0x2000) 402 #define ADW_RISC_CSR_RUN (0x4000) 403 #define ADW_RISC_CSR_SINGLE_STEP (0x8000) 404 405 #define ADW_CTRL_REG_HOST_INTR 0x0100 406 #define ADW_CTRL_REG_SEL_INTR 0x0200 407 #define ADW_CTRL_REG_DPR_INTR 0x0400 408 #define ADW_CTRL_REG_RTA_INTR 0x0800 409 #define ADW_CTRL_REG_RMA_INTR 0x1000 410 #define ADW_CTRL_REG_RES_BIT14 0x2000 411 #define ADW_CTRL_REG_DPE_INTR 0x4000 412 #define ADW_CTRL_REG_POWER_DONE 0x8000 413 #define ADW_CTRL_REG_ANY_INTR 0xFF00 414 415 #define ADW_CTRL_REG_CMD_RESET 0x00C6 416 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 417 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 418 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 419 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 420 421 #define ADW_TICKLE_NOP 0x00 422 #define ADW_TICKLE_A 0x01 423 #define ADW_TICKLE_B 0x02 424 #define ADW_TICKLE_C 0x03 425 426 #define ADW_SCSI_CTRL_RSTOUT 0x2000 427 428 #define ADW_IS_INT_PENDING(iot, ioh) \ 429 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 430 431 /* 432 * SCSI_CFG0 Register bit definitions 433 */ 434 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 435 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 436 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 437 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 438 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 439 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 440 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 441 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 442 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 443 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 444 #define ADW_OUR_ID 0x000F /* SCSI ID */ 445 446 /* 447 * SCSI_CFG1 Register bit definitions 448 */ 449 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 450 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 451 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 452 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 453 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 454 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 455 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 456 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 457 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 458 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 459 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 460 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 461 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 462 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 463 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 464 465 /* 466 * Addendum for ASC-38C0800 Chip 467 * 468 * The ASC-38C1600 Chip uses the same definitions except that the 469 * bus mode override bits [12:10] have been moved to byte register 470 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 471 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 472 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 473 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 474 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 475 */ 476 #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 477 #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 478 #define ADW_HVD 0x1000 /* HVD Device Detect */ 479 #define ADW_LVD 0x0800 /* LVD Device Detect */ 480 #define ADW_SE 0x0400 /* SE Device Detect */ 481 #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */ 482 #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 483 #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 484 #define ADW_TERM_SE 0x0030 /* SE Termination Bits */ 485 #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 486 #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 487 #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 488 #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 489 #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 490 #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */ 491 #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 492 #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 493 494 495 #define CABLE_ILLEGAL_A 0x7 496 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 497 498 #define CABLE_ILLEGAL_B 0xB 499 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 500 501 /* 502 The following table details the SCSI_CFG1 Termination Polarity, 503 Termination Control and Cable Detect bits. 504 505 Cable Detect | Termination 506 Bit 3 2 1 0 | 5 4 | Notes 507 _____________|________|____________________ 508 1 1 1 0 | on on | Internal wide only 509 1 1 0 1 | on on | Internal narrow only 510 1 0 1 1 | on on | External narrow only 511 0 x 1 1 | on on | External wide only 512 1 1 0 0 | on off| Internal wide and internal narrow 513 1 0 1 0 | on off| Internal wide and external narrow 514 0 x 1 0 | off off| Internal wide and external wide 515 1 0 0 1 | on off| Internal narrow and external narrow 516 0 x 0 1 | on off| Internal narrow and external wide 517 1 1 1 1 | on on | No devices are attached 518 x 0 0 0 | on on | Illegal (all 3 connectors are used) 519 0 x 0 0 | on on | Illegal (all 3 connectors are used) 520 521 x means don't-care (either '0' or '1') 522 523 If term_pol (bit 13) is '0' (active-low terminator enable), then: 524 'on' is '0' and 'off' is '1'. 525 526 If term_pol bit is '1' (meaning active-hi terminator enable), then: 527 'on' is '1' and 'off' is '0'. 528 */ 529 530 /* 531 * MEM_CFG Register bit definitions 532 */ 533 #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 534 #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 535 #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */ 536 #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */ 537 #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */ 538 #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */ 539 #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */ 540 #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */ 541 #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */ 542 543 /* 544 * DMA_CFG0 Register bit definitions 545 * 546 * This register is only accessible to the host. 547 */ 548 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 549 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 550 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 551 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 552 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 553 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 554 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 555 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 556 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 557 #define START_CTL 0x0C /* DMA start conditions */ 558 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 559 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 560 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 561 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 562 #define READ_CMD 0x03 /* Memory Read Method */ 563 #define READ_CMD_MR 0x00 /* Memory Read */ 564 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 565 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 566 567 /* 568 * ASC-38C0800 RAM BIST Register bit definitions 569 */ 570 #define RAM_TEST_MODE 0x80 571 #define PRE_TEST_MODE 0x40 572 #define NORMAL_MODE 0x00 573 #define RAM_TEST_DONE 0x10 574 #define RAM_TEST_STATUS 0x0F 575 #define RAM_TEST_HOST_ERROR 0x08 576 #define RAM_TEST_INTRAM_ERROR 0x04 577 #define RAM_TEST_RISC_ERROR 0x02 578 #define RAM_TEST_SCSI_ERROR 0x01 579 #define RAM_TEST_SUCCESS 0x00 580 #define PRE_TEST_VALUE 0x05 581 #define NORMAL_VALUE 0x00 582 583 /* 584 * ASC38C1600 Definitions 585 * 586 * IOPB_PCI_INT_CFG Bit Field Definitions 587 */ 588 589 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 590 591 /* 592 * Bit 1 can be set to change the interrupt for the Function to operate in 593 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 594 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 595 * mode, otherwise the operating mode is undefined. 596 */ 597 #define TOTEMPOLE 0x02 598 599 /* 600 * Bit 0 can be used to change the Int Pin for the Function. The value is 601 * 0 by default for both Functions with Function 0 using INT A and Function 602 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 603 * INT A is used. 604 * 605 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 606 * value specified in the PCI Configuration Space. 607 */ 608 #define INTAB 0x01 609 610 611 #define ADW_MAX_TID 15 /* max. target identifier */ 612 #define ADW_MAX_LUN 7 /* max. logical unit number */ 613 614 615 /* 616 * Adw Library Status Definitions 617 */ 618 #define ADW_TRUE 1 619 #define ADW_FALSE 0 620 #define ADW_NOERROR 1 621 #define ADW_SUCCESS 1 622 #define ADW_BUSY 0 623 #define ADW_ERROR (-1) 624 625 626 /* 627 * Warning code values for AdwInitFrom*EEP() functions 628 */ 629 #define ADW_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 630 #define ADW_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 631 #define ADW_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 632 #define ADW_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 633 #define ADW_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 634 635 /* 636 * Error code values for AdwInitAsc*Driver() functions 637 */ 638 #define ADW_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 639 #define ADW_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 640 #define ADW_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ 641 #define ADW_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 642 #define ADW_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 643 #define ADW_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 644 #define ADW_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ 645 #define ADW_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 646 #define ADW_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 647 #define ADW_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 648 #define ADW_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 649 #define ADW_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ 650 #define ADW_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ 651 #define ADW_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ 652 653 /* 654 * BIOS LRAM variable absolute offsets. 655 */ 656 #define BIOS_CODESEG 0x54 657 #define BIOS_CODELEN 0x56 658 #define BIOS_SIGNATURE 0x58 659 #define BIOS_VERSION 0x5A 660 661 /* 662 * Chip Type flag values 663 */ 664 #define ADW_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 665 #define ADW_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 666 #define ADW_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 667 668 /* 669 * Adapter temporary configuration structure 670 * 671 * This structure can be discarded after initialization. Don't add 672 * fields here needed after initialization. 673 * 674 * Field naming convention: 675 * 676 * *_enable indicates the field enables or disables a feature. The 677 * value of the field is never reset. 678 */ 679 typedef struct adw_dvc_cfg { 680 u_int16_t disc_enable; /* enable disconnection */ 681 u_int8_t chip_version; /* chip version */ 682 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 */ 683 u_int16_t pci_device_id; /* PCI device code number */ 684 u_int16_t lib_version; /* Adw Library version number */ 685 u_int16_t control_flag; /* Microcode Control Flag */ 686 u_int16_t mcode_date; /* Microcode date */ 687 u_int16_t mcode_version; /* Microcode version */ 688 u_int16_t pci_slot_info; /* high byte device/function number 689 bits 7-3 device num., 690 bits 2-0 function num. 691 low byte bus num. */ 692 u_int16_t serial1; /* EEPROM serial number word 1 */ 693 u_int16_t serial2; /* EEPROM serial number word 2 */ 694 u_int16_t serial3; /* EEPROM serial number word 3 */ 695 } ADW_DVC_CFG; 696 697 698 #define NO_OF_SG_PER_BLOCK 15 699 700 typedef struct adw_sg_block { 701 u_int8_t reserved1; 702 u_int8_t reserved2; 703 u_int8_t reserved3; 704 u_int8_t sg_cnt; /* Valid entries in block. */ 705 u_int32_t sg_ptr; /* links to next sg block */ 706 struct { 707 u_int32_t sg_addr; /* SG element address */ 708 u_int32_t sg_count; /* SG element count */ 709 } sg_list[NO_OF_SG_PER_BLOCK]; 710 } ADW_SG_BLOCK; 711 712 713 /* 714 * Adapter operation variable structure. 715 * 716 * One structure is required per host adapter. 717 * 718 * Field naming convention: 719 * 720 * *_able indicates both whether a feature should be enabled or disabled 721 * and whether a device is capable of the feature. At initialization 722 * this field may be set, but later if a device is found to be incapable 723 * of the feature, the field is cleared. 724 */ 725 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 726 #define CCB_HASH_SHIFT 9 727 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 728 729 typedef int (* ADW_CALLBACK) (int); 730 731 typedef struct adw_softc { 732 733 struct device sc_dev; 734 735 bus_space_tag_t sc_iot; 736 bus_space_handle_t sc_ioh; 737 bus_dma_tag_t sc_dmat; 738 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 739 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */ 740 void *sc_ih; 741 742 struct adw_control *sc_control; /* control structures */ 743 744 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; 745 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 746 TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb; 747 struct mutex sc_ccb_mtx; 748 struct scsi_iopool sc_iopool; 749 750 int sc_freeze_dev[ADW_MAX_TID+1]; 751 752 ADW_CALLBACK isr_callback; /* pointer to function, called in AdwISR() */ 753 ADW_CALLBACK async_callback; /* pointer to function, called in AdwISR() */ 754 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 755 u_int16_t wdtr_able; /* try WDTR for a device */ 756 u_int16_t sdtr_able; /* try SDTR for a device */ 757 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 758 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 759 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 760 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 761 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 762 u_int16_t tagqng_able; /* try tagged queuing with a device */ 763 u_int16_t ppr_able; /* PPR message capable per TID bitmask. */ 764 u_int16_t start_motor; /* start motor command allowed */ 765 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 766 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 767 u_int8_t chip_no; /* should be assigned by caller */ 768 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 769 u_int8_t irq_no; /* IRQ number */ 770 u_int8_t chip_type; /* chip SCSI target ID */ 771 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 772 u_int32_t drv_ptr; /* driver pointer to private structure */ 773 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 774 u_int8_t bist_err_code; 775 u_int16_t carr_pending_cnt; /* Count of pending carriers. */ 776 struct adw_carrier *carr_freelist; /* Carrier free list. */ 777 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */ 778 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */ 779 /* 780 * Note: The following fields will not be used after initialization. The 781 * driver may discard the buffer after initialization is done. 782 */ 783 ADW_DVC_CFG cfg; /* temporary configuration structure */ 784 } ADW_SOFTC; 785 786 787 /* 788 * ADW_SCSI_REQ_Q - microcode request structure 789 * 790 * All fields in this structure up to byte 60 are used by the microcode. 791 * The microcode makes assumptions about the size and ordering of fields 792 * in this structure. Do not change the structure definition here without 793 * coordinating the change with the microcode. 794 */ 795 typedef struct adw_scsi_req_q { 796 u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */ 797 u_int8_t target_cmd; 798 u_int8_t target_id; /* Device target identifier. */ 799 u_int8_t target_lun; /* Device target logical unit number. */ 800 u_int32_t data_addr; /* Data buffer physical address. */ 801 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 802 u_int32_t sense_addr; /* Sense buffer physical address. */ 803 u_int32_t carr_ba; /* Carrier p-address */ 804 u_int8_t mflag; /* Adw Library flag field. */ 805 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ 806 u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 807 u_int8_t scsi_cntl; 808 u_int8_t done_status; /* Completion status. (see below) */ 809 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 810 u_int8_t host_status; /* ,uCode host status. (see below) */ 811 u_int8_t sg_working_ix; /* ,uCode working SG variable. */ 812 u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */ 813 u_int32_t sg_real_addr; /* SG list physical address. */ 814 u_int32_t scsiq_rptr; /* Internal pointer to ADW_SCSI_REQ_Q */ 815 u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */ 816 u_int32_t ccb_ptr; /* CCB Physical Address */ 817 u_int32_t carr_va; /* Carrier v-address (unused) */ 818 /* 819 * End of microcode structure - 60 bytes. The rest of the structure 820 * is used by the Adw Library and ignored by the microcode. 821 */ 822 struct scsi_sense_data *vsense_addr; /* Sense buffer virtual address. */ 823 u_char *vdata_addr; /* Data buffer virtual address. */ 824 } ADW_SCSI_REQ_Q; 825 826 /* 827 * ADW_SCSI_REQ_Q 'done_status' return values. 828 */ 829 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 830 #define QD_NO_ERROR 0x01 831 #define QD_ABORTED_BY_HOST 0x02 832 #define QD_WITH_ERROR 0x04 833 834 /* 835 * ADW_SCSI_REQ_Q 'host_status' return values. 836 */ 837 #define QHSTA_NO_ERROR 0x00 838 #define QHSTA_M_SEL_TIMEOUT 0x11 839 #define QHSTA_M_DATA_OVER_RUN 0x12 840 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 841 #define QHSTA_M_QUEUE_ABORTED 0x15 842 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 843 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 844 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 845 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 846 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 847 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 848 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 849 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 850 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 851 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 852 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 853 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 854 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 855 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 856 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 857 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 858 #define QHSTA_M_WTM_TIMEOUT 0x41 859 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 860 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 861 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 862 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 863 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 864 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 865 866 /* 867 * Microcode idle loop commands 868 */ 869 #define IDLE_CMD_COMPLETED 0 870 #define IDLE_CMD_STOP_CHIP 0x0001 871 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 872 #define IDLE_CMD_SEND_INT 0x0004 873 #define IDLE_CMD_ABORT 0x0008 874 #define IDLE_CMD_DEVICE_RESET 0x0010 875 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 876 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 877 #define IDLE_CMD_SCSIREQ 0x0080 878 879 #define IDLE_CMD_STATUS_SUCCESS 0x0001 880 #define IDLE_CMD_STATUS_FAILURE 0x0002 881 882 /* 883 * AdwSendIdleCmd() flag definitions. 884 */ 885 #define ADW_NOWAIT 0x01 886 887 /* 888 * Wait loop time out values. 889 */ 890 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */ 891 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 892 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 893 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */ 894 #define SCSI_MAX_RETRY 10 /* retry count */ 895 896 #define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 897 #define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 898 #define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 899 900 #define ADW_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 901 902 903 /* Read byte from a register. */ 904 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 905 bus_space_read_1((iot), (ioh), (reg_off)) 906 907 /* Write byte to a register. */ 908 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 909 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 910 911 /* Read word (2 bytes) from a register. */ 912 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 913 bus_space_read_2((iot), (ioh), (reg_off)) 914 915 /* Write word (2 bytes) to a register. */ 916 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 917 bus_space_write_2((iot), (ioh), (reg_off), (word)) 918 919 /* Write double word (4 bytes) to a register. */ 920 #define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \ 921 bus_space_write_4((iot), (ioh), (reg_off), (dword)) 922 923 /* Read byte from LRAM. */ 924 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 925 do { \ 926 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 927 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 928 } while (0) 929 930 /* Write byte to LRAM. */ 931 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 932 do { \ 933 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 934 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 935 } while (0) 936 937 /* Read word (2 bytes) from LRAM. */ 938 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 939 do { \ 940 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 941 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 942 } while (0) 943 944 /* Write word (2 bytes) to LRAM. */ 945 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 946 do { \ 947 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 948 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 949 } while (0) 950 951 /* Write double word (4 bytes) to LRAM */ 952 /* Because of unspecified C language ordering don't use auto-increment. */ 953 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 954 do { \ 955 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 956 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 957 (u_int16_t) ((dword) & 0xFFFF)); \ 958 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 959 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 960 (u_int16_t) ((dword >> 16) & 0xFFFF)); \ 961 } while (0) 962 963 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 964 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 965 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 966 967 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 968 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 969 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 970 971 /* 972 * Define macro to check for Condor signature. 973 * 974 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 975 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 976 */ 977 #define ADW_FIND_SIGNATURE(iot, ioh) \ 978 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 979 ADW_CHIP_ID_BYTE) && \ 980 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 981 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 982 983 /* 984 * Define macro to Return the version number of the chip at 'iop_base'. 985 * 986 * The second parameter 'bus_type' is currently unused. 987 */ 988 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 989 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 990 991 /* 992 * Abort a CCB in the chip's RISC Memory. The 'ccb_ptr' argument must 993 * match the ADW_SCSI_REQ_Q 'ccb_ptr' field. 994 * 995 * If the request has not yet been sent to the device it will simply be 996 * aborted from RISC memory. If the request is disconnected it will be 997 * aborted on reselection by sending an Abort Message to the target ID. 998 * 999 * Return value: 1000 * ADW_TRUE(1) - ccb was successfully aborted. 1001 * ADW_FALSE(0) - ccb was not found on the active queue list. 1002 */ 1003 #define ADW_ABORT_CCB(sc, ccb_ptr) \ 1004 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) 1005 1006 /* 1007 * Send a Bus Device Reset Message to the specified target ID. 1008 * 1009 * All outstanding commands will be purged if sending the 1010 * Bus Device Reset Message is successful. 1011 * 1012 * Return Value: 1013 * ADW_TRUE(1) - All requests on the target are purged. 1014 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1015 * are not purged. 1016 */ 1017 #define ADW_RESET_DEVICE(sc, target_id) \ 1018 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) 1019 1020 /* 1021 * SCSI Wide Type definition. 1022 */ 1023 #define ADW_SCSI_BIT_ID_TYPE u_int16_t 1024 1025 /* 1026 * AdwInitScsiTarget() 'cntl_flag' options. 1027 */ 1028 #define ADW_SCAN_LUN 0x01 1029 #define ADW_CAPINFO_NOLUN 0x02 1030 1031 /* 1032 * Convert target id to target id bit mask. 1033 */ 1034 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 1035 1036 /* 1037 * SCSI Inquiry structure 1038 */ 1039 1040 #define INQ_CLOCKING_ST_ONLY 0x0 1041 #define INQ_CLOCKING_DT_ONLY 0x1 1042 #define INQ_CLOCKING_ST_AND_DT 0x3 1043 1044 typedef struct { 1045 u_int8_t peri_dvc_type : 5; /* peripheral device type */ 1046 u_int8_t peri_qualifier : 3; /* peripheral qualifier */ 1047 u_int8_t dvc_type_modifier : 7; /* device type modifier (for SCSI I) */ 1048 u_int8_t rmb : 1; /* RMB - removable medium bit */ 1049 u_int8_t ansi_apr_ver : 3; /* ANSI approved version */ 1050 u_int8_t ecma_ver : 3; /* ECMA version */ 1051 u_int8_t iso_ver : 2; /* ISO version */ 1052 u_int8_t rsp_data_fmt : 4; /* response data format */ 1053 /* 0 SCSI 1 */ 1054 /* 1 CCS */ 1055 /* 2 SCSI-2 */ 1056 /* 3-F reserved */ 1057 u_int8_t res1 : 2; /* reserved */ 1058 u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */ 1059 u_int8_t aenc : 1; /* asynch. event notification (processor) */ 1060 u_int8_t add_len; /* additional length */ 1061 u_int8_t res2 : 7; /* reserved */ 1062 u_int8_t SCC : 1; 1063 u_int8_t Addr16 : 1; 1064 u_int8_t res3 : 2; /* reserved */ 1065 u_int8_t MChngr : 1; 1066 u_int8_t MultiPort: 1; 1067 u_int8_t res4 : 1; 1068 u_int8_t EncServ : 1; 1069 u_int8_t BaseQue : 1; 1070 u_int8_t StfRe : 1; /* soft reset implemented */ 1071 u_int8_t CmdQue : 1; /* command queuing */ 1072 u_int8_t res5 : 1; /* reserved */ 1073 u_int8_t Linked : 1; /* linked command for this logical unit */ 1074 u_int8_t Sync : 1; /* synchronous data transfer */ 1075 u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ 1076 u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ 1077 u_int8_t RelAdr : 1; /* relative addressing mode */ 1078 u_int8_t vendor_id[8]; /* vendor identification */ 1079 u_int8_t product_id[16]; /* product identification */ 1080 u_int8_t product_rev_level[4]; /* product revision level */ 1081 u_int8_t vendor_specific[20]; /* vendor specific */ 1082 u_int8_t IUS : 1; /* information unit supported */ 1083 u_int8_t QAS : 1; /* quick arbitrate supported */ 1084 u_int8_t Clocking : 2; /* clocking field */ 1085 u_int8_t res6 : 4; /* reserved */ 1086 u_int8_t res7; /* reserved */ 1087 u_int8_t version_descriptor[8][2]; 1088 } ADW_SCSI_INQUIRY; /* 74 bytes */ 1089 1090 /* 1091 * Adw Library functions available to drivers. 1092 */ 1093 1094 int AdwInitFromEEPROM(ADW_SOFTC *); 1095 int AdwInitDriver(ADW_SOFTC *); 1096 int AdwExeScsiQueue(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 1097 int AdwISR(ADW_SOFTC *); 1098 void AdwResetChip(bus_space_tag_t, bus_space_handle_t); 1099 int AdwSendIdleCmd(ADW_SOFTC *, u_int16_t, u_int32_t); 1100 int AdwResetSCSIBus(ADW_SOFTC *); 1101 int AdwResetCCB(ADW_SOFTC *); 1102 1103 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1104