1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxipdreg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 7.9 IPD Registers 38 */ 39 40 #ifndef _CN30XXIPDREG_H_ 41 #define _CN30XXIPDREG_H_ 42 43 #define IPD_1ST_MBUFF_SKIP 0x00014f0000000000ULL 44 #define IPD_NOT_1ST_MBUFF_SKIP 0x00014f0000000008ULL 45 #define IPD_PACKET_MBUFF_SIZE 0x00014f0000000010ULL 46 #define IPD_CTL_STATUS 0x00014f0000000018ULL 47 #define IPD_WQE_FPA_QUEUE 0x00014f0000000020ULL 48 #define IPD_PORT0_BP_PAGE_CNT 0x00014f0000000028ULL 49 #define IPD_PORT1_BP_PAGE_CNT 0x00014f0000000030ULL 50 #define IPD_PORT2_BP_PAGE_CNT 0x00014f0000000038ULL 51 #define IPD_PORT32_BP_PAGE_CNT 0x00014f0000000128ULL 52 #define IPD_SUB_PORT_BP_PAGE_CNT 0x00014f0000000148ULL 53 #define IPD_1ST_NEXT_PTR_BACK 0x00014f0000000150ULL 54 #define IPD_2ND_NEXT_PTR_BACK 0x00014f0000000158ULL 55 #define IPD_INT_ENB 0x00014f0000000160ULL 56 #define IPD_INT_SUM 0x00014f0000000168ULL 57 #define IPD_SUB_PORT_FCS 0x00014f0000000170ULL 58 #define IPD_QOS0_RED_MARKS 0x00014f0000000178ULL 59 #define IPD_QOS1_RED_MARKS 0x00014f0000000180ULL 60 #define IPD_QOS2_RED_MARKS 0x00014f0000000188ULL 61 #define IPD_QOS3_RED_MARKS 0x00014f0000000190ULL 62 #define IPD_QOS4_RED_MARKS 0x00014f0000000198ULL 63 #define IPD_QOS5_RED_MARKS 0x00014f00000001a0ULL 64 #define IPD_QOS6_RED_MARKS 0x00014f00000001a8ULL 65 #define IPD_QOS7_RED_MARKS 0x00014f00000001b0ULL 66 #define IPD_PORT_BP_COUNTERS_PAIR0 0x00014f00000001b8ULL 67 #define IPD_PORT_BP_COUNTERS_PAIR1 0x00014f00000001c0ULL 68 #define IPD_PORT_BP_COUNTERS_PAIR2 0x00014f00000001c8ULL 69 #define IPD_PORT_BP_COUNTERS_PAIR32 0x00014f00000002b8ULL 70 #define IPD_RED_PORT_ENABLE 0x00014f00000002d8ULL 71 #define IPD_RED_QUE0_PARAM 0x00014f00000002e0ULL 72 #define IPD_RED_QUE1_PARAM 0x00014f00000002e8ULL 73 #define IPD_RED_QUE2_PARAM 0x00014f00000002f0ULL 74 #define IPD_RED_QUE3_PARAM 0x00014f00000002f8ULL 75 #define IPD_RED_QUE4_PARAM 0x00014f0000000300ULL 76 #define IPD_RED_QUE5_PARAM 0x00014f0000000308ULL 77 #define IPD_RED_QUE6_PARAM 0x00014f0000000310ULL 78 #define IPD_RED_QUE7_PARAM 0x00014f0000000318ULL 79 #define IPD_PTR_COUNT 0x00014f0000000320ULL 80 #define IPD_BP_PRT_RED_END 0x00014f0000000328ULL 81 #define IPD_QUE0_FREE_PAGE_CNT 0x00014f0000000330ULL 82 #define IPD_CLK_COUNT 0x00014f0000000338ULL 83 #define IPD_PWP_PTR_FIFO_CTL 0x00014f0000000340ULL 84 #define IPD_PRC_HOLD_PTR_FIFO_CTL 0x00014f0000000348ULL 85 #define IPD_PRC_PORT_PTR_FIFO_CTL 0x00014f0000000350ULL 86 #define IPD_PKT_PTR_VALID 0x00014f0000000358ULL 87 #define IPD_WQE_PTR_VALID 0x00014f0000000360ULL 88 #define IPD_BIST_STATUS 0x00014f00000007f8ULL 89 90 #define IPD_BASE 0x00014f0000000000ULL 91 #define IPD_SIZE 0x800ULL 92 93 #define IPD_1ST_MBUFF_SKIP_OFFSET 0x0ULL 94 #define IPD_NOT_1ST_MBUFF_SKIP_OFFSET 0x8ULL 95 #define IPD_PACKET_MBUFF_SIZE_OFFSET 0x10ULL 96 #define IPD_CTL_STATUS_OFFSET 0x18ULL 97 #define IPD_WQE_FPA_QUEUE_OFFSET 0x20ULL 98 #define IPD_PORT0_BP_PAGE_CNT_OFFSET 0x28ULL 99 #define IPD_PORT1_BP_PAGE_CNT_OFFSET 0x30ULL 100 #define IPD_PORT2_BP_PAGE_CNT_OFFSET 0x38ULL 101 #define IPD_PORT32_BP_PAGE_CNT_OFFSET 0x128ULL 102 #define IPD_SUB_PORT_BP_PAGE_CNT_OFFSET 0x148ULL 103 #define IPD_1ST_NEXT_PTR_BACK_OFFSET 0x150ULL 104 #define IPD_2ND_NEXT_PTR_BACK_OFFSET 0x158ULL 105 #define IPD_INT_ENB_OFFSET 0x160ULL 106 #define IPD_INT_SUM_OFFSET 0x168ULL 107 #define IPD_SUB_PORT_FCS_OFFSET 0x170ULL 108 #define IPD_QOS0_RED_MARKS_OFFSET 0x178ULL 109 #define IPD_QOS1_RED_MARKS_OFFSET 0x180ULL 110 #define IPD_QOS2_RED_MARKS_OFFSET 0x188ULL 111 #define IPD_QOS3_RED_MARKS_OFFSET 0x190ULL 112 #define IPD_QOS4_RED_MARKS_OFFSET 0x198ULL 113 #define IPD_QOS5_RED_MARKS_OFFSET 0x1a0ULL 114 #define IPD_QOS6_RED_MARKS_OFFSET 0x1a8ULL 115 #define IPD_QOS7_RED_MARKS_OFFSET 0x1b0ULL 116 #define IPD_PORT_BP_COUNTERS_PAIR0_OFFSET 0x1b8ULL 117 #define IPD_PORT_BP_COUNTERS_PAIR1_OFFSET 0x1c0ULL 118 #define IPD_PORT_BP_COUNTERS_PAIR2_OFFSET 0x1c8ULL 119 #define IPD_PORT_BP_COUNTERS_PAIR32_OFFSET 0x2b8ULL 120 #define IPD_RED_PORT_ENABLE_OFFSET 0x2d8ULL 121 #define IPD_RED_QUE0_PARAM_OFFSET 0x2e0ULL 122 #define IPD_RED_QUE1_PARAM_OFFSET 0x2e8ULL 123 #define IPD_RED_QUE2_PARAM_OFFSET 0x2f0ULL 124 #define IPD_RED_QUE3_PARAM_OFFSET 0x2f8ULL 125 #define IPD_RED_QUE4_PARAM_OFFSET 0x300ULL 126 #define IPD_RED_QUE5_PARAM_OFFSET 0x308ULL 127 #define IPD_RED_QUE6_PARAM_OFFSET 0x310ULL 128 #define IPD_RED_QUE7_PARAM_OFFSET 0x318ULL 129 #define IPD_PTR_COUNT_OFFSET 0x320ULL 130 #define IPD_BP_PRT_RED_END_OFFSET 0x328ULL 131 #define IPD_QUE0_FREE_PAGE_CNT_OFFSET 0x330ULL 132 #define IPD_CLK_COUNT_OFFSET 0x338ULL 133 #define IPD_PWP_PTR_FIFO_CTL_OFFSET 0x340ULL 134 #define IPD_PRC_HOLD_PTR_FIFO_CTL_OFFSET 0x348ULL 135 #define IPD_PRC_PORT_PTR_FIFO_CTL_OFFSET 0x350ULL 136 #define IPD_PKT_PTR_VALID_OFFSET 0x358ULL 137 #define IPD_WQE_PTR_VALID_OFFSET 0x360ULL 138 #define IPD_BIST_STATUS_OFFSET 0x7f8ULL 139 140 /* ----- */ 141 /* 142 * Work Queue Entry Format (for input packet) 143 * 7.5 Work Queue Entry 144 * Figure 7-8. PIP/IPD Hardware Work-Queue Entry 145 */ 146 147 /* 148 * word 2 149 * Figure. 7-9 Work-Queue Entry format; Word2 Cases 150 */ 151 /* RAWFULL */ 152 #define IPD_WQE_WORD2_RAW_BUFS 0xff00000000000000ULL 153 #define IPD_WQE_WORD2_RAW_WORD 0x00ffffffffffffffULL 154 155 /* is IP */ 156 #define IPD_WQE_WORD2_IP_BUFS 0xff00000000000000ULL 157 #define IPD_WQE_WORD2_IP_IPOFF 0x00ff000000000000ULL 158 #define IPD_WQE_WORD2_IP_VV 0x0000800000000000ULL 159 #define IPD_WQE_WORD2_IP_VS 0x0000400000000000ULL 160 #define IPD_WQE_WORD2_IP_45 0x0000200000000000ULL 161 #define IPD_WQE_WORD2_IP_VC 0x0000100000000000ULL 162 #define IPD_WQE_WORD2_IP_VLANID 0x00000fff00000000ULL 163 #define IPD_WQE_WORD2_IP_31_20 0x00000000fff00000ULL 164 #define IPD_WQE_WORD2_IP_CO 0x0000000000080000ULL 165 #define IPD_WQE_WORD2_IP_TU 0x0000000000040000ULL 166 #define IPD_WQE_WORD2_IP_SE 0x0000000000020000ULL 167 #define IPD_WQE_WORD2_IP_V6 0x0000000000010000ULL 168 #define IPD_WQE_WORD2_IP_15 0x0000000000008000ULL 169 #define IPD_WQE_WORD2_IP_LE 0x0000000000004000ULL 170 #define IPD_WQE_WORD2_IP_FR 0x0000000000002000ULL 171 #define IPD_WQE_WORD2_IP_IE 0x0000000000001000ULL 172 #define IPD_WQE_WORD2_IP_B 0x0000000000000800ULL 173 #define IPD_WQE_WORD2_IP_M 0x0000000000000400ULL 174 #define IPD_WQE_WORD2_IP_NI 0x0000000000000200ULL 175 #define IPD_WQE_WORD2_IP_RE 0x0000000000000100ULL 176 #define IPD_WQE_WORD2_IP_OPCODE 0x00000000000000ffULL 177 178 /* All other */ 179 #define IPD_WQE_WORD2_OTH_BUFS 0xff00000000000000ULL 180 #define IPD_WQE_WORD2_OTH_55_48 0x00ff000000000000ULL 181 #define IPD_WQE_WORD2_OTH_VV 0x0000800000000000ULL 182 #define IPD_WQE_WORD2_OTH_VS 0x0000400000000000ULL 183 #define IPD_WQE_WORD2_OTH_45 0x0000200000000000ULL 184 #define IPD_WQE_WORD2_OTH_VC 0x0000100000000000ULL 185 #define IPD_WQE_WORD2_OTH_VLANID 0x00000fff00000000ULL 186 #define IPD_WQE_WORD2_OTH_31_14 0x00000000ffffc000ULL 187 #define IPD_WQE_WORD2_OTH_IR 0x0000000000002000ULL 188 #define IPD_WQE_WORD2_OTH_IA 0x0000000000001000ULL 189 #define IPD_WQE_WORD2_OTH_B 0x0000000000000800ULL 190 #define IPD_WQE_WORD2_OTH_M 0x0000000000000400ULL 191 #define IPD_WQE_WORD2_OTH_NI 0x0000000000000200ULL 192 #define IPD_WQE_WORD2_OTH_RE 0x0000000000000100ULL 193 #define IPD_WQE_WORD2_OTH_OPCODE 0x00000000000000ffULL 194 195 /* 196 * word 3 197 */ 198 #define IPD_WQE_WORD3_63 0x8000000000000000ULL 199 #define IPD_WQE_WORD3_BACK 0x7800000000000000ULL 200 #define IPD_WQE_WORD3_58_56 0x0700000000000000ULL 201 #define IPD_WQE_WORD3_SIZE 0x00ffff0000000000ULL 202 #define IPD_WQE_WORD3_ADDR 0x000000ffffffffffULL 203 204 /* 205 * IPD_1ST_MBUFF_SKIP 206 */ 207 #define IPD_1ST_MBUFF_SKIP_63_6 0xffffffffffffffc0ULL 208 #define IPD_1ST_MBUFF_SKIP_SZ 0x000000000000003fULL 209 210 /* 211 * IPD_NOT_1ST_MBUFF_SKIP 212 */ 213 #define IPD_NOT_1ST_MBUFF_SKIP_63_6 0xffffffffffffffc0ULL 214 #define IPD_NOT_1ST_MBUFF_SKIP_SZ 0x000000000000003fULL 215 216 /* 217 * IPD_PACKET_MBUFF_SIZE 218 */ 219 #define IPD_PACKET_MBUFF_SIZE_63_12 0xfffffffffffff000ULL 220 #define IPD_PACKET_MBUFF_SIZE_MB_SIZE 0x0000000000000fffULL 221 222 /* 223 * IPD_CTL_STATUS 224 */ 225 #define IPD_CTL_STATUS_63_10 0xfffffffffffffc00ULL 226 #define IPD_CTL_STATUS_LEN_M8 0x0000000000000200ULL 227 #define IPD_CTL_STATUS_RESET 0x0000000000000100ULL 228 #define IPD_CTL_STATUS_ADDPKT 0x0000000000000080ULL 229 #define IPD_CTL_STATUS_NADDBUF 0x0000000000000040ULL 230 #define IPD_CTL_STATUS_PKT_LEND 0x0000000000000020ULL 231 #define IPD_CTL_STATUS_WQE_LEND 0x0000000000000010ULL 232 #define IPD_CTL_STATUS_PBP_EN 0x0000000000000008ULL 233 #define IPD_CTL_STATUS_OPC_MODE 0x0000000000000006ULL 234 #define IPD_CTL_STATUS_OPC_MODE_SHIFT 1 235 #define IPD_CTL_STATUS_OPC_MODE_NONE (0ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 236 #define IPD_CTL_STATUS_OPC_MODE_ALL (1ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 237 #define IPD_CTL_STATUS_OPC_MODE_ONE (2ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 238 #define IPD_CTL_STATUS_OPC_MODE_TWO (3ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 239 #define IPD_CTL_STATUS_IPD_EN 0x0000000000000001ULL 240 241 /* 242 * IPD_WQE_FPA_QUEUE 243 */ 244 #define IPD_WQE_FPA_QUEUE_63_3 0xfffffffffffffff8ULL 245 #define IPD_WQE_FPA_QUEUE_WQE_QUE 0x0000000000000007ULL 246 247 /* 248 * IPD_PORTN_BP_PAGE_CNT 249 */ 250 #define IPD_PORTN_BP_PAGE_CNT_63_18 0xfffffffffffc0000ULL 251 #define IPD_PORTN_BP_PAGE_CNT_BP_ENB 0x0000000000020000ULL 252 #define IPD_PORTN_BP_PAGE_CNT_PAGE_CNT 0x000000000001ffffULL 253 254 /* 255 * IPD_SUB_PORT_BP_PAGE_CNT 256 */ 257 #define IPD_SUB_PORT_BP_PAGE_CNT_63_18 0xffffffff80000000ULL 258 #define IPD_SUB_PORT_BP_PAGE_CNT_PORT 0x000000007e000000ULL 259 #define IPD_SUB_PORT_BP_PAGE_CNT_PAGE_CNT 0x0000000001ffffffULL 260 261 /* 262 * IPD_1ST_NEXT_PTR_BACK 263 */ 264 #define IPD_1ST_NEXT_PTR_BACK_63_4 0xfffffffffffffff0ULL 265 #define IPD_1ST_NEXT_PTR_BACK_BACK 0x000000000000000fULL 266 267 /* 268 * IPD_2ND_NEXT_PTR_BACK 269 */ 270 #define IPD_2ND_NEXT_PTR_BACK_63_4 0xfffffffffffffff0ULL 271 #define IPD_2ND_NEXT_PTR_BACK_BACK 0x000000000000000fULL 272 273 /* 274 * IPD_INT_ENB 275 */ 276 #define IPD_INT_ENB_63_4 0xffffffffffffffe0ULL 277 #define IPD_INT_ENB_BP_SUB 0x0000000000000010ULL 278 #define IPD_INT_ENB_PRC_PAR3 0x0000000000000008ULL 279 #define IPD_INT_ENB_PRC_PAR2 0x0000000000000004ULL 280 #define IPD_INT_ENB_PRC_PAR1 0x0000000000000002ULL 281 #define IPD_INT_ENB_PRC_PAR0 0x0000000000000001ULL 282 283 /* 284 * IPD_INT_SUM 285 */ 286 #define IPD_INT_SUM_63_4 0xffffffffffffffe0ULL 287 #define IPD_INT_SUM_BP_SUB 0x0000000000000010ULL 288 #define IPD_INT_SUM_PRC_PAR3 0x0000000000000008ULL 289 #define IPD_INT_SUM_PRC_PAR2 0x0000000000000004ULL 290 #define IPD_INT_SUM_PRC_PAR1 0x0000000000000002ULL 291 #define IPD_INT_SUM_PRC_PAR0 0x0000000000000001ULL 292 293 /* 294 * IPD_SUB_PORT_FCS 295 */ 296 #define IPD_SUB_PORT_FCS_63_3 0xfffffffffffffff8ULL 297 #define IPD_SUB_PORT_FCS_PORT_BIT 0x0000000000000007ULL 298 299 /* 300 * IPD_QOSN_RED_MARKS 301 */ 302 #define IPD_QOSN_READ_MARKS_DROP 0xffffffff00000000ULL 303 #define IPD_QOSN_READ_MARKS_PASS 0x00000000ffffffffULL 304 305 /* 306 * IPD_PORT_BP_COUNTERS_PAIRN 307 */ 308 #define IPD_PORT_BP_COUNTERS_PAIRN_63_25 0xfffffffffe000000ULL 309 #define IPD_PORT_BP_COUNTERS_PAIRN_CNT_VAL 0x0000000001ffffffULL 310 311 /* 312 * IPD_RED_PORT_ENABLE 313 */ 314 #define IPD_RED_PORT_ENABLE_PRB_DLY 0xfffc000000000000ULL 315 #define IPD_RED_PORT_ENABLE_AVG_DLY 0x0003fff000000000ULL 316 #define IPD_RED_PORT_ENABLE_PRT_ENB 0x0000000fffffffffULL 317 318 /* 319 * IPD_RED_QUEN_PARAM 320 */ 321 #define IPD_RED_QUEN_PARAM_63_49 0xfffe000000000000ULL 322 #define IPD_RED_QUEN_PARAM_USE_PCNT 0x0001000000000000ULL 323 #define IPD_RED_QUEN_PARAM_NEW_CON 0x0000ff0000000000ULL 324 #define IPD_RED_QUEN_PARAM_AVG_CON 0x000000ff00000000ULL 325 #define IPD_RED_QUEN_PARAM_PRB_CON 0x00000000ffffffffULL 326 327 /* 328 * IPD_PTR_COUNT 329 */ 330 #define IPD_PTR_COUNT_63_19 0xfffffffffff80000ULL 331 #define IPD_PTR_COUNT_PKTV_CNT 0x0000000000040000ULL 332 #define IPD_PTR_COUNT_WQEV_CNT 0x0000000000020000ULL 333 #define IPD_PTR_COUNT_PFIF_CNT 0x000000000001c000ULL 334 #define IPD_PTR_COUNT_PKT_PCNT 0x0000000000003f80ULL 335 #define IPD_PTR_COUNT_WQE_PCNT 0x000000000000007fULL 336 337 /* 338 * IPD_BP_PRT_RED_END 339 */ 340 #define IPD_BP_PRT_RED_END_63_36 0xfffffff000000000ULL 341 #define IPD_BP_PRT_RED_END_PRT_ENB 0x0000000fffffffffULL 342 343 /* 344 * IPD_QUE0_FREE_PAGE_CNT 345 */ 346 #define IPD_QUE0_FREE_PAGE_CNT_63_32 0xffffffff00000000ULL 347 #define IPD_QUE0_FREE_PAGE_CNT_Q0_PCNT 0x00000000ffffffffULL 348 349 /* 350 * IPD_CLK_COUNT 351 */ 352 #define IPD_CLK_COUNT_CLK_CNT 0xffffffffffffffffULL 353 354 /* 355 * IPD_PWP_PTR_FIFO_CTL 356 */ 357 #define IPD_PWP_PTR_FIFO_CTL_63_61 0xe000000000000000ULL 358 #define IPD_PWP_PTR_FIFO_CTL_MAX_CNTS 0x1fc0000000000000ULL 359 #define IPD_PWP_PTR_FIFO_CTL_WRADDR 0x003fc00000000000ULL 360 #define IPD_PWP_PTR_FIFO_CTL_PRADDR 0x00003fc000000000ULL 361 #define IPD_PWP_PTR_FIFO_CTL_PTR 0x0000003ffffffe00ULL 362 #define IPD_PWP_PTR_FIFO_CTL_CENA 0x0000000000000100ULL 363 #define IPD_PWP_PTR_FIFO_CTL_RADDR 0x00000000000000ffULL 364 365 /* 366 * IPD_PRC_HOLD_PTR_FIFO_CTL 367 */ 368 #define IPD_PRC_HOLD_PTR_FIFO_CTL_63_39 0xffffff8000000000ULL 369 #define IPD_PRC_HOLD_PTR_FIFO_CTL_MAX_PTR 0x0000007000000000ULL 370 #define IPD_PRC_HOLD_PTR_FIFO_CTL_PRADDR 0x0000000e00000000ULL 371 #define IPD_PRC_HOLD_PTR_FIFO_CTL_PTR 0x00000001fffffff0ULL 372 #define IPD_PRC_HOLD_PTR_FIFO_CTL_CENA 0x0000000000000008ULL 373 #define IPD_PRC_HOLD_PTR_FIFO_CTL_RADDR 0x0000000000000007ULL 374 375 /* 376 * IPD_PRC_PORT_PTR_FIFO_CTL 377 */ 378 #define IPD_PRC_PORT_PTR_FIFO_CTL_63_44 0xfffff00000000000ULL 379 #define IPD_PRC_PORT_PTR_FIFO_CTL_MAX_PTR 0x00000fe000000000ULL 380 #define IPD_PRC_PORT_PTR_FIFO_CTL_PTR 0x0000001fffffff00ULL 381 #define IPD_PRC_PORT_PTR_FIFO_CTL_CENA 0x0000000000000080ULL 382 #define IPD_PRC_PORT_PTR_FIFO_CTL_RADDR 0x000000000000007fULL 383 384 /* 385 * IPD_PKT_PTR_VALID 386 */ 387 #define IPD_PKT_PTR_VALID_63_29 0xffffffffe0000000ULL 388 #define IPD_PKT_PTR_VALID_PTR 0x000000001fffffffULL 389 390 /* 391 * IPD_WQE_PTR_VALID 392 */ 393 #define IPD_WQE_PTR_VALID_63_29 0xffffffffe0000000ULL 394 #define IPD_WQE_PTR_VALID_PTR 0x000000001fffffffULL 395 396 /* 397 * IPD_BIST_STATUS 398 */ 399 #define IPD_BIST_STATUS_63_29 0xffffffffffff0000ULL 400 #define IPD_BIST_STATUS_PWQ_WQED 0x0000000000008000ULL 401 #define IPD_BIST_STATUS_PWQ_WP1 0x0000000000004000ULL 402 #define IPD_BIST_STATUS_PWQ_POW 0x0000000000002000ULL 403 #define IPD_BIST_STATUS_IPQ_PBE1 0x0000000000001000ULL 404 #define IPD_BIST_STATUS_IPQ_PBE0 0x0000000000000800ULL 405 #define IPD_BIST_STATUS_PBM3 0x0000000000000400ULL 406 #define IPD_BIST_STATUS_PBM2 0x0000000000000200ULL 407 #define IPD_BIST_STATUS_PBM1 0x0000000000000100ULL 408 #define IPD_BIST_STATUS_PBM0 0x0000000000000080ULL 409 #define IPD_BIST_STATUS_PBM_WORD 0x0000000000000040ULL 410 #define IPD_BIST_STATUS_PWQ1 0x0000000000000020ULL 411 #define IPD_BIST_STATUS_PWQ0 0x0000000000000010ULL 412 #define IPD_BIST_STATUS_PRC_OFF 0x0000000000000008ULL 413 #define IPD_BIST_STATUS_IPD_OLD 0x0000000000000004ULL 414 #define IPD_BIST_STATUS_IPD_NEW 0x0000000000000002ULL 415 #define IPD_BIST_STATUS_PWP 0x0000000000000001ULL 416 417 /* 418 * word2[Opcode] 419 */ 420 /* L3 (IP) error */ 421 #define IPD_WQE_L3_NOT_IP 1 422 #define IPD_WQE_L3_V4_CSUM_ERR 2 423 #define IPD_WQE_L3_HEADER_MALFORMED 3 424 #define IPD_WQE_L3_MELFORMED 4 425 #define IPD_WQE_L3_TTL_HOP 5 426 #define IPD_WQE_L3_IP_OPT 6 427 428 /* L4 (UDP/TCP) error */ 429 #define IPD_WQE_L4_MALFORMED 1 430 #define IPD_WQE_L4_CSUM_ERR 2 431 #define IPD_WQE_L4_UDP_LEN_ERR 3 432 #define IPD_WQE_L4_BAD_PORT 4 433 #define IPD_WQE_L4_FIN_ONLY 8 434 #define IPD_WQE_L4_NO_FLAGS 9 435 #define IPD_WQE_L4_FIN_RST 10 436 #define IPD_WQE_L4_SYN_URG 11 437 #define IPD_WQE_L4_SYN_RST 12 438 #define IPD_WQE_L4_SYN_FIN 13 439 440 #endif /* _CN30XXIPDREG_H_ */ 441