1 /* $OpenBSD: if_ipwreg.h,v 1.16 2008/08/28 15:08:38 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define IPW_NTBD 128 21 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 22 #define IPW_NDATA (IPW_NTBD / 2) 23 #define IPW_NRBD 128 24 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 25 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 26 27 #define IPW_CSR_INTR 0x0008 28 #define IPW_CSR_INTR_MASK 0x000c 29 #define IPW_CSR_INDIRECT_ADDR 0x0010 30 #define IPW_CSR_INDIRECT_DATA 0x0014 31 #define IPW_CSR_AUTOINC_ADDR 0x0018 32 #define IPW_CSR_AUTOINC_DATA 0x001c 33 #define IPW_CSR_RST 0x0020 34 #define IPW_CSR_CTL 0x0024 35 #define IPW_CSR_IO 0x0030 36 #define IPW_CSR_TX_BD_BASE 0x0200 37 #define IPW_CSR_TX_BD_SIZE 0x0204 38 #define IPW_CSR_RX_BD_BASE 0x0240 39 #define IPW_CSR_RX_STATUS_BASE 0x0244 40 #define IPW_CSR_RX_BD_SIZE 0x0248 41 #define IPW_CSR_TX_READ_INDEX 0x0280 42 #define IPW_CSR_RX_READ_INDEX 0x02a0 43 #define IPW_CSR_TABLE1_BASE 0x0380 44 #define IPW_CSR_TABLE2_BASE 0x0384 45 #define IPW_CSR_TX_WRITE_INDEX 0x0f80 46 #define IPW_CSR_RX_WRITE_INDEX 0x0fa0 47 48 /* possible flags for register IPW_CSR_INTR */ 49 #define IPW_INTR_TX_TRANSFER 0x00000001 50 #define IPW_INTR_RX_TRANSFER 0x00000002 51 #define IPW_INTR_STATUS_CHANGE 0x00000010 52 #define IPW_INTR_COMMAND_DONE 0x00010000 53 #define IPW_INTR_FW_INIT_DONE 0x01000000 54 #define IPW_INTR_FATAL_ERROR 0x40000000 55 #define IPW_INTR_PARITY_ERROR 0x80000000 56 57 #define IPW_INTR_MASK \ 58 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 59 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 60 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 61 IPW_INTR_PARITY_ERROR) 62 63 /* possible flags for register IPW_CSR_RST */ 64 #define IPW_RST_PRINCETON_RESET 0x00000001 65 #define IPW_RST_SW_RESET 0x00000080 66 #define IPW_RST_MASTER_DISABLED 0x00000100 67 #define IPW_RST_STOP_MASTER 0x00000200 68 69 /* possible flags for register IPW_CSR_CTL */ 70 #define IPW_CTL_CLOCK_READY 0x00000001 71 #define IPW_CTL_ALLOW_STANDBY 0x00000002 72 #define IPW_CTL_INIT 0x00000004 73 74 /* possible flags for register IPW_CSR_IO */ 75 #define IPW_IO_GPIO1_ENABLE 0x00000008 76 #define IPW_IO_GPIO1_MASK 0x0000000c 77 #define IPW_IO_GPIO3_MASK 0x000000c0 78 #define IPW_IO_LED_OFF 0x00002000 79 #define IPW_IO_RADIO_DISABLED 0x00010000 80 81 #define IPW_STATE_ASSOCIATED 0x0004 82 #define IPW_STATE_ASSOCIATION_LOST 0x0008 83 #define IPW_STATE_SCAN_COMPLETE 0x0020 84 #define IPW_STATE_RADIO_DISABLED 0x0100 85 #define IPW_STATE_DISABLED 0x0200 86 #define IPW_STATE_SCANNING 0x0800 87 88 /* table1 offsets */ 89 #define IPW_INFO_LOCK 480 90 #define IPW_INFO_APS_CNT 604 91 #define IPW_INFO_APS_BASE 608 92 #define IPW_INFO_CARD_DISABLED 628 93 #define IPW_INFO_CURRENT_CHANNEL 756 94 #define IPW_INFO_CURRENT_TX_RATE 768 95 96 /* table2 offsets */ 97 #define IPW_INFO_CURRENT_SSID 48 98 #define IPW_INFO_CURRENT_BSSID 112 99 100 /* supported rates */ 101 #define IPW_RATE_DS1 1 102 #define IPW_RATE_DS2 2 103 #define IPW_RATE_DS5 4 104 #define IPW_RATE_DS11 8 105 106 /* firmware binary image header */ 107 struct ipw_firmware_hdr { 108 uint32_t version; 109 uint32_t main_size; /* firmware size */ 110 uint32_t ucode_size; /* microcode size */ 111 } __packed; 112 113 /* buffer descriptor */ 114 struct ipw_bd { 115 uint32_t physaddr; 116 uint32_t len; 117 uint8_t flags; 118 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 119 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 120 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 121 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 122 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 123 uint8_t nfrag; /* number of fragments */ 124 uint8_t reserved[6]; 125 } __packed; 126 127 /* status */ 128 struct ipw_status { 129 uint32_t len; 130 uint16_t code; 131 #define IPW_STATUS_CODE_COMMAND 0 132 #define IPW_STATUS_CODE_NEWSTATE 1 133 #define IPW_STATUS_CODE_DATA_802_11 2 134 #define IPW_STATUS_CODE_DATA_802_3 3 135 #define IPW_STATUS_CODE_NOTIFICATION 4 136 uint8_t flags; 137 #define IPW_STATUS_FLAG_DECRYPTED 0x01 138 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 139 uint8_t rssi; /* received signal strength indicator */ 140 } __packed; 141 142 /* data header */ 143 struct ipw_hdr { 144 uint32_t type; 145 #define IPW_HDR_TYPE_SEND 33 146 uint32_t subtype; 147 uint8_t encrypted; 148 uint8_t encrypt; 149 uint8_t keyidx; 150 uint8_t keysz; 151 uint8_t key[IEEE80211_KEYBUF_SIZE]; 152 uint8_t reserved[10]; 153 uint8_t src_addr[IEEE80211_ADDR_LEN]; 154 uint8_t dst_addr[IEEE80211_ADDR_LEN]; 155 uint16_t fragmentsz; 156 } __packed; 157 158 /* command */ 159 struct ipw_cmd { 160 uint32_t type; 161 #define IPW_CMD_ENABLE 2 162 #define IPW_CMD_SET_CONFIGURATION 6 163 #define IPW_CMD_SET_ESSID 8 164 #define IPW_CMD_SET_MANDATORY_BSSID 9 165 #define IPW_CMD_SET_MAC_ADDRESS 11 166 #define IPW_CMD_SET_MODE 12 167 #define IPW_CMD_SET_CHANNEL 14 168 #define IPW_CMD_SET_RTS_THRESHOLD 15 169 #define IPW_CMD_SET_FRAG_THRESHOLD 16 170 #define IPW_CMD_SET_POWER_MODE 17 171 #define IPW_CMD_SET_TX_RATES 18 172 #define IPW_CMD_SET_BASIC_TX_RATES 19 173 #define IPW_CMD_SET_WEP_KEY 20 174 #define IPW_CMD_SET_WEP_KEY_INDEX 25 175 #define IPW_CMD_SET_PRIVACY_FLAGS 26 176 #define IPW_CMD_ADD_MULTICAST 27 177 #define IPW_CMD_SET_BEACON_INTERVAL 29 178 #define IPW_CMD_SET_TX_POWER_INDEX 36 179 #define IPW_CMD_BROADCAST_SCAN 43 180 #define IPW_CMD_DISABLE 44 181 #define IPW_CMD_SET_DESIRED_BSSID 45 182 #define IPW_CMD_SET_SCAN_OPTIONS 46 183 #define IPW_CMD_PREPARE_POWER_DOWN 58 184 #define IPW_CMD_DISABLE_PHY 61 185 #define IPW_CMD_SET_MSDU_TX_RATES 62 186 #define IPW_CMD_SET_SECURITY_INFORMATION 67 187 #define IPW_CMD_SET_ASSOC_REQ 69 188 uint32_t subtype; 189 uint32_t seq; 190 uint32_t len; 191 uint8_t data[400]; 192 uint32_t status; 193 uint8_t reserved[68]; 194 } __packed; 195 196 /* possible values for command IPW_CMD_SET_POWER_MODE */ 197 #define IPW_POWER_MODE_CAM 0 198 #define IPW_POWER_AUTOMATIC 6 199 200 /* possible values for command IPW_CMD_SET_MODE */ 201 #define IPW_MODE_BSS 0 202 #define IPW_MODE_IBSS 1 203 #define IPW_MODE_MONITOR 2 204 205 /* possible flags for command IPW_CMD_SET_PRIVACY_FLAGS */ 206 #define IPW_PRIVACYON 0x8 207 208 /* structure for command IPW_CMD_SET_WEP_KEY */ 209 struct ipw_wep_key { 210 uint8_t idx; 211 uint8_t len; 212 uint8_t key[13]; 213 } __packed; 214 215 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 216 struct ipw_security { 217 uint32_t ciphers; 218 #define IPW_CIPHER_NONE 0x00000001 219 #define IPW_CIPHER_WEP40 0x00000002 220 #define IPW_CIPHER_TKIP 0x00000004 221 #define IPW_CIPHER_CCMP 0x00000010 222 #define IPW_CIPHER_WEP104 0x00000020 223 uint16_t reserved1; 224 uint8_t authmode; 225 #define IPW_AUTH_OPEN 0 226 #define IPW_AUTH_SHARED 1 227 uint16_t reserved2; 228 } __packed; 229 230 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 231 struct ipw_scan_options { 232 uint32_t flags; 233 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 234 #define IPW_SCAN_MIXED_CELL 0x00000002 235 #define IPW_SCAN_PASSIVE 0x00000008 236 uint32_t channels; 237 } __packed; 238 239 /* structure for command IPW_CMD_SET_CONFIGURATION */ 240 struct ipw_configuration { 241 uint32_t flags; 242 #define IPW_CFG_PROMISCUOUS 0x00000004 243 #define IPW_CFG_PREAMBLE_AUTO 0x00000010 244 #define IPW_CFG_IBSS_AUTO_START 0x00000020 245 #define IPW_CFG_802_1X_ENABLE 0x00004000 246 #define IPW_CFG_BSS_MASK 0x00008000 247 #define IPW_CFG_IBSS_MASK 0x00010000 248 uint32_t bss_chan; 249 uint32_t ibss_chan; 250 } __packed; 251 252 /* structure for command IPW_CMD_SET_ASSOC_REQ */ 253 struct ipw_assoc_req { 254 uint16_t flags; 255 #define IPW_ASSOC_CAPINFO 0x0001 256 #define IPW_ASSOC_LINTVAL 0x0002 257 #define IPW_ASSOC_BSSID 0x0004 /* reassoc */ 258 uint16_t capinfo; 259 uint16_t lintval; 260 uint8_t bssid[IEEE80211_ADDR_LEN]; 261 uint32_t optie_len; 262 uint8_t optie[384]; 263 } __packed; 264 265 #define IPW_MEM_EEPROM_CTL 0x00300040 266 267 #define IPW_EEPROM_MAC 0x21 268 269 #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 270 271 #define IPW_EEPROM_C (1 << 0) /* Serial Clock */ 272 #define IPW_EEPROM_S (1 << 1) /* Chip Select */ 273 #define IPW_EEPROM_D (1 << 2) /* Serial data input */ 274 #define IPW_EEPROM_Q (1 << 4) /* Serial data output */ 275 276 #define IPW_EEPROM_SHIFT_D 2 277 #define IPW_EEPROM_SHIFT_Q 4 278 279 /* 280 * control and status registers access macros 281 */ 282 #define CSR_READ_1(sc, reg) \ 283 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 284 285 #define CSR_READ_2(sc, reg) \ 286 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 287 288 #define CSR_READ_4(sc, reg) \ 289 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 290 291 #define CSR_WRITE_1(sc, reg, val) \ 292 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 293 294 #define CSR_WRITE_2(sc, reg, val) \ 295 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 296 297 #define CSR_WRITE_4(sc, reg, val) \ 298 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 299 300 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 301 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 302 (buf), (len)) 303 304 /* 305 * indirect memory space access macros 306 */ 307 #define MEM_WRITE_1(sc, addr, val) do { \ 308 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 309 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 310 } while (/* CONSTCOND */0) 311 312 #define MEM_WRITE_2(sc, addr, val) do { \ 313 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 314 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 315 } while (/* CONSTCOND */0) 316 317 #define MEM_WRITE_4(sc, addr, val) do { \ 318 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 319 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 320 } while (/* CONSTCOND */0) 321 322 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 323 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 324 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 325 } while (/* CONSTCOND */0) 326 327 /* 328 * EEPROM access macro 329 */ 330 #define IPW_EEPROM_CTL(sc, val) do { \ 331 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ 332 DELAY(IPW_EEPROM_DELAY); \ 333 } while (/* CONSTCOND */0) 334 335