1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: ixgb_hw.h,v 1.4 2024/05/13 01:15:51 jsg Exp $ */ 35 36 #ifndef _IXGB_HW_H_ 37 #define _IXGB_HW_H_ 38 39 #include <dev/pci/if_ixgb_osdep.h> 40 41 /* Enums */ 42 typedef enum { 43 ixgb_mac_unknown = 0, 44 ixgb_82597, 45 ixgb_num_macs 46 } ixgb_mac_type; 47 48 /* Types of physical layer modules */ 49 typedef enum { 50 ixgb_phy_type_unknown = 0, 51 ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */ 52 ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */ 53 ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */ 54 ixgb_phy_type_txn17401, /* 1310nm, SM fiber, XENPAK transceiver */ 55 ixgb_phy_type_bcm /* SUN specific board */ 56 } ixgb_phy_type; 57 58 /* XPAK transceiver vendors, for the SR adapters */ 59 typedef enum { 60 ixgb_xpak_vendor_intel, 61 ixgb_xpak_vendor_infineon 62 } ixgb_xpak_vendor; 63 64 /* Media Types */ 65 typedef enum { 66 ixgb_media_type_unknown = 0, 67 ixgb_media_type_fiber = 1, 68 ixgb_media_type_copper = 2, 69 ixgb_num_media_types 70 } ixgb_media_type; 71 72 /* Flow Control Settings */ 73 typedef enum { 74 ixgb_fc_none = 0, 75 ixgb_fc_rx_pause = 1, 76 ixgb_fc_tx_pause = 2, 77 ixgb_fc_full = 3, 78 ixgb_fc_default = 0xFF 79 } ixgb_fc_type; 80 81 /* PCI bus types */ 82 typedef enum { 83 ixgb_bus_type_unknown = 0, 84 ixgb_bus_type_pci, 85 ixgb_bus_type_pcix 86 } ixgb_bus_type; 87 88 /* PCI bus speeds */ 89 typedef enum { 90 ixgb_bus_speed_unknown = 0, 91 ixgb_bus_speed_33, 92 ixgb_bus_speed_66, 93 ixgb_bus_speed_100, 94 ixgb_bus_speed_133, 95 ixgb_bus_speed_reserved 96 } ixgb_bus_speed; 97 98 /* PCI bus widths */ 99 typedef enum { 100 ixgb_bus_width_unknown = 0, 101 ixgb_bus_width_32, 102 ixgb_bus_width_64 103 } ixgb_bus_width; 104 105 #define IXGB_ETH_LENGTH_OF_ADDRESS 6 106 107 #define IXGB_EEPROM_SIZE 64 /* Size in words */ 108 109 #define SPEED_10000 10000 110 #define FULL_DUPLEX 2 111 112 #define MIN_NUMBER_OF_DESCRIPTORS 8 113 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B 114 * aligned */ 115 116 #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling 117 * rx/tx units */ 118 #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */ 119 #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM 120 * reset */ 121 122 #define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after 123 * the reset */ 124 /* NOTE: this is MICROSECONDS */ 125 #define MAX_RESET_ITERATIONS 8 /* number of iterations to get 126 * things right */ 127 128 /* General Registers */ 129 #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */ 130 #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */ 131 #define IXGB_STATUS 0x00010 /* Device Status Register - RO */ 132 #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */ 133 #define IXGB_MFRMS 0x00020 /* Maximum Frame Size - RW */ 134 135 /* Interrupt */ 136 #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */ 137 #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */ 138 #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */ 139 #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */ 140 141 /* Receive */ 142 #define IXGB_RCTL 0x00100 /* RX Control - RW */ 143 #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */ 144 #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */ 145 #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */ 146 #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */ 147 #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */ 148 #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */ 149 #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */ 150 #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */ 151 #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */ 152 #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Ctrl RW */ 153 #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */ 154 #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */ 155 #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */ 156 #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */ 157 #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */ 158 #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */ 159 #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8 160 161 /* Transmit */ 162 #define IXGB_TCTL 0x00600 /* TX Control - RW */ 163 #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */ 164 #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */ 165 #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */ 166 #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */ 167 #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */ 168 #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */ 169 #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */ 170 #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */ 171 #define IXGB_PAP 0x00640 /* Pause and Pace - RW */ 172 #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8 173 174 /* Physical */ 175 #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */ 176 #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */ 177 #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */ 178 #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */ 179 #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - 180 * RO */ 181 #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */ 182 #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */ 183 #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */ 184 #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */ 185 #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */ 186 #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */ 187 #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */ 188 #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */ 189 190 /* Wake-up */ 191 #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */ 192 #define IXGB_WUS 0x00810 /* Wake Up Status - RO */ 193 #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */ 194 #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */ 195 #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */ 196 197 /* Statistics */ 198 #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */ 199 #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */ 200 #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */ 201 #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */ 202 #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */ 203 #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */ 204 #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */ 205 #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */ 206 #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */ 207 #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */ 208 #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */ 209 #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */ 210 #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */ 211 #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */ 212 #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */ 213 #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */ 214 #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */ 215 #define IXGB_TORH 0x02044 /* Total Octets Received (High) */ 216 #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */ 217 #define IXGB_RUC 0x02050 /* Receive Undersize Count */ 218 #define IXGB_ROC 0x02058 /* Receive Oversize Count */ 219 #define IXGB_RLEC 0x02060 /* Receive Length Error Count */ 220 #define IXGB_CRCERRS 0x02068 /* CRC Error Count */ 221 #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */ 222 #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */ 223 #define IXGB_MPC 0x02080 /* Missed Packets Count */ 224 #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */ 225 #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */ 226 #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */ 227 #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */ 228 #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */ 229 #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */ 230 #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */ 231 #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */ 232 #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */ 233 #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */ 234 #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */ 235 #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */ 236 #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */ 237 #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */ 238 #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */ 239 #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */ 240 #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */ 241 #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */ 242 #define IXGB_DC 0x02148 /* Defer Count */ 243 #define IXGB_PLT64C 0x02150 /* Packet Transmitted was < 64 bytes Count */ 244 #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */ 245 #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */ 246 #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */ 247 #define IXGB_RFC 0x02188 /* Remote Fault Count */ 248 #define IXGB_LFC 0x02190 /* Local Fault Count */ 249 #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */ 250 #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */ 251 #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received 252 * Count */ 253 #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted 254 * Count */ 255 #define IXGB_XONRXC 0x021B8 /* XON Received Count */ 256 #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */ 257 #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */ 258 #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */ 259 #define IXGB_RJC 0x021D8 /* Receive Jabber Count */ 260 261 262 /* CTRL0 Bit Masks */ 263 #define IXGB_CTRL0_LRST 0x00000008 264 #define IXGB_CTRL0_JFE 0x00000010 265 #define IXGB_CTRL0_XLE 0x00000020 266 #define IXGB_CTRL0_MDCS 0x00000040 267 #define IXGB_CTRL0_CMDC 0x00000080 268 #define IXGB_CTRL0_SDP0 0x00040000 269 #define IXGB_CTRL0_SDP1 0x00080000 270 #define IXGB_CTRL0_SDP2 0x00100000 271 #define IXGB_CTRL0_SDP3 0x00200000 272 #define IXGB_CTRL0_SDP0_DIR 0x00400000 273 #define IXGB_CTRL0_SDP1_DIR 0x00800000 274 #define IXGB_CTRL0_SDP2_DIR 0x01000000 275 #define IXGB_CTRL0_SDP3_DIR 0x02000000 276 #define IXGB_CTRL0_RST 0x04000000 277 #define IXGB_CTRL0_RPE 0x08000000 278 #define IXGB_CTRL0_TPE 0x10000000 279 #define IXGB_CTRL0_VME 0x40000000 280 281 /* CTRL1 Bit Masks */ 282 #define IXGB_CTRL1_GPI0_EN 0x00000001 283 #define IXGB_CTRL1_GPI1_EN 0x00000002 284 #define IXGB_CTRL1_GPI2_EN 0x00000004 285 #define IXGB_CTRL1_GPI3_EN 0x00000008 286 #define IXGB_CTRL1_SDP4 0x00000010 287 #define IXGB_CTRL1_SDP5 0x00000020 288 #define IXGB_CTRL1_SDP6 0x00000040 289 #define IXGB_CTRL1_SDP7 0x00000080 290 #define IXGB_CTRL1_SDP4_DIR 0x00000100 291 #define IXGB_CTRL1_SDP5_DIR 0x00000200 292 #define IXGB_CTRL1_SDP6_DIR 0x00000400 293 #define IXGB_CTRL1_SDP7_DIR 0x00000800 294 #define IXGB_CTRL1_EE_RST 0x00002000 295 #define IXGB_CTRL1_RO_DIS 0x00020000 296 #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000 297 #define IXGB_CTRL1_PCIXHM_1_2 0x00000000 298 #define IXGB_CTRL1_PCIXHM_5_8 0x00400000 299 #define IXGB_CTRL1_PCIXHM_3_4 0x00800000 300 #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000 301 302 /* STATUS Bit Masks */ 303 #define IXGB_STATUS_LU 0x00000002 304 #define IXGB_STATUS_AIP 0x00000004 305 #define IXGB_STATUS_TXOFF 0x00000010 306 #define IXGB_STATUS_XAUIME 0x00000020 307 #define IXGB_STATUS_RES 0x00000040 308 #define IXGB_STATUS_RIS 0x00000080 309 #define IXGB_STATUS_RIE 0x00000100 310 #define IXGB_STATUS_RLF 0x00000200 311 #define IXGB_STATUS_RRF 0x00000400 312 #define IXGB_STATUS_PCI_SPD 0x00000800 313 #define IXGB_STATUS_BUS64 0x00001000 314 #define IXGB_STATUS_PCIX_MODE 0x00002000 315 #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000 316 #define IXGB_STATUS_PCIX_SPD_66 0x00000000 317 #define IXGB_STATUS_PCIX_SPD_100 0x00004000 318 #define IXGB_STATUS_PCIX_SPD_133 0x00008000 319 #define IXGB_STATUS_REV_ID_MASK 0x000F0000 320 #define IXGB_STATUS_REV_ID_SHIFT 16 321 322 /* EECD Bit Masks */ 323 #define IXGB_EECD_SK 0x00000001 324 #define IXGB_EECD_CS 0x00000002 325 #define IXGB_EECD_DI 0x00000004 326 #define IXGB_EECD_DO 0x00000008 327 #define IXGB_EECD_FWE_MASK 0x00000030 328 #define IXGB_EECD_FWE_DIS 0x00000010 329 #define IXGB_EECD_FWE_EN 0x00000020 330 331 /* MFRMS */ 332 #define IXGB_MFRMS_SHIFT 16 333 334 /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */ 335 #define IXGB_INT_TXDW 0x00000001 336 #define IXGB_INT_TXQE 0x00000002 337 #define IXGB_INT_LSC 0x00000004 338 #define IXGB_INT_RXSEQ 0x00000008 339 #define IXGB_INT_RXDMT0 0x00000010 340 #define IXGB_INT_RXO 0x00000040 341 #define IXGB_INT_RXT0 0x00000080 342 #define IXGB_INT_AUTOSCAN 0x00000200 343 #define IXGB_INT_GPI0 0x00000800 344 #define IXGB_INT_GPI1 0x00001000 345 #define IXGB_INT_GPI2 0x00002000 346 #define IXGB_INT_GPI3 0x00004000 347 348 /* RCTL Bit Masks */ 349 #define IXGB_RCTL_RXEN 0x00000002 350 #define IXGB_RCTL_SBP 0x00000004 351 #define IXGB_RCTL_UPE 0x00000008 352 #define IXGB_RCTL_MPE 0x00000010 353 #define IXGB_RCTL_RDMTS_MASK 0x00000300 354 #define IXGB_RCTL_RDMTS_1_2 0x00000000 355 #define IXGB_RCTL_RDMTS_1_4 0x00000100 356 #define IXGB_RCTL_RDMTS_1_8 0x00000200 357 #define IXGB_RCTL_MO_MASK 0x00003000 358 #define IXGB_RCTL_MO_47_36 0x00000000 359 #define IXGB_RCTL_MO_46_35 0x00001000 360 #define IXGB_RCTL_MO_45_34 0x00002000 361 #define IXGB_RCTL_MO_43_32 0x00003000 362 #define IXGB_RCTL_MO_SHIFT 12 363 #define IXGB_RCTL_BAM 0x00008000 364 #define IXGB_RCTL_BSIZE_MASK 0x00030000 365 #define IXGB_RCTL_BSIZE_2048 0x00000000 366 #define IXGB_RCTL_BSIZE_4096 0x00010000 367 #define IXGB_RCTL_BSIZE_8192 0x00020000 368 #define IXGB_RCTL_BSIZE_16384 0x00030000 369 #define IXGB_RCTL_VFE 0x00040000 370 #define IXGB_RCTL_CFIEN 0x00080000 371 #define IXGB_RCTL_CFI 0x00100000 372 #define IXGB_RCTL_RPDA_MASK 0x00600000 373 #define IXGB_RCTL_RPDA_MC_MAC 0x00000000 374 #define IXGB_RCTL_MC_ONLY 0x00400000 375 #define IXGB_RCTL_CFF 0x00800000 376 #define IXGB_RCTL_SECRC 0x04000000 377 #define IXGB_RDT_FPDB 0x80000000 378 379 #define IXGB_RCTL_IDLE_RX_UNIT 0 380 381 /* FCRTL Bit Masks */ 382 #define IXGB_FCRTL_XONE 0x80000000 383 384 /* RXDCTL Bit Masks */ 385 #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF 386 #define IXGB_RXDCTL_PTHRESH_SHIFT 0 387 #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00 388 #define IXGB_RXDCTL_HTHRESH_SHIFT 9 389 #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000 390 #define IXGB_RXDCTL_WTHRESH_SHIFT 18 391 392 /* RAIDC Bit Masks */ 393 #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F 394 #define IXGB_RAIDC_DELAY_MASK 0x000FF800 395 #define IXGB_RAIDC_DELAY_SHIFT 11 396 #define IXGB_RAIDC_POLL_MASK 0x1FF00000 397 #define IXGB_RAIDC_POLL_SHIFT 20 398 #define IXGB_RAIDC_RXT_GATE 0x40000000 399 #define IXGB_RAIDC_EN 0x80000000 400 401 #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220 402 #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244 403 #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122 404 #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61 405 406 /* RXCSUM Bit Masks */ 407 #define IXGB_RXCSUM_IPOFL 0x00000100 408 #define IXGB_RXCSUM_TUOFL 0x00000200 409 410 /* RAH Bit Masks */ 411 #define IXGB_RAH_ASEL_MASK 0x00030000 412 #define IXGB_RAH_ASEL_DEST 0x00000000 413 #define IXGB_RAH_ASEL_SRC 0x00010000 414 #define IXGB_RAH_AV 0x80000000 415 416 /* TCTL Bit Masks */ 417 #define IXGB_TCTL_TCE 0x00000001 418 #define IXGB_TCTL_TXEN 0x00000002 419 #define IXGB_TCTL_TPDE 0x00000004 420 421 #define IXGB_TCTL_IDLE_TX_UNIT 0 422 423 /* TXDCTL Bit Masks */ 424 #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F 425 #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00 426 #define IXGB_TXDCTL_HTHRESH_SHIFT 8 427 #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000 428 #define IXGB_TXDCTL_WTHRESH_SHIFT 16 429 430 /* TSPMT Bit Masks */ 431 #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF 432 #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000 433 #define IXGB_TSPMT_TSPBP_SHIFT 16 434 435 /* PAP Bit Masks */ 436 #define IXGB_PAP_TXPC_MASK 0x0000FFFF 437 #define IXGB_PAP_TXPV_MASK 0x000F0000 438 #define IXGB_PAP_TXPV_10G 0x00000000 439 #define IXGB_PAP_TXPV_1G 0x00010000 440 #define IXGB_PAP_TXPV_2G 0x00020000 441 #define IXGB_PAP_TXPV_3G 0x00030000 442 #define IXGB_PAP_TXPV_4G 0x00040000 443 #define IXGB_PAP_TXPV_5G 0x00050000 444 #define IXGB_PAP_TXPV_6G 0x00060000 445 #define IXGB_PAP_TXPV_7G 0x00070000 446 #define IXGB_PAP_TXPV_8G 0x00080000 447 #define IXGB_PAP_TXPV_9G 0x00090000 448 #define IXGB_PAP_TXPV_WAN 0x000F0000 449 450 /* PCSC1 Bit Masks */ 451 #define IXGB_PCSC1_LOOPBACK 0x00004000 452 453 /* PCSC2 Bit Masks */ 454 #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003 455 #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001 456 457 /* PCSS1 Bit Masks */ 458 #define IXGB_PCSS1_LOCAL_FAULT 0x00000080 459 #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004 460 461 /* PCSS2 Bit Masks */ 462 #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000 463 #define IXGB_PCSS2_DEV_PRES 0x00004000 464 #define IXGB_PCSS2_TX_LF 0x00000800 465 #define IXGB_PCSS2_RX_LF 0x00000400 466 #define IXGB_PCSS2_10GBW 0x00000004 467 #define IXGB_PCSS2_10GBX 0x00000002 468 #define IXGB_PCSS2_10GBR 0x00000001 469 470 /* XPCSS Bit Masks */ 471 #define IXGB_XPCSS_ALIGN_STATUS 0x00001000 472 #define IXGB_XPCSS_PATTERN_TEST 0x00000800 473 #define IXGB_XPCSS_LANE_3_SYNC 0x00000008 474 #define IXGB_XPCSS_LANE_2_SYNC 0x00000004 475 #define IXGB_XPCSS_LANE_1_SYNC 0x00000002 476 #define IXGB_XPCSS_LANE_0_SYNC 0x00000001 477 478 /* XPCSTC Bit Masks */ 479 #define IXGB_XPCSTC_BERT_TRIG 0x00200000 480 #define IXGB_XPCSTC_BERT_SST 0x00100000 481 #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000 482 #define IXGB_XPCSTC_BERT_PSZ_SHIFT 17 483 #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003 484 #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001 485 #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000 486 487 /* MSCA bit Masks */ 488 489 /* New Protocol Address */ 490 #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF 491 #define IXGB_MSCA_NP_ADDR_SHIFT 0 492 493 /* Either Device Type or Register Address,depending on ST_CODE */ 494 #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000 495 #define IXGB_MSCA_DEV_TYPE_SHIFT 16 496 #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000 497 #define IXGB_MSCA_PHY_ADDR_SHIFT 21 498 #define IXGB_MSCA_OP_CODE_MASK 0x0C000000 499 500 /* OP_CODE == 00, Address cycle, New Protocol */ 501 502 /* OP_CODE == 01, Write operation */ 503 504 /* OP_CODE == 10, Read operation */ 505 506 /* OP_CODE == 11, Read, auto increment, New Protocol */ 507 #define IXGB_MSCA_ADDR_CYCLE 0x00000000 508 #define IXGB_MSCA_WRITE 0x04000000 509 #define IXGB_MSCA_READ 0x08000000 510 #define IXGB_MSCA_READ_AUTOINC 0x0C000000 511 #define IXGB_MSCA_OP_CODE_SHIFT 26 512 #define IXGB_MSCA_ST_CODE_MASK 0x30000000 513 514 /* ST_CODE == 00, New Protocol */ 515 516 /* ST_CODE == 01, Old Protocol */ 517 #define IXGB_MSCA_NEW_PROTOCOL 0x00000000 518 #define IXGB_MSCA_OLD_PROTOCOL 0x10000000 519 #define IXGB_MSCA_ST_CODE_SHIFT 28 520 521 /* Initiate command, self-clearing when command completes */ 522 #define IXGB_MSCA_MDI_COMMAND 0x40000000 523 524 /*MDI In Progress Enable. */ 525 #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000 526 527 /* MSRWD bit masks */ 528 #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF 529 #define IXGB_MSRWD_WRITE_DATA_SHIFT 0 530 #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000 531 #define IXGB_MSRWD_READ_DATA_SHIFT 16 532 533 /* Definitions for the optics devices on the MDIO bus. */ 534 #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */ 535 536 /* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */ 537 #define MDIO_PMA_PMD_DID 0x01 538 #define MDIO_WIS_DID 0x02 539 #define MDIO_PCS_DID 0x03 540 #define MDIO_XGXS_DID 0x04 541 542 /* Standard PMA/PMD registers and bit definitions. */ 543 544 /* Note: This is a very limited set of definitions, */ 545 546 /* only implemented features are defined. */ 547 #define MDIO_PMA_PMD_CR1 0x0000 548 #define MDIO_PMA_PMD_CR1_RESET 0x8000 549 550 #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices 551 * only */ 552 553 /* Vendor-specific MDIO registers */ 554 #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific 555 * register */ 556 #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific 557 * register */ 558 559 #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80 560 #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00 561 #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes 562 * synchronized */ 563 564 /* Layout of a single receive descriptor. */ 565 struct ixgb_rx_desc { 566 uint64_t buff_addr; 567 uint16_t length; 568 uint16_t reserved; 569 uint8_t status; 570 uint8_t errors; 571 uint16_t special; 572 } __packed; 573 574 #define IXGB_RX_DESC_STATUS_DD 0x01 575 #define IXGB_RX_DESC_STATUS_EOP 0x02 576 #define IXGB_RX_DESC_STATUS_IXSM 0x04 577 #define IXGB_RX_DESC_STATUS_VP 0x08 578 #define IXGB_RX_DESC_STATUS_TCPCS 0x20 579 #define IXGB_RX_DESC_STATUS_IPCS 0x40 580 #define IXGB_RX_DESC_STATUS_PIF 0x80 581 582 #define IXGB_RX_DESC_ERRORS_CE 0x01 583 #define IXGB_RX_DESC_ERRORS_SE 0x02 584 #define IXGB_RX_DESC_ERRORS_P 0x08 585 #define IXGB_RX_DESC_ERRORS_TCPE 0x20 586 #define IXGB_RX_DESC_ERRORS_IPE 0x40 587 #define IXGB_RX_DESC_ERRORS_RXE 0x80 588 589 #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 590 #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 591 #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 592 */ 593 594 /* Layout of a single transmit descriptor. */ 595 struct ixgb_tx_desc { 596 uint64_t buff_addr; 597 uint32_t cmd_type_len; 598 uint8_t status; 599 uint8_t popts; 600 uint16_t vlan; 601 } __packed; 602 603 #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF 604 #define IXGB_TX_DESC_TYPE_MASK 0x00F00000 605 #define IXGB_TX_DESC_TYPE_SHIFT 20 606 #define IXGB_TX_DESC_CMD_MASK 0xFF000000 607 #define IXGB_TX_DESC_CMD_SHIFT 24 608 #define IXGB_TX_DESC_CMD_EOP 0x01000000 609 #define IXGB_TX_DESC_CMD_TSE 0x04000000 610 #define IXGB_TX_DESC_CMD_RS 0x08000000 611 #define IXGB_TX_DESC_CMD_VLE 0x40000000 612 #define IXGB_TX_DESC_CMD_IDE 0x80000000 613 614 #define IXGB_TX_DESC_TYPE 0x00100000 615 616 #define IXGB_TX_DESC_STATUS_DD 0x01 617 618 #define IXGB_TX_DESC_POPTS_IXSM 0x01 619 #define IXGB_TX_DESC_POPTS_TXSM 0x02 620 /* Priority is in upper 3 of 16 */ 621 #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT 622 623 struct ixgb_context_desc { 624 uint8_t ipcss; 625 uint8_t ipcso; 626 uint16_t ipcse; 627 uint8_t tucss; 628 uint8_t tucso; 629 uint16_t tucse; 630 uint32_t cmd_type_len; 631 uint8_t status; 632 uint8_t hdr_len; 633 uint16_t mss; 634 } __packed; 635 636 #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000 637 #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000 638 #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000 639 #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000 640 #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000 641 642 #define IXGB_CONTEXT_DESC_TYPE 0x00000000 643 644 #define IXGB_CONTEXT_DESC_STATUS_DD 0x01 645 646 /* Filters */ 647 #define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */ 648 #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 649 #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 650 651 #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0 652 #define ENET_HEADER_SIZE 14 653 #define ENET_FCS_LENGTH 4 654 #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128 655 #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60 656 #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514 657 #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00 658 659 /* Phy Addresses */ 660 #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */ 661 #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */ 662 #define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */ 663 664 /* This structure takes a 64k flash and maps it for identification commands */ 665 struct ixgb_flash_buffer { 666 uint8_t manufacturer_id; 667 uint8_t device_id; 668 uint8_t filler1[0x2AA8]; 669 uint8_t cmd2; 670 uint8_t filler2[0x2AAA]; 671 uint8_t cmd1; 672 uint8_t filler3[0xAAAA]; 673 } __packed; 674 675 /* 676 * This is a little-endian specific check. 677 */ 678 #define IS_MULTICAST(Address) \ 679 (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) 680 681 /* 682 * Check whether an address is broadcast. 683 */ 684 #define IS_BROADCAST(Address) \ 685 ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) 686 687 /* Flow control parameters */ 688 struct ixgb_fc { 689 uint32_t high_water; /* Flow Control High-water */ 690 uint32_t low_water; /* Flow Control Low-water */ 691 uint16_t pause_time; /* Flow Control Pause timer */ 692 boolean_t send_xon; /* Flow control send XON */ 693 ixgb_fc_type type; /* Type of flow control */ 694 } __packed; 695 696 /* The historical defaults for the flow control values are given below. */ 697 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 698 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 699 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 700 701 /* Phy definitions */ 702 #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF 703 #define IXGB_MAX_PHY_ADDRESS 31 704 #define IXGB_MAX_PHY_DEV_TYPE 31 705 706 /* Bus parameters */ 707 struct ixgb_bus { 708 ixgb_bus_speed speed; 709 ixgb_bus_width width; 710 ixgb_bus_type type; 711 }; 712 713 struct ixgb_hw { 714 uint8_t *hw_addr; /* Base Address of the hardware */ 715 void *back; /* Pointer to OS-dependent struct */ 716 struct ixgb_fc fc; /* Flow control parameters */ 717 struct ixgb_bus bus; /* Bus parameters */ 718 uint32_t phy_id; /* Phy Identifier */ 719 uint32_t phy_addr; /* XGMII address of Phy */ 720 ixgb_mac_type mac_type; /* Identifier for MAC controller */ 721 ixgb_phy_type phy_type; /* Transceiver/phy identifier */ 722 uint32_t max_frame_size; /* Maximum frame size supported */ 723 uint32_t mc_filter_type; /* Multicast filter hash type */ 724 uint32_t num_mc_addrs; /* Number of current Multicast addrs */ 725 /* Individual address currently programmed in MAC */ 726 uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; 727 uint32_t num_tx_desc; /* Number of Transmit descriptors */ 728 uint32_t num_rx_desc; /* Number of Receive descriptors */ 729 uint32_t rx_buffer_size; /* Size of Receive buffer */ 730 boolean_t link_up; /* TRUE if link is valid */ 731 boolean_t adapter_stopped; /* State of adapter */ 732 uint16_t device_id; /* device id from PCI configuration space */ 733 uint16_t vendor_id; /* vendor id from PCI configuration space */ 734 uint8_t revision_id; /* revision id from PCI configuration space */ 735 uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI 736 * configuration space */ 737 uint16_t subsystem_id; /* subsystem id from PCI configuration space */ 738 uint32_t bar0; /* Base Address registers */ 739 uint32_t bar1; 740 uint32_t bar2; 741 uint32_t bar3; 742 uint16_t pci_cmd_word; /* PCI command register id from PCI 743 * configuration space */ 744 uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init 745 * time */ 746 unsigned long io_base; /* Our I/O mapped location */ 747 uint32_t lastLFC; 748 uint32_t lastRFC; 749 }; 750 751 /* Statistics reported by the hardware */ 752 struct ixgb_hw_stats { 753 uint64_t tprl; 754 uint64_t tprh; 755 uint64_t gprcl; 756 uint64_t gprch; 757 uint64_t bprcl; 758 uint64_t bprch; 759 uint64_t mprcl; 760 uint64_t mprch; 761 uint64_t uprcl; 762 uint64_t uprch; 763 uint64_t vprcl; 764 uint64_t vprch; 765 uint64_t jprcl; 766 uint64_t jprch; 767 uint64_t gorcl; 768 uint64_t gorch; 769 uint64_t torl; 770 uint64_t torh; 771 uint64_t rnbc; 772 uint64_t ruc; 773 uint64_t roc; 774 uint64_t rlec; 775 uint64_t crcerrs; 776 uint64_t icbc; 777 uint64_t ecbc; 778 uint64_t mpc; 779 uint64_t tptl; 780 uint64_t tpth; 781 uint64_t gptcl; 782 uint64_t gptch; 783 uint64_t bptcl; 784 uint64_t bptch; 785 uint64_t mptcl; 786 uint64_t mptch; 787 uint64_t uptcl; 788 uint64_t uptch; 789 uint64_t vptcl; 790 uint64_t vptch; 791 uint64_t jptcl; 792 uint64_t jptch; 793 uint64_t gotcl; 794 uint64_t gotch; 795 uint64_t totl; 796 uint64_t toth; 797 uint64_t dc; 798 uint64_t plt64c; 799 uint64_t tsctc; 800 uint64_t tsctfc; 801 uint64_t ibic; 802 uint64_t rfc; 803 uint64_t lfc; 804 uint64_t pfrc; 805 uint64_t pftc; 806 uint64_t mcfrc; 807 uint64_t mcftc; 808 uint64_t xonrxc; 809 uint64_t xontxc; 810 uint64_t xoffrxc; 811 uint64_t xofftxc; 812 uint64_t rjc; 813 }; 814 815 /* Function Prototypes */ 816 extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw); 817 extern boolean_t ixgb_init_hw(struct ixgb_hw *hw); 818 extern void ixgb_check_for_link(struct ixgb_hw *hw); 819 extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw); 820 extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index); 821 extern void ixgb_init_rx_addrs(struct ixgb_hw *hw); 822 extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw); 823 extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw); 824 extern boolean_t mac_addr_valid(uint8_t *mac_addr); 825 826 extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr, 827 uint32_t phy_addr, uint32_t device_type); 828 829 extern void ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr, 830 uint32_t phy_addr, uint32_t device_type, 831 uint16_t data); 832 833 834 /* Filters (multicast, vlan, receive) */ 835 extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list, 836 uint32_t mc_addr_count, uint32_t pad); 837 838 /* Vfta functions */ 839 extern void ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, 840 uint32_t value); 841 842 extern void ixgb_clear_vfta(struct ixgb_hw *hw); 843 844 /* Access functions to eeprom data */ 845 void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr); 846 uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw); 847 uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw); 848 boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw); 849 uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index); 850 851 /* Everything else */ 852 void ixgb_led_on(struct ixgb_hw *hw); 853 void ixgb_led_off(struct ixgb_hw *hw); 854 void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value); 855 856 #endif /* _IXGB_HW_H_ */ 857