Searched refs:InsElt (Results 1 – 7 of 7) sorted by relevance
/openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 729 if (InsElt->hasOneUse() && isa<InsertElementInst>(InsElt->user_back())) in replaceExtractElements() 1194 if (InsElt.hasOneUse() && isa<InsertElementInst>(InsElt.user_back())) in foldInsSequenceIntoSplat() 1197 VectorType *VecTy = InsElt.getType(); in foldInsSequenceIntoSplat() 1209 Value *SplatVal = InsElt.getOperand(1); in foldInsSequenceIntoSplat() 1210 InsertElementInst *CurrIE = &InsElt; in foldInsSequenceIntoSplat() 1225 if (CurrIE != &InsElt && in foldInsSequenceIntoSplat() 1235 if (FirstIE == &InsElt) in foldInsSequenceIntoSplat() 1281 Value *X = InsElt.getOperand(1); in foldInsEltIntoSplat() 1320 Value *Scalar = InsElt.getOperand(1); in foldInsEltIntoIdentityShuffle() 1493 Value *Vec = InsElt.getOperand(0); in narrowInsElt() [all …]
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H A D | InstCombineCasts.cpp | 780 auto *InsElt = dyn_cast<InsertElementInst>(Trunc.getOperand(0)); in shrinkInsertElt() local 781 if (!InsElt || !InsElt->hasOneUse()) in shrinkInsertElt() 786 Value *VecOp = InsElt->getOperand(0); in shrinkInsertElt() 787 Value *ScalarOp = InsElt->getOperand(1); in shrinkInsertElt() 788 Value *Index = InsElt->getOperand(2); in shrinkInsertElt() 2809 if (auto *InsElt = dyn_cast<InsertElementInst>(Src)) in visitBitCast() local 2810 return new BitCastInst(InsElt->getOperand(1), DestTy); in visitBitCast()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 712 auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero); in buildShuffleSplat() local 714 return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask); in buildShuffleSplat()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 4732 auto InsElt = in emitVectorConcat() local 4738 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitVectorConcat() 4739 return &*InsElt; in emitVectorConcat() 5256 MachineInstr *InsElt = nullptr; in emitLaneInsert() local 5269 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert() 5274 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert() 5279 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitLaneInsert() 5280 return InsElt; in emitLaneInsert()
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/openbsd/gnu/llvm/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 8668 auto *InsElt = dyn_cast<InsertElementInst>(Vec); in gather() local 8669 if (!InsElt) in gather() 8671 GatherShuffleExtractSeq.insert(InsElt); in gather() 8672 CSEBlocks.insert(InsElt->getParent()); in gather() 8677 ExternalUses.emplace_back(V, InsElt, FoundLane); in gather()
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 15325 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine() local 15327 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 23846 if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG)) in visitVECTOR_SHUFFLE() local 23847 return InsElt; in visitVECTOR_SHUFFLE()
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