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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7617 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 macro
H A Ddce_8_0_sh_mask.h3192 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_10_0_sh_mask.h3114 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_11_0_sh_mask.h3184 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_11_2_sh_mask.h3432 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_12_0_sh_mask.h9252 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21249 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40003 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43237 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42519 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48746 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49115 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro