| /openbsd/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; }
64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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| H A D | LanaiInstrInfo.cpp | 754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
758 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth()
760 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth()
761 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth()
764 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth()
785 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
786 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
795 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
798 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth()
812 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 71 const MachineInstr &LdSt,
76 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 298 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
301 unsigned Opc = LdSt.getOpcode(); in getMemOperandsWithOffsetWidth()
306 if (isDS(LdSt)) { in getMemOperandsWithOffsetWidth()
341 if (LdSt.mayLoad()) in getMemOperandsWithOffsetWidth()
344 assert(LdSt.mayStore()); in getMemOperandsWithOffsetWidth()
368 if (isMUBUF(LdSt) || isMTBUF(LdSt)) { in getMemOperandsWithOffsetWidth()
393 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
397 if (isMIMG(LdSt)) { in getMemOperandsWithOffsetWidth()
411 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
415 if (isSMRD(LdSt)) { in getMemOperandsWithOffsetWidth()
[all …]
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| H A D | SIInstrInfo.h | 195 const MachineInstr &LdSt,
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 661 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
662 LLT PtrTy = MRI.getType(LdSt.getPointerReg()); in select()
672 I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(), in select()
673 LdSt.getMemSizeInBits()); in select()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2865 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster()
2868 if (LdSt.getOperand(2).isFI()) in isLdStSafeToCluster()
2874 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI)) in isLdStSafeToCluster()
5643 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
5647 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5648 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5650 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5651 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5654 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
5658 Offset = LdSt.getOperand(1).getImm(); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | PPCInstrInfo.h | 662 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
672 const MachineInstr &LdSt,
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1755 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
1757 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth()
1763 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
1765 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
1768 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
1771 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth()
1772 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
1773 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
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| H A D | RISCVInstrInfo.h | 131 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2589 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
2625 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2627 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth()
2628 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
2632 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth()
2633 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) || in getMemOperandWithOffsetWidth()
2634 !LdSt.getOperand(3).isImm()) in getMemOperandWithOffsetWidth()
2651 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2652 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2656 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | AArch64InstrInfo.h | 155 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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| H A D | AArch64SchedTSV110.td | 135 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
138 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2813 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
2823 uint64_t MemSizeInBytes = LdSt.getMemSize(); in select()
2831 assert(!isa<GZExtLoad>(LdSt)); in select()
2835 if (isa<GLoad>(LdSt)) { in select()
2848 Register ValReg = LdSt.getReg(0); in select()
2872 const Register ValReg = LdSt.getReg(0); in select()
2880 LLT MemTy = LdSt.getMMO().getMemoryType(); in select()
2890 LdSt.getOperand(0).setReg(Copy); in select()
2900 Register OldDst = LdSt.getReg(0); in select()
2903 LdSt.getOperand(0).setReg(NewDst); in select()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 209 const MachineInstr &LdSt,
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| H A D | HexagonInstrInfo.cpp | 3041 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3045 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); in getMemOperandsWithOffsetWidth()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 342 const MachineInstr &LdSt,
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleR52.td | 551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
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| H A D | ARMISelDAGToDAG.cpp | 1086 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
1087 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1092 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) in SelectAddrMode6Offset()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1384 if (auto *LdSt = dyn_cast<GLoadStore>(&UseMI)) { in matchPtrAddImmedChain() local
1385 AccessTy = getTypeForLLT(MRI.getType(LdSt->getReg(0)), in matchPtrAddImmedChain()
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