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Searched refs:MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h9543 #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018 macro
H A Dgmc_7_1_sh_mask.h6570 #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18 macro
H A Dgmc_8_1_sh_mask.h7484 #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18 macro