1 /* $OpenBSD: octmmcreg.h,v 1.3 2017/10/16 14:18:47 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Visa Hankala 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _OCTMMCREG_H_ 20 #define _OCTMMCREG_H_ 21 22 #define MIO_BOOT_CFG 0x00011800000000d0ull 23 24 /* 25 * MMC registers 26 */ 27 28 #define MIO_EMM_CFG 0x00 29 #define MIO_EMM_SWITCH 0x48 30 #define MIO_EMM_SWITCH_RES_62_63 0xc000000000000000ull 31 #define MIO_EMM_SWITCH_BUS_ID 0x3000000000000000ull 32 #define MIO_EMM_SWITCH_BUS_ID_SHIFT 60 33 #define MIO_EMM_SWITCH_SWITCH_EXE 0x0800000000000000ull 34 #define MIO_EMM_SWITCH_SWITCH_ERR0 0x0400000000000000ull 35 #define MIO_EMM_SWITCH_SWITCH_ERR1 0x0200000000000000ull 36 #define MIO_EMM_SWITCH_SWITCH_ERR2 0x0100000000000000ull 37 #define MIO_EMM_SWITCH_RES_49_55 0x00fe000000000000ull 38 #define MIO_EMM_SWITCH_HS_TIMING 0x0001000000000000ull 39 #define MIO_EMM_SWITCH_HS_TIMING_SHIFT 48 40 #define MIO_EMM_SWITCH_RES_43_47 0x0000f80000000000ull 41 #define MIO_EMM_SWITCH_BUS_WIDTH 0x0000070000000000ull 42 #define MIO_EMM_SWITCH_BUS_WIDTH_SHIFT 40 43 #define MIO_EMM_SWITCH_RES_36_39 0x000000f000000000ull 44 #define MIO_EMM_SWITCH_POWER_CLASS 0x0000000f00000000ull 45 #define MIO_EMM_SWITCH_POWER_CLASS_SHIFT 32 46 #define MIO_EMM_SWITCH_CLK_HI 0x00000000ffff0000ull 47 #define MIO_EMM_SWITCH_CLK_HI_SHIFT 16 48 #define MIO_EMM_SWITCH_CLK_LO 0x000000000000ffffull 49 #define MIO_EMM_SWITCH_CLK_LO_SHIFT 0 50 #define MIO_EMM_SWITCH_CLK_MAX 0xffffu 51 #define MIO_EMM_DMA 0x50 52 #define MIO_EMM_DMA_RES_62_63 0xc000000000000000ull 53 #define MIO_EMM_DMA_BUS_ID 0x3000000000000000ull 54 #define MIO_EMM_DMA_BUS_ID_SHIFT 60 55 #define MIO_EMM_DMA_DMA_VAL 0x0800000000000000ull 56 #define MIO_EMM_DMA_SECTOR 0x0400000000000000ull 57 #define MIO_EMM_DMA_DAT_NULL 0x0200000000000000ull 58 #define MIO_EMM_DMA_THRES 0x01f8000000000000ull 59 #define MIO_EMM_DMA_REL_WR 0x0004000000000000ull 60 #define MIO_EMM_DMA_RW 0x0002000000000000ull 61 #define MIO_EMM_DMA_MULTI 0x0001000000000000ull 62 #define MIO_EMM_DMA_BLOCK_CNT 0x0000ffff00000000ull 63 #define MIO_EMM_DMA_BLOCK_CNT_SHIFT 32 64 #define MIO_EMM_DMA_CARD_ADDR 0x00000000ffffffffull 65 #define MIO_EMM_CMD 0x58 66 #define MIO_EMM_CMD_RES_62_63 0xc000000000000000ull 67 #define MIO_EMM_CMD_BUS_ID 0x3000000000000000ull 68 #define MIO_EMM_CMD_BUS_ID_SHIFT 60 69 #define MIO_EMM_CMD_CMD_VAL 0x0800000000000000ull 70 #define MIO_EMM_CMD_RES_56_58 0x0700000000000000ull 71 #define MIO_EMM_CMD_DBUF 0x0080000000000000ull 72 #define MIO_EMM_CMD_OFFSET 0x007e000000000000ull 73 #define MIO_EMM_CMD_RES_43_48 0x0001f80000000000ull 74 #define MIO_EMM_CMD_CTYPE_XOR 0x0000060000000000ull 75 #define MIO_EMM_CMD_CTYPE_XOR_SHIFT 41 76 #define MIO_EMM_CMD_RTYPE_XOR 0x000001c000000000ull 77 #define MIO_EMM_CMD_RTYPE_XOR_SHIFT 38 78 #define MIO_EMM_CMD_CMD_IDX 0x0000003f00000000ull 79 #define MIO_EMM_CMD_CMD_IDX_SHIFT 32 80 #define MIO_EMM_CMD_ARG 0x00000000ffffffffull 81 #define MIO_EMM_RSP_STS 0x60 82 #define MIO_EMM_RSP_STS_RES_62_63 0xc000000000000000ull 83 #define MIO_EMM_RSP_STS_BUS_ID 0x3000000000000000ull 84 #define MIO_EMM_RSP_STS_CMD_VAL 0x0800000000000000ull 85 #define MIO_EMM_RSP_STS_SWITCH_VAL 0x0400000000000000ull 86 #define MIO_EMM_RSP_STS_DMA_VAL 0x0200000000000000ull 87 #define MIO_EMM_RSP_STS_DMA_PEND 0x0100000000000000ull 88 #define MIO_EMM_RSP_STS_RES_29_55 0x00ffffffe0000000ull 89 #define MIO_EMM_RSP_STS_DBUF_ERR 0x0000000010000000ull 90 #define MIO_EMM_RSP_STS_RES_24_27 0x000000000f000000ull 91 #define MIO_EMM_RSP_STS_DBUF 0x0000000000800000ull 92 #define MIO_EMM_RSP_STS_DBUF_SHIFT 23 93 #define MIO_EMM_RSP_STS_BLK_TIMEOUT 0x0000000000400000ull 94 #define MIO_EMM_RSP_STS_BLK_CRC_ERR 0x0000000000200000ull 95 #define MIO_EMM_RSP_STS_RSP_BUSY 0x0000000000100000ull 96 #define MIO_EMM_RSP_STS_STP_TIMEOUT 0x0000000000080000ull 97 #define MIO_EMM_RSP_STS_STP_CRC_ERR 0x0000000000040000ull 98 #define MIO_EMM_RSP_STS_STP_BAD_STS 0x0000000000020000ull 99 #define MIO_EMM_RSP_STS_STP_VAL 0x0000000000010000ull 100 #define MIO_EMM_RSP_STS_RSP_TIMEOUT 0x0000000000008000ull 101 #define MIO_EMM_RSP_STS_RSP_CRC_ERR 0x0000000000004000ull 102 #define MIO_EMM_RSP_STS_RSP_BAD_STS 0x0000000000002000ull 103 #define MIO_EMM_RSP_STS_RSP_VAL 0x0000000000001000ull 104 #define MIO_EMM_RSP_STS_RSP_TYPE 0x0000000000000e00ull 105 #define MIO_EMM_RSP_STS_CMD_TYPE 0x0000000000000180ull 106 #define MIO_EMM_RSP_STS_CMD_IDX 0x000000000000007eull 107 #define MIO_EMM_RSP_STS_CMD_IDX_SHIFT 1 108 #define MIO_EMM_RSP_STS_CMD_DONE 0x0000000000000001ull 109 #define MIO_EMM_RSP_LO 0x68 110 #define MIO_EMM_RSP_HI 0x70 111 #define MIO_EMM_INT 0x78 112 #define MIO_EMM_INT_RES_7_63 0xffffffffffffff80ull 113 #define MIO_EMM_INT_SWITCH_ERR 0x0000000000000040ull 114 #define MIO_EMM_INT_SWITCH_DONE 0x0000000000000020ull 115 #define MIO_EMM_INT_DMA_ERR 0x0000000000000010ull 116 #define MIO_EMM_INT_CMD_ERR 0x0000000000000008ull 117 #define MIO_EMM_INT_DMA_DONE 0x0000000000000004ull 118 #define MIO_EMM_INT_CMD_DONE 0x0000000000000002ull 119 #define MIO_EMM_INT_BUF_DONE 0x0000000000000001ull 120 #define MIO_EMM_INT_EN 0x80 121 #define MIO_EMM_WDOG 0x88 122 #define MIO_EMM_WDOG_CLK_CNT 0x0000000003ffffffull 123 #define MIO_EMM_SAMPLE 0x90 124 #define MIO_EMM_SAMPLE_CMD_CNT 0x0000000003ff0000ull 125 #define MIO_EMM_SAMPLE_CMD_CNT_SHIFT 16 126 #define MIO_EMM_SAMPLE_DAT_CNT 0x00000000000003ffull 127 #define MIO_EMM_SAMPLE_DAT_CNT_SHIFT 0 128 #define MIO_EMM_STS_MASK 0x98 129 #define MIO_EMM_RCA 0xa0 130 #define MIO_EMM_BUF_IDX 0xe0 131 #define MIO_EMM_BUF_IDX_RES_17_63 0xfffffffffffe0000ull 132 #define MIO_EMM_BUF_IDX_INC 0x0000000000010000ull 133 #define MIO_EMM_BUF_IDX_RES_7_15 0x000000000000ff80ull 134 #define MIO_EMM_BUF_IDX_BUF_NUM 0x0000000000000040ull 135 #define MIO_EMM_BUF_IDX_BUF_NUM_SHIFT 6 136 #define MIO_EMM_BUF_IDX_OFFSET 0x000000000000003full 137 #define MIO_EMM_BUF_DAT 0xe8 138 139 /* 140 * MMC DMA FIFO registers 141 */ 142 143 /* Size of the register space. */ 144 #define MIO_EMM_DMA_FIFO_REGSIZE 0x20 145 146 #define MIO_EMM_DMA_FIFO_CFG 0x00 147 #define MIO_EMM_DMA_FIFO_CFG_CLR 0x0000000000010000ull 148 149 #define MIO_EMM_DMA_FIFO_ADR 0x10 150 151 #define MIO_EMM_DMA_FIFO_CMD 0x18 152 #define MIO_EMM_DMA_FIFO_CMD_RW 0x4000000000000000ull 153 #define MIO_EMM_DMA_FIFO_CMD_INTDIS 0x1000000000000000ull 154 #define MIO_EMM_DMA_FIFO_CMD_SIZE 0x00fffff000000000ull 155 #define MIO_EMM_DMA_FIFO_CMD_SIZE_SHIFT 36 156 157 /* 158 * NAND flash DMA registers 159 */ 160 161 #define MIO_NDF_DMA_CFG 0x00 162 #define MIO_NDF_DMA_CFG_EN 0x8000000000000000ull 163 #define MIO_NDF_DMA_CFG_RW 0x4000000000000000ull 164 #define MIO_NDF_DMA_CFG_CLR 0x2000000000000000ull 165 #define MIO_NDF_DMA_CFG_RES_60_60 0x1000000000000000ull 166 #define MIO_NDF_DMA_CFG_SWAP32 0x0800000000000000ull 167 #define MIO_NDF_DMA_CFG_SWAP16 0x0400000000000000ull 168 #define MIO_NDF_DMA_CFG_SWAP8 0x0200000000000000ull 169 #define MIO_NDF_DMA_CFG_ENDIAN 0x0100000000000000ull 170 #define MIO_NDF_DMA_CFG_SIZE 0x00fffff000000000ull 171 #define MIO_NDF_DMA_CFG_SIZE_SHIFT 36 172 #define MIO_NDF_DMA_CFG_ADDR 0x0000000fffffffffull 173 #define MIO_NDF_DMA_ADR 0x08 174 175 #endif /* !_OCTMMCREG_H_ */ 176