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Searched refs:MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_sh_mask.h2668 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_2_3_0_sh_mask.h3009 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_9_1_sh_mask.h3198 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_1_0_sh_mask.h3746 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_9_3_0_sh_mask.h3754 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_1_8_0_sh_mask.h9166 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_1_7_sh_mask.h11131 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro
H A Dmmhub_9_4_1_sh_mask.h8782 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK … macro