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Searched refs:MRI (Results 1 – 25 of 674) sorted by relevance

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/openbsd/gnu/usr.bin/binutils/ld/
H A Dldlex.l122 %s MRI
151 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
313 <MRI>"#".*\n? { ++ lineno; }
315 <MRI>"*".* { /* Mri comment line */ }
318 <MRI>"ALIGNMOD" { RTOKEN(ALIGNMOD);}
319 <MRI>"ALIGN" { RTOKEN(ALIGN_K);}
332 <MRI>"SECT" { RTOKEN(SECT); }
335 <MRI>"alignmod" { RTOKEN(ALIGNMOD);}
336 <MRI>"align" { RTOKEN(ALIGN_K);}
350 <MRI>"sect" { RTOKEN(SECT); }
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/ld/
H A Dldlex.l119 %s MRI
148 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
319 <MRI>"#".*\n? { ++ lineno; }
321 <MRI>"*".* { /* Mri comment line */ }
324 <MRI>"ALIGNMOD" { RTOKEN(ALIGNMOD);}
325 <MRI>"ALIGN" { RTOKEN(ALIGN_K);}
338 <MRI>"SECT" { RTOKEN(SECT); }
341 <MRI>"alignmod" { RTOKEN(ALIGNMOD);}
342 <MRI>"align" { RTOKEN(ALIGN_K);}
356 <MRI>"sect" { RTOKEN(SECT); }
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h41 MachineRegisterInfo &MRI,
46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
64 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
75 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
84 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
130 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp101 MachineRegisterInfo &MRI; member in __anonf909820b0111::ApplyRegBankMapping
175 MRI.setRegBank(Reg, *RB); in applyBank()
650 MRI->setRegBank(LoLHS, *Bank); in split64BitValueForMapping()
651 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
667 MRI.setType(Reg, NewTy); in setRegsToType()
687 LLT Ty = MRI.getType(Src); in buildReadFirstLane()
1185 LLT PtrTy = MRI.getType(Dst); in applyMappingDynStackAlloc()
1341 LLT Ty = MRI.getType(Dst); in applyMappingSBufferLoad()
1462 LLT Ty = MRI.getType(DstReg); in applyMappingBFE()
1637 MRI.setRegBank(Zero, in applyMappingMAD_64_32()
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H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
67 MachineRegisterInfo &MRI,
70 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI) const;
80 MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI, int RSrcIdx) const;
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
151 unsigned getMappingType(const MachineRegisterInfo &MRI,
186 MachineRegisterInfo &MRI,
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H A DGCNRegPressure.cpp41 const auto RC = MRI.getRegClass(Reg); in getRegKind()
64 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
166 MRI.getMaxLaneMaskForVReg(MO.getReg()) : in getDefRegMask()
229 LiveMask = MRI.getMaxLaneMaskForVReg(Reg); in getLiveLaneMask()
253 MRI = &MF.getRegInfo(); in reset()
271 assert(MRI && "call reset first"); in recede()
299 LiveMask &= ~getDefRegMask(MO, *MRI); in recede()
327 assert(MRI && "call reset first"); in advanceBeforeNext()
378 LiveMask |= getDefRegMask(MO, *MRI); in advanceToNext()
441 << print(LISLR, *MRI); in isValid()
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H A DAMDGPUCombinerHelper.cpp126 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
187 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
193 if (MRI.hasOneNonDBGUse(Src)) { in matchFoldableFneg()
194 if (allUsesHaveSourceMods(MI, MRI, 0)) in matchFoldableFneg()
198 (allUsesHaveSourceMods(MI, MRI) || in matchFoldableFneg()
270 replaceRegOpWith(MRI, Op, Reg); in applyFoldableFneg()
278 replaceRegOpWith(MRI, X, XReg); in applyFoldableFneg()
280 replaceRegOpWith(MRI, Y, YReg); in applyFoldableFneg()
283 replaceRegOpWith(MRI, Y, YReg); in applyFoldableFneg()
361 if (MRI.hasOneNonDBGUse(MatchInfoDst)) { in applyFoldableFneg()
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H A DAMDGPUInstructionSelector.cpp69 MRI = &MF.getRegInfo(); in setupMF()
130 if (isVCC(DstReg, *MRI)) { in selectCOPY()
139 if (!isVCC(SrcReg, *MRI)) { in selectCOPY()
418 if (isVCC(Dst1Reg, *MRI)) { in selectG_UADDO_USUBO_UADDE_USUBE()
1022 LLT Ty = MRI->getType(Dst0); in selectDivScale()
1286 if (!isVCC(CCReg, *MRI)) { in selectG_ICMP()
1319 if (isVCC(Dst, *MRI)) in selectIntrinsicCmp()
2084 if (!isVCC(CCReg, *MRI)) { in selectG_SELECT()
2094 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
3667 MachineRegisterInfo &MRI in selectVOP3PMods() local
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp204 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) in canReplaceReg()
209 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); in canReplaceReg()
435 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal()
444 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies()
451 auto SrcTy = MRI.getType(SrcReg); in getDefSrcRegIgnoringCopies()
454 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
752 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
771 LLT Ty = MRI.getType(Op1); in ConstantFoldExtOp()
794 LLT Ty = MRI.getType(Src); in ConstantFoldCTLZ()
831 const LLT Ty = MRI.getType(Reg); in isKnownToBeAPowerOfTwo()
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H A DCombinerHelper.cpp79 LLT Ty = MRI.getType(V); in buildLogBase2()
2655 if (MRI.hasOneUse(DstReg) && MRI.use_instr_begin(DstReg)->getOpcode() == in matchCombineInsertVecElts()
2732 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg)) in matchHoistLogicOpWithSameOpcodeHands()
2862 Dst, MRI, in matchOverlappingAnd()
3223 return isConstantOrConstantVector(*MRI.getVRegDef(OtherOperandReg), MRI, in matchFoldBinOpIntoSelect()
3311 if (!MRI.hasOneNonDBGUse(OrLHS) || !MRI.hasOneNonDBGUse(OrRHS)) in findCandidatesForLoadOrCombine()
3657 else if (MRI.getType(SrcVal) != MRI.getType(FoundSrcVal)) in getTruncStoreByteOffset()
4355 Src, MRI, in matchBitfieldExtractFromSExtInReg()
5977 MI, MRI, in matchBuildVectorIdentityFold()
5987 MI, MRI, in matchBuildVectorIdentityFold()
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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h89 Register constrainRegToClass(MachineRegisterInfo &MRI,
104 MachineRegisterInfo &MRI,
123 MachineRegisterInfo &MRI,
193 Register VReg, const MachineRegisterInfo &MRI,
215 const MachineRegisterInfo &MRI);
252 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef()
302 return isKnownNeverNaN(Val, MRI, true); in isKnownNeverSNaN()
415 const MachineRegisterInfo &MRI,
421 const MachineRegisterInfo &MRI,
445 const MachineRegisterInfo &MRI,
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H A DMIPatternMatch.h27 return P.match(MRI, R); in mi_match()
33 return P.match(MRI, &MI); in mi_match()
42 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
56 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
288 return P.match(MRI, src) && And<Preds...>::match(MRI, src);
306 return P.match(MRI, src) || Or<Preds...>::match(MRI, src);
328 MI = MRI.getVRegDef(Reg);
342 Ty = MRI.getType(Reg);
659 if (!P.match(MRI, TmpPred))
663 if (L.match(MRI, LHS) && R.match(MRI, RHS))
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H A DLegalizationArtifactCombiner.h35 MachineRegisterInfo &MRI; variable
53 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
70 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
83 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
126 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
131 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
185 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
202 if (mi_match(SrcReg, MRI, in tryCombineSExt()
557 MachineRegisterInfo &MRI; variable
863 LLT DstTy = MRI.getType(Dst); in tryCombineMergeLike()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anonbc831c490111::AArch64AdvSIMDScalar
145 MRI) && in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
151 MRI)) { in getSrcFromCopy()
208 if (!MRI->def_empty(OrigSrc0)) { in isProfitableToTransform()
210 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform()
223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
301 if (!MRI->def_empty(OrigSrc0)) { in transformInstruction()
320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction()
[all …]
H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
60 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
67 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
74 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
81 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
121 (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
140 [{ return trySwapICmpOperands(*${root}, MRI); }]),
174 [{ return lowerVectorFCMP(*${root}, MRI, B); }]),
188 [{ return matchFoldMergeToZext(*${d}, MRI); }]),
202 [{ return matchSplitStoreZero128(*${d}, MRI); }]),
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp247 LLT Ty = MRI.getType(Reg); in selectDebugInstr()
396 return selectCopy(I, MRI); in select()
547 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
573 X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM); in selectLoadStoreOp()
607 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
660 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
852 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
856 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
947 LLT Ty = MRI.getType(LHS); in selectCmp()
1024 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp681 auto &MRI = MF.getRegInfo(); in getImmedFromMO() local
1117 LLT Ty = MRI.getType(True); in emitSelect()
1182 if (mi_match(Reg, MRI, in emitSelect()
2337 Dst, MRI, in earlySelect()
4618 LLT Ty = MRI.getType(Dst); in emitCSetForFCmp()
4644 LLT Ty = MRI.getType(LHS); in emitFPCompare()
4855 auto &MRI = *MIB.getMRI(); in emitConditionalComparison() local
4898 auto &MRI = *MIB.getMRI(); in emitConjunctionRec() local
5134 if (isCMN(LHSDef, P, MRI)) in tryFoldIntegerCompare()
5147 if (isCMN(RHSDef, P, MRI)) in tryFoldIntegerCompare()
[all …]
H A DAArch64PostLegalizerCombiner.cpp54 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
79 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
82 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
125 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine() argument
131 const LLT Ty = MRI.getType(LHS); in matchAArch64MulConstCombine()
156 if (MRI.hasOneNonDBGUse(LHS) && in matchAArch64MulConstCombine()
157 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
161 if (MRI.hasOneNonDBGUse(Dst)) { in matchAArch64MulConstCombine()
280 return MRI.getType(Dst).isScalar() && in matchMutateAnyExtToZExt()
281 mi_match(Src, MRI, in matchMutateAnyExtToZExt()
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H A DAArch64PostLegalizerLowering.cpp228 LLT Ty = MRI.getType(Dst); in matchREV()
331 MRI)) in matchDupFromInsertVectorElt()
410 LLT DstTy = MRI.getType(Dst); in matchEXT()
564 const auto &Ty = MRI.getType(RHS); in tryAdjustICmpImmAndPred()
792 if (!MRI.hasOneNonDBGUse(CmpOp)) in getCmpOperandFoldingProfit()
901 LLT DstTy = MRI.getType(LHS); in getVectorFCMP()
958 LLT DstTy = MRI.getType(Dst); in lowerVectorFCMP()
969 auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI); in lowerVectorFCMP()
1003 MRI.replaceRegWith(Dst, CmpRes); in lowerVectorFCMP()
1012 if (MRI.getType(DstReg).isVector()) in matchFormTruncstore()
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H A DAArch64PreLegalizerCombiner.cpp74 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
82 !mi_match(RHS, MRI, m_SpecificICst(0))) in matchICmpRedundantTrunc()
85 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
100 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
151 UseInstr.getOperand(2).getReg(), MRI); in matchFoldGlobalOffset()
256 auto &MRI = *B.getMRI(); in tryToSimplifyUADDO() local
265 LLT WideTy0 = MRI.getType(Op0Wide); in tryToSimplifyUADDO()
266 LLT WideTy1 = MRI.getType(Op1Wide); in tryToSimplifyUADDO()
268 LLT OpTy = MRI.getType(ResVal); in tryToSimplifyUADDO()
289 if (!MRI.hasOneNonDBGUse(ResStatus)) in tryToSimplifyUADDO()
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H A DAArch64RegisterBankInfo.cpp529 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
547 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyUsesFP()
566 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyDefinesFP()
683 LLT Ty = MRI.getType(MO.getReg()); in getInstrMapping()
703 LLT ScalarTy = MRI.getType(ScalarReg); in getInstrMapping()
704 auto ScalarDef = MRI.getVRegDef(ScalarReg); in getInstrMapping()
708 onlyDefinesFP(*ScalarDef, MRI, TRI))) in getInstrMapping()
798 if (onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
848 onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
926 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
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/openbsd/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp114 if (!MRI->getUniqueVRegDef(MO.getReg())) in checkADDrr()
171 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
179 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
183 if (!MRI->getUniqueVRegDef(I->getReg())) in processCandidate()
200 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
206 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
214 if (IsAma && MRI->getUniqueVRegDef(I->getReg())) in processDstReg()
215 processInst(MRI, I->getParent(), &*I, GVal); in processDstReg()
249 checkADDrr(MRI, RelocOp, GVal); in processInst()
260 MachineRegisterInfo *MRI = &MF->getRegInfo(); in removeLD() local
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/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp42 MachineRegisterInfo &MRI = MF.getRegInfo(); in addConstantsToTrack() local
182 if (!MRI.getRegClassOrNull(Reg)) in propagateSPIRVType()
198 MachineInstr *Def = MRI.getVRegDef(Reg); in insertAssignInstr()
203 Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg)); in insertAssignInstr()
205 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
257 if (MRI.hasOneUse(Reg)) { in generateAssignInstrs()
316 if (MRI.getType(ValReg).isPointer()) { in createNewIdReg()
326 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
361 processInstr(MI, MIB, MRI, GR); in processInstrsWithTypeFolding()
376 if (MRI.getType(DstReg).isVector()) in processInstrsWithTypeFolding()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
844 auto &MRI = MF.getRegInfo(); in select() local
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1034 return selectSelect(MIB, MRI); in select()
1038 return selectCmp(Helper, MIB, MRI); in select()
1057 return selectCmp(Helper, MIB, MRI); in select()
1077 return selectGlobal(MIB, MRI); in select()
[all …]

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