| /openbsd/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 66 case ISD::MSTORE: in getVVPOpcode()
203 case ISD::MSTORE: in getMaskPos()
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| H A D | VEISelLowering.cpp | 346 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1944 case ISD::MSTORE: in LowerOperation()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1212 MSTORE, enumerator
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| H A D | SelectionDAGNodes.h | 1384 case ISD::MSTORE:
1427 case ISD::MSTORE:
2653 N->getOpcode() == ISD::MSTORE;
2694 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2716 return N->getOpcode() == ISD::MSTORE;
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 140 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
179 setOperationAction(ISD::MSTORE, P, Custom); in initializeHVXLowering()
222 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
290 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
381 setOperationAction(ISD::MSTORE, BoolW, Custom); in initializeHVXLowering()
2178 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2983 uint64_t MemSize = (MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE) in SplitHvxMemOp()
3007 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
3030 if (MemOpc == ISD::MSTORE) { in SplitHvxMemOp()
3151 case ISD::MSTORE: in LowerHvxOperation()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 401 case ISD::MSTORE: return "masked_store"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 2821 case ISD::MSTORE: in SplitVectorOperand()
5795 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break; in WidenVectorOperand()
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| H A D | SelectionDAG.cpp | 822 case ISD::MSTORE: { in AddNodeIDCustom()
8927 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
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| H A D | LegalizeDAG.cpp | 1170 case ISD::MSTORE: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 1663 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 1809 case ISD::MSTORE: return visitMSTORE(N); in visit()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 654 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
743 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
873 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
942 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
4096 case ISD::MSTORE: in LowerOperation()
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| /openbsd/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 680 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 957 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
1322 setOperationAction(ISD::MSTORE, VT, Custom); in AArch64TargetLowering()
1770 setOperationAction(ISD::MSTORE, VT, Custom); in addTypeForStreamingSVE()
1892 setOperationAction(ISD::MSTORE, VT, Custom); in addTypeForFixedLengthSVE()
5985 case ISD::MSTORE: in LowerOperation()
19215 assert((N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::MSTORE) && in foldTruncStoreOfExt()
21463 case ISD::MSTORE: in PerformDAGCombine()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1459 case ISD::MSTORE: in SelectT2AddrModeImm7Offset()
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| H A D | ARMISelLowering.cpp | 266 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
340 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1521 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1727 setOperationAction(ISD::MSTORE, VT, Custom); in X86TargetLowering()
1894 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1901 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
2021 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2386 ISD::MSTORE, in X86TargetLowering()
33304 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG); in LowerOperation()
56439 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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