1 /* $OpenBSD: mtwreg.h,v 1.2 2022/07/27 06:41:04 hastings Exp $ */ 2 /* 3 * Copyright (c) 2007 Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2021 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define MTW_ASIC_VER 0x0000 20 #define MTW_CMB_CTRL 0x0020 21 #define MTW_EFUSE_CTRL 0x0024 22 #define MTW_EFUSE_DATA0 0x0028 23 #define MTW_EFUSE_DATA1 0x002c 24 #define MTW_EFUSE_DATA2 0x0030 25 #define MTW_EFUSE_DATA3 0x0034 26 #define MTW_OSC_CTRL 0x0038 27 #define MTW_COEX_CFG0 0x0040 28 #define MTW_PLL_CTRL 0x0050 29 #define MTW_LDO_CFG0 0x006c 30 #define MTW_LDO_CFG1 0x0070 31 #define MTW_WLAN_CTRL 0x0080 32 33 /* SCH/DMA registers */ 34 #define MTW_INT_STATUS 0x0200 35 #define RT2860_INT_MASK 0x0204 36 #define MTW_WPDMA_GLO_CFG 0x0208 37 #define RT2860_WPDMA_RST_IDX 0x020c 38 #define RT2860_DELAY_INT_CFG 0x0210 39 #define MTW_WMM_AIFSN_CFG 0x0214 40 #define MTW_WMM_CWMIN_CFG 0x0218 41 #define MTW_WMM_CWMAX_CFG 0x021c 42 #define MTW_WMM_TXOP0_CFG 0x0220 43 #define MTW_WMM_TXOP1_CFG 0x0224 44 #define RT2860_GPIO_CTRL 0x0228 45 #define RT2860_MCU_CMD_REG 0x022c 46 #define MTW_MCU_DMA_ADDR 0x0230 47 #define MTW_MCU_DMA_LEN 0x0234 48 #define MTW_USB_DMA_CFG 0x0238 49 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 50 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 51 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 52 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 53 #define MTW_TSO_CTRL 0x0250 54 #define MTW_HDR_TRANS_CTRL 0x0260 55 #define RT2860_RX_BASE_PTR 0x0290 56 #define RT2860_RX_MAX_CNT 0x0294 57 #define RT2860_RX_CALC_IDX 0x0298 58 #define RT2860_FS_DRX_IDX 0x029c 59 #define MTW_US_CYC_CNT 0x02a4 60 61 #define MTW_TX_RING_BASE 0x0300 62 #define MTW_RX_RING_BASE 0x03c0 63 64 /* Packet Buffer registers */ 65 #define MTW_SYS_CTRL 0x0400 66 #define MTW_PBF_CFG 0x0404 67 #define MTW_TX_MAX_PCNT 0x0408 68 #define MTW_RX_MAX_PCNT 0x040c 69 #define MTW_PBF_CTRL 0x0410 70 #define RT2860_BUF_CTRL 0x0410 71 #define RT2860_MCU_INT_STA 0x0414 72 #define RT2860_MCU_INT_ENA 0x0418 73 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 74 #define MTW_BCN_OFFSET0 0x041c 75 #define MTW_BCN_OFFSET1 0x0420 76 #define MTW_BCN_OFFSET2 0x0424 77 #define MTW_BCN_OFFSET3 0x0428 78 #define RT2860_RX0Q_IO 0x0424 79 #define MTW_RXQ_STA 0x0430 80 #define MTW_TXQ_STA 0x0434 81 #define MTW_TXRXQ_PCNT 0x0438 82 83 /* RF registers */ 84 #define MTW_RF_CSR 0x0500 85 #define MTW_RF_BYPASS0 0x0504 86 #define MTW_RF_BYPASS1 0x0508 87 #define MTW_RF_SETTING0 0x050C 88 #define MTW_RF_MISC 0x0518 89 #define MTW_RF_DATA_WR 0x0524 90 #define MTW_RF_CTRL 0x0528 91 #define MTW_RF_DATA_RD 0x052c 92 93 /* MCU registers */ 94 #define MTW_MCU_RESET_CTL 0x070c 95 #define MTW_MCU_INT_LEVEL 0x0718 96 #define MTW_MCU_COM_REG0 0x0730 97 #define MTW_MCU_COM_REG1 0x0734 98 #define MTW_MCU_COM_REG2 0x0738 99 #define MTW_MCU_COM_REG3 0x073c 100 #define MTW_FCE_PSE_CTRL 0x0800 101 #define MTW_FCE_PARAMETERS 0x0804 102 #define MTW_FCE_CSO 0x0808 103 #define MTW_FCE_L2_STUFF 0x080c 104 #define MTW_FCE_WLAN_FLOW_CTRL 0x0824 105 #define MTW_TX_CPU_FCE_BASE 0x09a0 106 #define MTW_TX_CPU_FCE_MAX_COUNT 0x09a4 107 #define MTW_MCU_FW_IDX 0x09a8 108 #define MTW_FCE_PDMA 0x09c4 109 #define MTW_FCE_SKIP_FS 0x0a6c 110 111 /* MAC registers */ 112 #define MTW_MAC_VER_ID 0x1000 113 #define MTW_MAC_SYS_CTRL 0x1004 114 #define MTW_MAC_ADDR_DW0 0x1008 115 #define MTW_MAC_ADDR_DW1 0x100c 116 #define MTW_MAC_BSSID_DW0 0x1010 117 #define MTW_MAC_BSSID_DW1 0x1014 118 #define MTW_MAX_LEN_CFG 0x1018 119 #define MTW_BBP_CSR 0x101c 120 #define MTW_LED_CFG 0x102c 121 #define MTW_AMPDU_MAX_LEN_20M1S 0x1030 122 #define MTW_AMPDU_MAX_LEN_20M2S 0x1034 123 #define MTW_AMPDU_MAX_LEN_40M1S 0x1038 124 #define MTW_AMPDU_MAX_LEN_40M2S 0x103c 125 #define MTW_AMPDU_MAX_LEN 0x1040 126 127 /* MAC Timing control registers */ 128 #define MTW_XIFS_TIME_CFG 0x1100 129 #define MTW_BKOFF_SLOT_CFG 0x1104 130 #define RT2860_NAV_TIME_CFG 0x1108 131 #define RT2860_CH_TIME_CFG 0x110c 132 #define RT2860_PBF_LIFE_TIMER 0x1110 133 #define MTW_BCN_TIME_CFG 0x1114 134 #define MTW_TBTT_SYNC_CFG 0x1118 135 #define MTW_TSF_TIMER_DW0 0x111c 136 #define MTW_TSF_TIMER_DW1 0x1120 137 #define RT2860_TBTT_TIMER 0x1124 138 #define MTW_INT_TIMER_CFG 0x1128 139 #define RT2860_INT_TIMER_EN 0x112c 140 #define RT2860_CH_IDLE_TIME 0x1130 141 142 /* MAC Power Save configuration registers */ 143 #define MTW_MAC_STATUS_REG 0x1200 144 #define MTW_PWR_PIN_CFG 0x1204 145 #define MTW_AUTO_WAKEUP_CFG 0x1208 146 #define MTW_AUX_CLK_CFG 0x120c 147 #define MTW_BBP_PA_MODE_CFG0 0x1214 148 #define MTW_BBP_PA_MODE_CFG1 0x1218 149 #define MTW_RF_PA_MODE_CFG0 0x121c 150 #define MTW_RF_PA_MODE_CFG1 0x1220 151 #define MTW_RF_PA_MODE_ADJ0 0x1228 152 #define MTW_RF_PA_MODE_ADJ1 0x122c 153 #define MTW_DACCLK_EN_DLY_CFG 0x1264 /* MT7612 */ 154 155 /* MAC TX configuration registers */ 156 #define MTW_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 157 #define MTW_EDCA_TID_AC_MAP 0x1310 158 #define MTW_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 159 #define MTW_TX_PIN_CFG 0x1328 160 #define MTW_TX_BAND_CFG 0x132c 161 #define MTW_TX_SW_CFG0 0x1330 162 #define MTW_TX_SW_CFG1 0x1334 163 #define MTW_TX_SW_CFG2 0x1338 164 #define RT2860_TXOP_THRES_CFG 0x133c 165 #define MTW_TXOP_CTRL_CFG 0x1340 166 #define MTW_TX_RTS_CFG 0x1344 167 #define MTW_TX_TIMEOUT_CFG 0x1348 168 #define MTW_TX_RETRY_CFG 0x134c 169 #define MTW_TX_LINK_CFG 0x1350 170 #define MTW_HT_FBK_CFG0 0x1354 171 #define MTW_HT_FBK_CFG1 0x1358 172 #define MTW_LG_FBK_CFG0 0x135c 173 #define MTW_LG_FBK_CFG1 0x1360 174 #define MTW_CCK_PROT_CFG 0x1364 175 #define MTW_OFDM_PROT_CFG 0x1368 176 #define MTW_MM20_PROT_CFG 0x136c 177 #define MTW_MM40_PROT_CFG 0x1370 178 #define MTW_GF20_PROT_CFG 0x1374 179 #define MTW_GF40_PROT_CFG 0x1378 180 #define RT2860_EXP_CTS_TIME 0x137c 181 #define MTW_EXP_ACK_TIME 0x1380 182 #define MTW_TX_PWR_CFG5 0x1384 183 #define MTW_TX_PWR_CFG6 0x1388 184 #define MTW_TX_PWR_EXT_CFG(ridx) (0x1390 + (ridx) * 4) 185 #define MTW_TX0_RF_GAIN_CORR 0x13a0 186 #define MTW_TX1_RF_GAIN_CORR 0x13a4 187 #define MTW_TX0_RF_GAIN_ATTEN 0x13a8 188 #define MTW_TX_ALC_CFG3 0x13ac 189 #define MTW_TX_ALC_CFG0 0x13b0 190 #define MTW_TX_ALC_CFG1 0x13b4 191 #define MTW_TX_ALC_CFG4 0x13c0 192 #define MTW_TX_ALC_VGA3 0x13c8 193 #define MTW_TX_PWR_CFG7 0x13d4 194 #define MTW_TX_PWR_CFG8 0x13d8 195 #define MTW_TX_PWR_CFG9 0x13dc 196 #define MTW_VHT20_PROT_CFG 0x13e0 197 #define MTW_VHT40_PROT_CFG 0x13e4 198 #define MTW_VHT80_PROT_CFG 0x13e8 199 #define MTW_TX_PIFS_CFG 0x13ec /* MT761X */ 200 201 /* MAC RX configuration registers */ 202 #define MTW_RX_FILTR_CFG 0x1400 203 #define MTW_AUTO_RSP_CFG 0x1404 204 #define MTW_LEGACY_BASIC_RATE 0x1408 205 #define MTW_HT_BASIC_RATE 0x140c 206 #define MTW_HT_CTRL_CFG 0x1410 207 #define RT2860_SIFS_COST_CFG 0x1414 208 #define RT2860_RX_PARSER_CFG 0x1418 209 210 /* MAC Security configuration registers */ 211 #define RT2860_TX_SEC_CNT0 0x1500 212 #define RT2860_RX_SEC_CNT0 0x1504 213 #define RT2860_CCMP_FC_MUTE 0x1508 214 #define MTW_PN_PAD_MODE 0x150c /* MT761X */ 215 216 /* MAC HCCA/PSMP configuration registers */ 217 #define MTW_TXOP_HLDR_ADDR0 0x1600 218 #define MTW_TXOP_HLDR_ADDR1 0x1604 219 #define MTW_TXOP_HLDR_ET 0x1608 220 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 221 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 222 #define RT2860_QOS_CFPOLL_QC 0x1614 223 #define MTW_PROT_AUTO_TX_CFG 0x1648 224 225 /* MAC Statistics Counters */ 226 #define MTW_RX_STA_CNT0 0x1700 227 #define MTW_RX_STA_CNT1 0x1704 228 #define MTW_RX_STA_CNT2 0x1708 229 #define MTW_TX_STA_CNT0 0x170c 230 #define MTW_TX_STA_CNT1 0x1710 231 #define MTW_TX_STA_CNT2 0x1714 232 #define MTW_TX_STAT_FIFO 0x1718 233 234 /* RX WCID search table */ 235 #define MTW_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 236 237 /* MT761x Baseband */ 238 #define MTW_BBP_CORE(x) (0x2000 + (x) * 4) 239 #define MTW_BBP_IBI(x) (0x2100 + (x) * 4) 240 #define MTW_BBP_AGC(x) (0x2300 + (x) * 4) 241 #define MTW_BBP_TXC(x) (0x2400 + (x) * 4) 242 #define MTW_BBP_RXC(x) (0x2500 + (x) * 4) 243 #define MTW_BBP_TXQ(x) (0x2600 + (x) * 4) 244 #define MTW_BBP_TXBE(x) (0x2700 + (x) * 4) 245 #define MTW_BBP_RXFE(x) (0x2800 + (x) * 4) 246 #define MTW_BBP_RXO(x) (0x2900 + (x) * 4) 247 #define MTW_BBP_DFS(x) (0x2a00 + (x) * 4) 248 #define MTW_BBP_TR(x) (0x2b00 + (x) * 4) 249 #define MTW_BBP_CAL(x) (0x2c00 + (x) * 4) 250 #define MTW_BBP_DSC(x) (0x2e00 + (x) * 4) 251 #define MTW_BBP_PFMU(x) (0x2f00 + (x) * 4) 252 253 #define MTW_SKEY_MODE_16_23 0x7008 254 #define MTW_SKEY_MODE_24_31 0x700c 255 #define MTW_H2M_MAILBOX 0x7010 256 257 /* Pair-wise key table */ 258 #define MTW_PKEY(wcid) (0x8000 + (wcid) * 32) 259 260 /* USB 3.0 DMA */ 261 #define MTW_USB_U3DMA_CFG 0x9018 262 263 /* IV/EIV table */ 264 #define MTW_IVEIV(wcid) (0xa000 + (wcid) * 8) 265 266 /* WCID attribute table */ 267 #define MTW_WCID_ATTR(wcid) (0xa800 + (wcid) * 4) 268 269 /* Shared Key Table */ 270 #define MTW_SKEY(vap, kidx) ((vap & 8) ? MTW_SKEY_1(vap, kidx) : \ 271 MTW_SKEY_0(vap, kidx)) 272 #define MTW_SKEY_0(vap, kidx) (0xac00 + (4 * (vap) + (kidx)) * 32) 273 #define MTW_SKEY_1(vap, kidx) (0xb400 + (4 * ((vap) & 7) + (kidx)) * 32) 274 275 /* Shared Key Mode */ 276 #define MTW_SKEY_MODE_0_7 0xb000 277 #define MTW_SKEY_MODE_8_15 0xb004 278 279 /* Shared Key Mode */ 280 #define MTW_SKEY_MODE_BASE 0xb000 281 282 /* Beacon */ 283 #define MTW_BCN_BASE 0xc000 284 285 /* possible flags for register CMB_CTRL 0x0020 */ 286 #define MTW_PLL_LD (1U << 23) 287 #define MTW_XTAL_RDY (1U << 22) 288 289 /* possible flags for register EFUSE_CTRL 0x0024 */ 290 #define MTW_SEL_EFUSE (1U << 31) 291 #define MTW_EFSROM_KICK (1U << 30) 292 #define MTW_EFSROM_AIN_MASK 0x03ff0000 293 #define MTW_EFSROM_AIN_SHIFT 16 294 #define MTW_EFSROM_MODE_MASK 0x000000c0 295 #define MTW_EFUSE_AOUT_MASK 0x0000003f 296 297 /* possible flags for register OSC_CTRL 0x0038 */ 298 #define MTW_OSC_EN (1U << 31) 299 #define MTW_OSC_CAL_REQ (1U << 30) 300 #define MTW_OSC_CLK_32K_VLD (1U << 29) 301 #define MTW_OSC_CAL_ACK (1U << 28) 302 #define MTW_OSC_CAL_CNT (0xfff << 16) 303 #define MTW_OSC_REF_CYCLE 0x1fff 304 305 /* possible flags for register WLAN_CTRL 0x0080 */ 306 #define MTW_GPIO_OUT_OE_ALL (0xff << 24) 307 #define MTW_GPIO_OUT_ALL (0xff << 16) 308 #define MTW_GPIO_IN_ALL (0xff << 8) 309 #define MTW_THERM_CKEN (1U << 9) 310 #define MTW_THERM_RST (1U << 8) 311 #define MTW_INV_TR_SW0 (1U << 6) 312 #define MTW_FRC_WL_ANT_SET (1U << 5) 313 #define MTW_PCIE_APP0_CLK_REQ (1U << 4) 314 #define MTW_WLAN_RESET (1U << 3) 315 #define MTW_WLAN_RESET_RF (1U << 2) 316 #define MTW_WLAN_CLK_EN (1U << 1) 317 #define MTW_WLAN_EN (1U << 0) 318 319 /* possible flags for registers INT_STATUS/INT_MASK 0x0200 */ 320 #define RT2860_TX_COHERENT (1 << 17) 321 #define RT2860_RX_COHERENT (1 << 16) 322 #define RT2860_MAC_INT_4 (1 << 15) 323 #define RT2860_MAC_INT_3 (1 << 14) 324 #define RT2860_MAC_INT_2 (1 << 13) 325 #define RT2860_MAC_INT_1 (1 << 12) 326 #define RT2860_MAC_INT_0 (1 << 11) 327 #define RT2860_TX_RX_COHERENT (1 << 10) 328 #define RT2860_MCU_CMD_INT (1 << 9) 329 #define RT2860_TX_DONE_INT5 (1 << 8) 330 #define RT2860_TX_DONE_INT4 (1 << 7) 331 #define RT2860_TX_DONE_INT3 (1 << 6) 332 #define RT2860_TX_DONE_INT2 (1 << 5) 333 #define RT2860_TX_DONE_INT1 (1 << 4) 334 #define RT2860_TX_DONE_INT0 (1 << 3) 335 #define RT2860_RX_DONE_INT (1 << 2) 336 #define RT2860_TX_DLY_INT (1 << 1) 337 #define RT2860_RX_DLY_INT (1 << 0) 338 339 /* possible flags for register WPDMA_GLO_CFG 0x0208 */ 340 #define MTW_HDR_SEG_LEN_SHIFT 8 341 #define MTW_BIG_ENDIAN (1 << 7) 342 #define MTW_TX_WB_DDONE (1 << 6) 343 #define MTW_WPDMA_BT_SIZE_SHIFT 4 344 #define MTW_WPDMA_BT_SIZE16 0 345 #define MTW_WPDMA_BT_SIZE32 1 346 #define MTW_WPDMA_BT_SIZE64 2 347 #define MTW_WPDMA_BT_SIZE128 3 348 #define MTW_RX_DMA_BUSY (1 << 3) 349 #define MTW_RX_DMA_EN (1 << 2) 350 #define MTW_TX_DMA_BUSY (1 << 1) 351 #define MTW_TX_DMA_EN (1 << 0) 352 353 /* possible flags for register DELAY_INT_CFG */ 354 #define RT2860_TXDLY_INT_EN (1U << 31) 355 #define RT2860_TXMAX_PINT_SHIFT 24 356 #define RT2860_TXMAX_PTIME_SHIFT 16 357 #define RT2860_RXDLY_INT_EN (1U << 15) 358 #define RT2860_RXMAX_PINT_SHIFT 8 359 #define RT2860_RXMAX_PTIME_SHIFT 0 360 361 /* possible flags for register GPIO_CTRL */ 362 #define RT2860_GPIO_D_SHIFT 8 363 #define RT2860_GPIO_O_SHIFT 0 364 365 /* possible flags for register MCU_DMA_ADDR 0x0230 */ 366 #define MTW_MCU_READY (1U << 0) 367 368 /* possible flags for register USB_DMA_CFG 0x0238 */ 369 #define MTW_USB_TX_BUSY (1U << 31) 370 #define MTW_USB_RX_BUSY (1U << 30) 371 #define MTW_USB_EPOUT_VLD_SHIFT 24 372 #define MTW_USB_RX_WL_DROP (1U << 25) 373 #define MTW_USB_TX_EN (1U << 23) 374 #define MTW_USB_RX_EN (1U << 22) 375 #define MTW_USB_RX_AGG_EN (1U << 21) 376 #define MTW_USB_TXOP_HALT (1U << 20) 377 #define MTW_USB_TX_CLEAR (1U << 19) 378 #define MTW_USB_PHY_WD_EN (1U << 16) 379 #define MTW_USB_PHY_MAN_RST (1U << 15) 380 #define MTW_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 381 #define MTW_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 382 383 /* possible flags for register US_CYC_CNT 0x02a4 */ 384 #define RT2860_TEST_EN (1 << 24) 385 #define RT2860_TEST_SEL_SHIFT 16 386 #define RT2860_BT_MODE_EN (1 << 8) 387 #define RT2860_US_CYC_CNT_SHIFT 0 388 389 /* possible flags for register PBF_CFG 0x0404 */ 390 #define MTW_PBF_CFG_RX_DROP (1 << 8) 391 #define MTW_PBF_CFG_RX0Q_EN (1 << 4) 392 #define MTW_PBF_CFG_TX3Q_EN (1 << 3) 393 #define MTW_PBF_CFG_TX2Q_EN (1 << 2) 394 #define MTW_PBF_CFG_TX1Q_EN (1 << 1) 395 #define MTW_PBF_CFG_TX0Q_EN (1 << 0) 396 397 /* possible flags for register BUF_CTRL 0x0410 */ 398 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 399 #define RT2860_NULL0_KICK (1 << 7) 400 #define RT2860_NULL1_KICK (1 << 6) 401 #define RT2860_BUF_RESET (1 << 5) 402 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 403 #define RT2860_READ_RX0Q (1 << 0) 404 405 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 406 #define RT2860_MCU_MAC_INT_8 (1 << 24) 407 #define RT2860_MCU_MAC_INT_7 (1 << 23) 408 #define RT2860_MCU_MAC_INT_6 (1 << 22) 409 #define RT2860_MCU_MAC_INT_4 (1 << 20) 410 #define RT2860_MCU_MAC_INT_3 (1 << 19) 411 #define RT2860_MCU_MAC_INT_2 (1 << 18) 412 #define RT2860_MCU_MAC_INT_1 (1 << 17) 413 #define RT2860_MCU_MAC_INT_0 (1 << 16) 414 #define RT2860_DTX0_INT (1 << 11) 415 #define RT2860_DTX1_INT (1 << 10) 416 #define RT2860_DTX2_INT (1 << 9) 417 #define RT2860_DRX0_INT (1 << 8) 418 #define RT2860_HCMD_INT (1 << 7) 419 #define RT2860_N0TX_INT (1 << 6) 420 #define RT2860_N1TX_INT (1 << 5) 421 #define RT2860_BCNTX_INT (1 << 4) 422 #define RT2860_MTX0_INT (1 << 3) 423 #define RT2860_MTX1_INT (1 << 2) 424 #define RT2860_MTX2_INT (1 << 1) 425 #define RT2860_MRX0_INT (1 << 0) 426 427 /* possible flags for register TXRXQ_PCNT 0x0438 */ 428 #define MTW_RX0Q_PCNT_MASK 0xff000000 429 #define MTW_TX2Q_PCNT_MASK 0x00ff0000 430 #define MTW_TX1Q_PCNT_MASK 0x0000ff00 431 #define MTW_TX0Q_PCNT_MASK 0x000000ff 432 433 /* possible flags for register RF_CSR_CFG 0x0500 */ 434 #define MTW_RF_CSR_KICK (1U << 31) 435 #define MTW_RF_CSR_WRITE (1U << 30) 436 #define MT7610_BANK_SHIFT 15 437 #define MT7601_BANK_SHIFT 14 438 439 /* possible flags for register FCE_L2_STUFF 0x080c */ 440 #define MTW_L2S_WR_MPDU_LEN_EN (1 << 4) 441 442 /* possible flag for register DEBUG_INDEX */ 443 #define RT5592_SEL_XTAL (1U << 31) 444 445 /* possible flags for register MAC_SYS_CTRL 0x1004 */ 446 #define MTW_RX_TS_EN (1 << 7) 447 #define MTW_WLAN_HALT_EN (1 << 6) 448 #define MTW_PBF_LOOP_EN (1 << 5) 449 #define MTW_CONT_TX_TEST (1 << 4) 450 #define MTW_MAC_RX_EN (1 << 3) 451 #define MTW_MAC_TX_EN (1 << 2) 452 #define MTW_BBP_HRST (1 << 1) 453 #define MTW_MAC_SRST (1 << 0) 454 455 /* possible flags for register MAC_BSSID_DW1 0x100c */ 456 #define RT2860_MULTI_BCN_NUM_SHIFT 18 457 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 458 459 /* possible flags for register MAX_LEN_CFG 0x1018 */ 460 #define RT2860_MIN_MPDU_LEN_SHIFT 16 461 #define RT2860_MAX_PSDU_LEN_SHIFT 12 462 #define RT2860_MAX_PSDU_LEN8K 0 463 #define RT2860_MAX_PSDU_LEN16K 1 464 #define RT2860_MAX_PSDU_LEN32K 2 465 #define RT2860_MAX_PSDU_LEN64K 3 466 #define RT2860_MAX_MPDU_LEN_SHIFT 0 467 468 /* possible flags for registers BBP_CSR_CFG 0x101c */ 469 #define MTW_BBP_CSR_KICK (1 << 17) 470 #define MTW_BBP_CSR_READ (1 << 16) 471 #define MTW_BBP_ADDR_SHIFT 8 472 #define MTW_BBP_DATA_SHIFT 0 473 474 /* possible flags for register LED_CFG */ 475 #define MTW_LED_MODE_ON 0 476 #define MTW_LED_MODE_DIM 1 477 #define MTW_LED_MODE_BLINK_TX 2 478 #define MTW_LED_MODE_SLOW_BLINK 3 479 480 /* possible flags for register XIFS_TIME_CFG 0x1100 */ 481 #define MTW_BB_RXEND_EN (1 << 29) 482 #define MTW_EIFS_TIME_SHIFT 20 483 #define MTW_OFDM_XIFS_TIME_SHIFT 16 484 #define MTW_OFDM_SIFS_TIME_SHIFT 8 485 #define MTW_CCK_SIFS_TIME_SHIFT 0 486 487 /* possible flags for register BKOFF_SLOT_CFG 0x1104 */ 488 #define MTW_CC_DELAY_TIME_SHIFT 8 489 #define MTW_SLOT_TIME 0 490 491 /* possible flags for register NAV_TIME_CFG */ 492 #define RT2860_NAV_UPD (1U << 31) 493 #define RT2860_NAV_UPD_VAL_SHIFT 16 494 #define RT2860_NAV_CLR_EN (1U << 15) 495 #define RT2860_NAV_TIMER_SHIFT 0 496 497 /* possible flags for register CH_TIME_CFG */ 498 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 499 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 500 #define RT2860_RX_AS_CH_BUSY (1 << 2) 501 #define RT2860_TX_AS_CH_BUSY (1 << 1) 502 #define RT2860_CH_STA_TIMER_EN (1 << 0) 503 504 /* possible values for register BCN_TIME_CFG 0x1114 */ 505 #define MTW_TSF_INS_COMP_SHIFT 24 506 #define MTW_BCN_TX_EN (1 << 20) 507 #define MTW_TBTT_TIMER_EN (1 << 19) 508 #define MTW_TSF_SYNC_MODE_SHIFT 17 509 #define MTW_TSF_SYNC_MODE_DIS 0 510 #define MTW_TSF_SYNC_MODE_STA 1 511 #define MTW_TSF_SYNC_MODE_IBSS 2 512 #define MTW_TSF_SYNC_MODE_HOSTAP 3 513 #define MTW_TSF_TIMER_EN (1 << 16) 514 #define MTW_BCN_INTVAL_SHIFT 0 515 516 /* possible flags for register TBTT_SYNC_CFG 0x1118 */ 517 #define RT2860_BCN_CWMIN_SHIFT 20 518 #define RT2860_BCN_AIFSN_SHIFT 16 519 #define RT2860_BCN_EXP_WIN_SHIFT 8 520 #define RT2860_TBTT_ADJUST_SHIFT 0 521 522 /* possible flags for register INT_TIMER_CFG 0x1128 */ 523 #define RT2860_GP_TIMER_SHIFT 16 524 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 525 526 /* possible flags for register INT_TIMER_EN */ 527 #define RT2860_GP_TIMER_EN (1 << 1) 528 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 529 530 /* possible flags for register MAC_STATUS_REG 0x1200 */ 531 #define MTW_RX_STATUS_BUSY (1 << 1) 532 #define MTW_TX_STATUS_BUSY (1 << 0) 533 534 /* possible flags for register PWR_PIN_CFG 0x1204 */ 535 #define RT2860_IO_ADDA_PD (1 << 3) 536 #define RT2860_IO_PLL_PD (1 << 2) 537 #define RT2860_IO_RA_PE (1 << 1) 538 #define RT2860_IO_RF_PE (1 << 0) 539 540 /* possible flags for register AUTO_WAKEUP_CFG 0x1208 */ 541 #define MTW_AUTO_WAKEUP_EN (1 << 15) 542 #define MTW_SLEEP_TBTT_NUM_SHIFT 8 543 #define MTW_WAKEUP_LEAD_TIME_SHIFT 0 544 545 /* possible flags for register TX_PIN_CFG 0x1328 */ 546 #define RT2860_TRSW_POL (1U << 19) 547 #define RT2860_TRSW_EN (1U << 18) 548 #define RT2860_RFTR_POL (1U << 17) 549 #define RT2860_RFTR_EN (1U << 16) 550 #define RT2860_LNA_PE_G1_POL (1U << 15) 551 #define RT2860_LNA_PE_A1_POL (1U << 14) 552 #define RT2860_LNA_PE_G0_POL (1U << 13) 553 #define RT2860_LNA_PE_A0_POL (1U << 12) 554 #define RT2860_LNA_PE_G1_EN (1U << 11) 555 #define RT2860_LNA_PE_A1_EN (1U << 10) 556 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 557 #define RT2860_LNA_PE_G0_EN (1U << 9) 558 #define RT2860_LNA_PE_A0_EN (1U << 8) 559 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 560 #define RT2860_PA_PE_G1_POL (1U << 7) 561 #define RT2860_PA_PE_A1_POL (1U << 6) 562 #define RT2860_PA_PE_G0_POL (1U << 5) 563 #define RT2860_PA_PE_A0_POL (1U << 4) 564 #define RT2860_PA_PE_G1_EN (1U << 3) 565 #define RT2860_PA_PE_A1_EN (1U << 2) 566 #define RT2860_PA_PE_G0_EN (1U << 1) 567 #define RT2860_PA_PE_A0_EN (1U << 0) 568 569 /* possible flags for register TX_BAND_CFG 0x132c */ 570 #define MTW_TX_BAND_SEL_2G (1 << 2) 571 #define MTW_TX_BAND_SEL_5G (1 << 1) 572 #define MTW_TX_BAND_UPPER_40M (1 << 0) 573 574 /* possible flags for register TX_SW_CFG0 0x1330 */ 575 #define RT2860_DLY_RFTR_EN_SHIFT 24 576 #define RT2860_DLY_TRSW_EN_SHIFT 16 577 #define RT2860_DLY_PAPE_EN_SHIFT 8 578 #define RT2860_DLY_TXPE_EN_SHIFT 0 579 580 /* possible flags for register TX_SW_CFG1 0x1334 */ 581 #define RT2860_DLY_RFTR_DIS_SHIFT 16 582 #define RT2860_DLY_TRSW_DIS_SHIFT 8 583 #define RT2860_DLY_PAPE_DIS SHIFT 0 584 585 /* possible flags for register TX_SW_CFG2 0x1338 */ 586 #define RT2860_DLY_LNA_EN_SHIFT 24 587 #define RT2860_DLY_LNA_DIS_SHIFT 16 588 #define RT2860_DLY_DAC_EN_SHIFT 8 589 #define RT2860_DLY_DAC_DIS_SHIFT 0 590 591 /* possible flags for register TXOP_THRES_CFG 0x133c */ 592 #define RT2860_TXOP_REM_THRES_SHIFT 24 593 #define RT2860_CF_END_THRES_SHIFT 16 594 #define RT2860_RDG_IN_THRES 8 595 #define RT2860_RDG_OUT_THRES 0 596 597 /* possible flags for register TXOP_CTRL_CFG 0x1340 */ 598 #define MTW_TXOP_ED_CCA_EN (1 << 20) 599 #define MTW_EXT_CW_MIN_SHIFT 16 600 #define MTW_EXT_CCA_DLY_SHIFT 8 601 #define MTW_EXT_CCA_EN (1 << 7) 602 #define MTW_LSIG_TXOP_EN (1 << 6) 603 #define MTW_TXOP_TRUN_EN_MIMOPS (1 << 4) 604 #define MTW_TXOP_TRUN_EN_TXOP (1 << 3) 605 #define MTW_TXOP_TRUN_EN_RATE (1 << 2) 606 #define MTW_TXOP_TRUN_EN_AC (1 << 1) 607 #define MTW_TXOP_TRUN_EN_TIMEOUT (1 << 0) 608 609 /* possible flags for register TX_RTS_CFG 0x1344 */ 610 #define MTW_RTS_FBK_EN (1 << 24) 611 #define MTW_RTS_THRES_SHIFT 8 612 #define MTW_RTS_RTY_LIMIT_SHIFT 0 613 614 /* possible flags for register TX_TIMEOUT_CFG 0x1348 */ 615 #define MTW_TXOP_TIMEOUT_SHIFT 16 616 #define MTW_RX_ACK_TIMEOUT_SHIFT 8 617 #define MTW_MPDU_LIFE_TIME_SHIFT 4 618 619 /* possible flags for register TX_RETRY_CFG 0x134c */ 620 #define MTW_TX_AUTOFB_EN (1 << 30) 621 #define MTW_AGG_RTY_MODE_TIMER (1 << 29) 622 #define MTW_NAG_RTY_MODE_TIMER (1 << 28) 623 #define MTW_LONG_RTY_THRES_SHIFT 16 624 #define MTW_LONG_RTY_LIMIT_SHIFT 8 625 #define MTW_SHORT_RTY_LIMIT_SHIFT 0 626 627 /* possible flags for register TX_LINK_CFG 0x1350 */ 628 #define MTW_REMOTE_MFS_SHIFT 24 629 #define MTW_REMOTE_MFB_SHIFT 16 630 #define MTW_TX_CFACK_EN (1 << 12) 631 #define MTW_TX_RDG_EN (1 << 11) 632 #define MTW_TX_MRQ_EN (1 << 10) 633 #define MTW_REMOTE_UMFS_EN (1 << 9) 634 #define MTW_TX_MFB_EN (1 << 8) 635 #define MTW_REMOTE_MFB_LT_SHIFT 0 636 637 /* possible flags for registers *_PROT_CFG */ 638 #define RT2860_RTSTH_EN (1 << 26) 639 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 640 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 641 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 642 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 643 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 644 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 645 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 646 #define RT2860_PROT_NAV_SHORT (1 << 18) 647 #define RT2860_PROT_NAV_LONG (2 << 18) 648 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 649 #define RT2860_PROT_CTRL_CTS (2 << 16) 650 651 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 652 #define RT2860_EXP_OFDM_TIME_SHIFT 16 653 #define RT2860_EXP_CCK_TIME_SHIFT 0 654 655 /* possible flags for register RX_FILTR_CFG 0x1400 */ 656 #define MTW_DROP_CTRL_RSV (1 << 16) 657 #define MTW_DROP_BAR (1 << 15) 658 #define MTW_DROP_BA (1 << 14) 659 #define MTW_DROP_PSPOLL (1 << 13) 660 #define MTW_DROP_RTS (1 << 12) 661 #define MTW_DROP_CTS (1 << 11) 662 #define MTW_DROP_ACK (1 << 10) 663 #define MTW_DROP_CFEND (1 << 9) 664 #define MTW_DROP_CFACK (1 << 8) 665 #define MTW_DROP_DUPL (1 << 7) 666 #define MTW_DROP_BC (1 << 6) 667 #define MTW_DROP_MC (1 << 5) 668 #define MTW_DROP_VER_ERR (1 << 4) 669 #define MTW_DROP_NOT_MYBSS (1 << 3) 670 #define MTW_DROP_UC_NOME (1 << 2) 671 #define MTW_DROP_PHY_ERR (1 << 1) 672 #define MTW_DROP_CRC_ERR (1 << 0) 673 674 /* possible flags for register AUTO_RSP_CFG 0x1404 */ 675 #define MTW_CTRL_PWR_BIT (1 << 7) 676 #define MTW_BAC_ACK_POLICY (1 << 6) 677 #define MTW_CCK_SHORT_EN (1 << 4) 678 #define MTW_CTS_40M_REF_EN (1 << 3) 679 #define MTW_CTS_40M_MODE_EN (1 << 2) 680 #define MTW_BAC_ACKPOLICY_EN (1 << 1) 681 #define MTW_AUTO_RSP_EN (1 << 0) 682 683 /* possible flags for register SIFS_COST_CFG */ 684 #define RT2860_OFDM_SIFS_COST_SHIFT 8 685 #define RT2860_CCK_SIFS_COST_SHIFT 0 686 687 /* possible flags for register TXOP_HLDR_ET 0x1608 */ 688 #define MTW_TXOP_ETM1_EN (1 << 25) 689 #define MTW_TXOP_ETM0_EN (1 << 24) 690 #define MTW_TXOP_ETM_THRES_SHIFT 16 691 #define MTW_TXOP_ETO_EN (1 << 8) 692 #define MTW_TXOP_ETO_THRES_SHIFT 1 693 #define MTW_PER_RX_RST_EN (1 << 0) 694 695 /* possible flags for register TX_STAT_FIFO 0x1718 */ 696 #define MTW_TXQ_MCS_SHIFT 16 697 #define MTW_TXQ_WCID_SHIFT 8 698 #define MTW_TXQ_ACKREQ (1 << 7) 699 #define MTW_TXQ_AGG (1 << 6) 700 #define MTW_TXQ_OK (1 << 5) 701 #define MTW_TXQ_PID_SHIFT 1 702 #define MTW_TXQ_VLD (1 << 0) 703 704 /* possible flags for register TX_STAT_FIFO_EXT 0x1798 */ 705 #define MTW_TXQ_PKTID_SHIFT 8 706 #define MTW_TXQ_RETRY_SHIFT 0 707 708 /* possible flags for register WCID_ATTR 0xa800 */ 709 #define MTW_MODE_NOSEC 0 710 #define MTW_MODE_WEP40 1 711 #define MTW_MODE_WEP104 2 712 #define MTW_MODE_TKIP 3 713 #define MTW_MODE_AES_CCMP 4 714 #define MTW_MODE_CKIP40 5 715 #define MTW_MODE_CKIP104 6 716 #define MTW_MODE_CKIP128 7 717 #define MTW_RX_PKEY_EN (1 << 0) 718 719 /* possible flags for MT7601 BBP register 47 */ 720 #define MT7601_R47_MASK 0x07 721 #define MT7601_R47_TSSI (0 << 0) 722 #define MT7601_R47_PKT (1 << 0) 723 #define MT7601_R47_TXRATE (1 << 1) 724 #define MT7601_R47_TEMP (1 << 2) 725 726 #define MTW_RXQ_WLAN 0 727 #define MTW_RXQ_MCU 1 728 #define MTW_TXQ_MCU 5 729 730 enum mtw_phy_mode { 731 MTW_PHY_CCK, 732 MTW_PHY_OFDM, 733 MTW_PHY_HT, 734 MTW_PHY_HT_GF, 735 MTW_PHY_VHT, 736 }; 737 738 /* RT2860 TX descriptor */ 739 struct rt2860_txd { 740 uint32_t sdp0; /* Segment Data Pointer 0 */ 741 uint16_t sdl1; /* Segment Data Length 1 */ 742 #define RT2860_TX_BURST (1 << 15) 743 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 744 745 uint16_t sdl0; /* Segment Data Length 0 */ 746 #define RT2860_TX_DDONE (1 << 15) 747 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 748 749 uint32_t sdp1; /* Segment Data Pointer 1 */ 750 uint8_t reserved[3]; 751 uint8_t flags; 752 #define RT2860_TX_QSEL_SHIFT 1 753 #define RT2860_TX_QSEL_MGMT (0 << 1) 754 #define RT2860_TX_QSEL_HCCA (1 << 1) 755 #define RT2860_TX_QSEL_EDCA (2 << 1) 756 #define RT2860_TX_WIV (1 << 0) 757 } __packed; 758 759 /* TX descriptor */ 760 struct mtw_txd { 761 uint16_t len; 762 uint16_t flags; 763 #define MTW_TXD_CMD (1 << 14) 764 #define MTW_TXD_DATA (0 << 14) 765 #define MTW_TXD_MCU (2 << 11) 766 #define MTW_TXD_WLAN (0 << 11) 767 #define MTW_TXD_QSEL_EDCA (2 << 9) 768 #define MTW_TXD_QSEL_HCCA (1 << 9) 769 #define MTW_TXD_QSEL_MGMT (0 << 9) 770 #define MTW_TXD_WIV (1 << 8) 771 #define MTW_TXD_CMD_SHIFT 4 772 #define MTW_TXD_80211 (1 << 3) 773 } __packed; 774 775 /* TX Wireless Information */ 776 struct mtw_txwi { 777 uint8_t flags; 778 #define MTW_TX_MPDU_DSITY_SHIFT 5 779 #define MTW_TX_AMPDU (1 << 4) 780 #define MTW_TX_TS (1 << 3) 781 #define MTW_TX_CFACK (1 << 2) 782 #define MTW_TX_MMPS (1 << 1) 783 #define MTW_TX_FRAG (1 << 0) 784 785 uint8_t txop; 786 #define MTW_TX_TXOP_HT 0 787 #define MTW_TX_TXOP_PIFS 1 788 #define MTW_TX_TXOP_SIFS 2 789 #define MTW_TX_TXOP_BACKOFF 3 790 791 uint16_t phy; 792 #define MT7650_PHY_MODE 0xe000 793 #define MT7601_PHY_MODE 0xc000 794 #define MT7601_PHY_SHIFT 14 795 #define MT7650_PHY_SHIFT 13 796 #define MT7650_PHY_SGI (1 << 9) 797 #define MT7601_PHY_SGI (1 << 8) 798 #define MTW_PHY_BW20 (0 << 7) 799 #define MTW_PHY_BW40 (1 << 7) 800 #define MTW_PHY_BW80 (2 << 7) 801 #define MTW_PHY_BW160 (3 << 7) 802 #define MTW_PHY_LDPC (1 << 6) 803 #define MTW_PHY_MCS 0x3f 804 #define MTW_PHY_SHPRE (1 << 3) 805 806 uint8_t xflags; 807 #define MTW_TX_BAWINSIZE_SHIFT 2 808 #define MTW_TX_NSEQ (1 << 1) 809 #define MTW_TX_ACK (1 << 0) 810 811 uint8_t wcid; /* Wireless Client ID */ 812 uint16_t len; 813 #define MTW_TX_PID_SHIFT 12 814 815 uint32_t iv; 816 uint32_t eiv; 817 uint32_t reserved1; 818 } __packed; 819 820 /* RT2860 RX descriptor */ 821 struct rt2860_rxd { 822 uint32_t sdp0; 823 uint16_t sdl1; /* unused */ 824 uint16_t sdl0; 825 #define MTW_RX_DDONE (1 << 15) 826 #define MTW_RX_LS0 (1 << 14) 827 828 uint32_t sdp1; /* unused */ 829 uint32_t flags; 830 #define MTW_RX_DEC (1 << 16) 831 #define MTW_RX_AMPDU (1 << 15) 832 #define MTW_RX_L2PAD (1 << 14) 833 #define MTW_RX_RSSI (1 << 13) 834 #define MTW_RX_HTC (1 << 12) 835 #define MTW_RX_AMSDU (1 << 11) 836 #define MTW_RX_MICERR (1 << 10) 837 #define MTW_RX_ICVERR (1 << 9) 838 #define MTW_RX_CRCERR (1 << 8) 839 #define MTW_RX_MYBSS (1 << 7) 840 #define MTW_RX_BC (1 << 6) 841 #define MTW_RX_MC (1 << 5) 842 #define MTW_RX_UC2ME (1 << 4) 843 #define MTW_RX_FRAG (1 << 3) 844 #define MTW_RX_NULL (1 << 2) 845 #define MTW_RX_DATA (1 << 1) 846 #define MTW_RX_BA (1 << 0) 847 } __packed; 848 849 /* RX descriptor */ 850 struct mtw_rxd { 851 uint16_t len; 852 #define MTW_RXD_SELF_GEN (1 << 15) 853 #define MTW_RXD_LEN 0x3fff 854 855 uint16_t flags; 856 } __packed; 857 858 /* RX Wireless Information */ 859 struct mtw_rxwi { 860 uint32_t flags; 861 uint8_t wcid; 862 uint8_t keyidx; 863 #define MTW_RX_UDF_SHIFT 5 864 #define MTW_RX_BSS_IDX_SHIFT 2 865 866 uint16_t len; 867 #define MTW_RX_TID_SHIFT 12 868 869 uint16_t seq; 870 uint16_t phy; 871 uint8_t rssi[4]; 872 uint32_t reserved1; 873 uint32_t reserved2; 874 uint32_t reserved3; 875 } __packed __aligned(4); 876 877 /* MCU Command */ 878 struct mtw_mcu_cmd_8 { 879 uint32_t func; 880 uint32_t val; 881 } __packed __aligned(4); 882 883 struct mtw_mcu_cmd_16 { 884 uint32_t r1; 885 uint32_t r2; 886 uint32_t r3; 887 uint32_t r4; 888 } __packed __aligned(4); 889 890 #define MTW_DMA_PAD 4 891 892 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 893 #define MTW_TXWI_DMASZ \ 894 (sizeof (struct mtw_txwi) + \ 895 sizeof (struct ieee80211_htframe) + \ 896 sizeof (uint16_t)) 897 898 #define MT7601_RF_7601 0x7601 /* 1T1R */ 899 #define MT7610_RF_7610 0x7610 /* 1T1R */ 900 #define MT7612_RF_7612 0x7612 /* 2T2R */ 901 902 #define MTW_CONFIG_NO 1 903 904 /* USB vendor request */ 905 #define MTW_RESET 0x1 906 #define MTW_WRITE_2 0x2 907 #define MTW_WRITE_REGION_1 0x6 908 #define MTW_READ_REGION_1 0x7 909 #define MTW_EEPROM_READ 0x9 910 #define MTW_WRITE_CFG 0x46 911 #define MTW_READ_CFG 0x47 912 913 /* eFUSE ROM */ 914 #define MTW_EEPROM_CHIPID 0x00 915 #define MTW_EEPROM_VERSION 0x01 916 #define MTW_EEPROM_MAC01 0x02 917 #define MTW_EEPROM_MAC23 0x03 918 #define MTW_EEPROM_MAC45 0x04 919 #define MTW_EEPROM_ANTENNA 0x1a 920 #define MTW_EEPROM_CONFIG 0x1b 921 #define MTW_EEPROM_COUNTRY 0x1c 922 #define MTW_EEPROM_FREQ_OFFSET 0x1d 923 #define MTW_EEPROM_LED1 0x1e 924 #define MTW_EEPROM_LED2 0x1f 925 #define MTW_EEPROM_LED3 0x20 926 #define MTW_EEPROM_LNA 0x22 927 #define MTW_EEPROM_RSSI1_2GHZ 0x23 928 #define MTW_EEPROM_RSSI2_2GHZ 0x24 929 #define MTW_EEPROM_RSSI1_5GHZ 0x25 930 #define MTW_EEPROM_RSSI2_5GHZ 0x26 931 #define MTW_EEPROM_DELTAPWR 0x28 932 #define MTW_EEPROM_PWR2GHZ_BASE1 0x29 933 #define MTW_EEPROM_PWR2GHZ_BASE2 0x30 934 #define MTW_EEPROM_TSSI1_2GHZ 0x37 935 #define MTW_EEPROM_TSSI2_2GHZ 0x38 936 #define MTW_EEPROM_TSSI3_2GHZ 0x39 937 #define MTW_EEPROM_TSSI4_2GHZ 0x3a 938 #define MTW_EEPROM_TSSI5_2GHZ 0x3b 939 #define MTW_EEPROM_PWR5GHZ_BASE1 0x3c 940 #define MTW_NIC_CONF2 0x42 941 #define MTW_EEPROM_PWR5GHZ_BASE2 0x53 942 #define MTW_TXPWR_EXT_PA_5G 0x54 943 #define MTW_TXPWR_START_2G_0 0x56 944 #define MTW_TXPWR_START_2G_1 0x5c 945 #define MTW_TXPWR_START_5G_0 0x62 946 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 947 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 948 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 949 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 950 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 951 #define MTW_TX_TSSI_SLOPE 0x6e 952 #define MTW_EEPROM_RPWR 0x6f 953 954 #define MTW_RIDX_CCK1 0 955 #define MTW_RIDX_CCK11 3 956 #define MTW_RIDX_OFDM6 4 957 #define MTW_RIDX_MAX 11 958 static const struct rt2860_rate { 959 uint8_t rate; 960 uint8_t mcs; 961 enum ieee80211_phytype phy; 962 uint8_t ctl_ridx; 963 uint16_t sp_ack_dur; 964 uint16_t lp_ack_dur; 965 } rt2860_rates[] = { 966 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 967 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 968 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 969 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 970 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 971 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 972 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 973 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 974 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 975 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 976 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 977 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 978 }; 979 980 #define MT7601_RF_CHAN \ 981 { 1, 0x99, 0x99, 0x09, 0x50 }, \ 982 { 2, 0x46, 0x44, 0x0a, 0x50 }, \ 983 { 3, 0xec, 0xee, 0x0a, 0x50 }, \ 984 { 4, 0x99, 0x99, 0x0b, 0x50 }, \ 985 { 5, 0x46, 0x44, 0x08, 0x51 }, \ 986 { 6, 0xec, 0xee, 0x08, 0x51 }, \ 987 { 7, 0x99, 0x99, 0x09, 0x51 }, \ 988 { 8, 0x46, 0x44, 0x0a, 0x51 }, \ 989 { 9, 0xec, 0xee, 0x0a, 0x51 }, \ 990 { 10, 0x99, 0x99, 0x0b, 0x51 }, \ 991 { 11, 0x46, 0x44, 0x08, 0x52 }, \ 992 { 12, 0xec, 0xee, 0x08, 0x52 }, \ 993 { 13, 0x99, 0x99, 0x09, 0x52 }, \ 994 { 14, 0x33, 0x33, 0x0b, 0x52 } 995 996 /* 997 * Default values for MAC registers. 998 */ 999 #define MT7601_DEF_MAC \ 1000 { MTW_BCN_OFFSET0, 0x18100800 }, \ 1001 { MTW_BCN_OFFSET1, 0x38302820 }, \ 1002 { MTW_BCN_OFFSET2, 0x58504840 }, \ 1003 { MTW_BCN_OFFSET3, 0x78706860 }, \ 1004 { MTW_MAC_SYS_CTRL, 0x0000000c }, \ 1005 { MTW_MAX_LEN_CFG, 0x000a3fff }, \ 1006 { MTW_AMPDU_MAX_LEN_20M1S, 0x77777777 }, \ 1007 { MTW_AMPDU_MAX_LEN_20M2S, 0x77777777 }, \ 1008 { MTW_AMPDU_MAX_LEN_40M1S, 0x77777777 }, \ 1009 { MTW_AMPDU_MAX_LEN_40M2S, 0x77777777 }, \ 1010 { MTW_XIFS_TIME_CFG, 0x33a41010 }, \ 1011 { MTW_BKOFF_SLOT_CFG, 0x00000209 }, \ 1012 { MTW_TBTT_SYNC_CFG, 0x00422010 }, \ 1013 { MTW_INT_TIMER_CFG, 0x00000000 }, \ 1014 { MTW_PWR_PIN_CFG, 0x00000000 }, \ 1015 { MTW_AUTO_WAKEUP_CFG, 0x00000014 }, \ 1016 { MTW_EDCA_AC_CFG(0), 0x000a4360 }, \ 1017 { MTW_EDCA_AC_CFG(1), 0x000a4700 }, \ 1018 { MTW_EDCA_AC_CFG(2), 0x00043338 }, \ 1019 { MTW_EDCA_AC_CFG(3), 0x0003222f }, \ 1020 { MTW_TX_PIN_CFG, 0x33150f0f }, \ 1021 { MTW_TX_BAND_CFG, 0x00000005 }, \ 1022 { MTW_TX_SW_CFG0, 0x00000402 }, \ 1023 { MTW_TX_SW_CFG1, 0x00000000 }, \ 1024 { MTW_TX_SW_CFG2, 0x00000000 }, \ 1025 { MTW_TXOP_CTRL_CFG, 0x0000583f }, \ 1026 { MTW_TX_RTS_CFG, 0x01100020 }, \ 1027 { MTW_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1028 { MTW_TX_RETRY_CFG, 0x47d01f0f }, \ 1029 { MTW_TX_LINK_CFG, 0x007f1820 }, \ 1030 { MTW_HT_FBK_CFG1, 0xedcba980 }, \ 1031 { MTW_CCK_PROT_CFG, 0x07f40000 }, \ 1032 { MTW_OFDM_PROT_CFG, 0x07f60000 }, \ 1033 { MTW_MM20_PROT_CFG, 0x01750003 }, \ 1034 { MTW_MM40_PROT_CFG, 0x03f50003 }, \ 1035 { MTW_GF20_PROT_CFG, 0x01750003 }, \ 1036 { MTW_GF40_PROT_CFG, 0x03f50003 }, \ 1037 { MTW_EXP_ACK_TIME, 0x002400ca }, \ 1038 { MTW_TX_PWR_CFG5, 0x00000000 }, \ 1039 { MTW_TX_PWR_CFG6, 0x01010101 }, \ 1040 { MTW_TX0_RF_GAIN_CORR, 0x003b0005 }, \ 1041 { MTW_TX1_RF_GAIN_CORR, 0x00000000 }, \ 1042 { MTW_TX0_RF_GAIN_ATTEN, 0x00006969 }, \ 1043 { MTW_TX_ALC_CFG3, 0x6c6c6c6c }, \ 1044 { MTW_TX_ALC_CFG0, 0x2f2f0005 }, \ 1045 { MTW_TX_ALC_CFG4, 0x00000400 }, \ 1046 { MTW_TX_ALC_VGA3, 0x00060006 }, \ 1047 { MTW_RX_FILTR_CFG, 0x00015f97 }, \ 1048 { MTW_AUTO_RSP_CFG, 0x00000003 }, \ 1049 { MTW_LEGACY_BASIC_RATE, 0x0000015f }, \ 1050 { MTW_HT_BASIC_RATE, 0x00008003 }, \ 1051 { MTW_RX_MAX_PCNT, 0x0000009f }, \ 1052 { MTW_WPDMA_GLO_CFG, 0x00000030 }, \ 1053 { MTW_WMM_AIFSN_CFG, 0x00002273 }, \ 1054 { MTW_WMM_CWMIN_CFG, 0x00002344 }, \ 1055 { MTW_WMM_CWMAX_CFG, 0x000034aa }, \ 1056 { MTW_TSO_CTRL, 0x00000000 }, \ 1057 { MTW_SYS_CTRL, 0x00080c00 }, \ 1058 { MTW_FCE_PSE_CTRL, 0x00000001 }, \ 1059 { MTW_AUX_CLK_CFG, 0x00000000 }, \ 1060 { MTW_BBP_PA_MODE_CFG0, 0x010055ff }, \ 1061 { MTW_BBP_PA_MODE_CFG1, 0x00550055 }, \ 1062 { MTW_RF_PA_MODE_CFG0, 0x010055ff }, \ 1063 { MTW_RF_PA_MODE_CFG1, 0x00550055 }, \ 1064 { 0x0a38, 0x00000000 }, \ 1065 { MTW_BBP_CSR, 0x00000000 }, \ 1066 { MTW_PBF_CFG, 0x7f723c1f } 1067 1068 /* 1069 * Default values for Baseband registers 1070 */ 1071 #define MT7601_DEF_BBP \ 1072 { 1, 0x04 }, \ 1073 { 4, 0x40 }, \ 1074 { 20, 0x06 }, \ 1075 { 31, 0x08 }, \ 1076 { 178, 0xff }, \ 1077 { 66, 0x14 }, \ 1078 { 68, 0x8b }, \ 1079 { 69, 0x12 }, \ 1080 { 70, 0x09 }, \ 1081 { 73, 0x11 }, \ 1082 { 75, 0x60 }, \ 1083 { 76, 0x44 }, \ 1084 { 84, 0x9a }, \ 1085 { 86, 0x38 }, \ 1086 { 91, 0x07 }, \ 1087 { 92, 0x02 }, \ 1088 { 99, 0x50 }, \ 1089 { 101, 0x00 }, \ 1090 { 103, 0xc0 }, \ 1091 { 104, 0x92 }, \ 1092 { 105, 0x3c }, \ 1093 { 106, 0x03 }, \ 1094 { 128, 0x12 }, \ 1095 { 142, 0x04 }, \ 1096 { 143, 0x37 }, \ 1097 { 142, 0x03 }, \ 1098 { 143, 0x99 }, \ 1099 { 160, 0xeb }, \ 1100 { 161, 0xc4 }, \ 1101 { 162, 0x77 }, \ 1102 { 163, 0xf9 }, \ 1103 { 164, 0x88 }, \ 1104 { 165, 0x80 }, \ 1105 { 166, 0xff }, \ 1106 { 167, 0xe4 }, \ 1107 { 195, 0x00 }, \ 1108 { 196, 0x00 }, \ 1109 { 195, 0x01 }, \ 1110 { 196, 0x04 }, \ 1111 { 195, 0x02 }, \ 1112 { 196, 0x20 }, \ 1113 { 195, 0x03 }, \ 1114 { 196, 0x0a }, \ 1115 { 195, 0x06 }, \ 1116 { 196, 0x16 }, \ 1117 { 195, 0x07 }, \ 1118 { 196, 0x05 }, \ 1119 { 195, 0x08 }, \ 1120 { 196, 0x37 }, \ 1121 { 195, 0x0a }, \ 1122 { 196, 0x15 }, \ 1123 { 195, 0x0b }, \ 1124 { 196, 0x17 }, \ 1125 { 195, 0x0c }, \ 1126 { 196, 0x06 }, \ 1127 { 195, 0x0d }, \ 1128 { 196, 0x09 }, \ 1129 { 195, 0x0e }, \ 1130 { 196, 0x05 }, \ 1131 { 195, 0x0f }, \ 1132 { 196, 0x09 }, \ 1133 { 195, 0x10 }, \ 1134 { 196, 0x20 }, \ 1135 { 195, 0x20 }, \ 1136 { 196, 0x17 }, \ 1137 { 195, 0x21 }, \ 1138 { 196, 0x06 }, \ 1139 { 195, 0x22 }, \ 1140 { 196, 0x09 }, \ 1141 { 195, 0x23 }, \ 1142 { 196, 0x17 }, \ 1143 { 195, 0x24 }, \ 1144 { 196, 0x06 }, \ 1145 { 195, 0x25 }, \ 1146 { 196, 0x09 }, \ 1147 { 195, 0x26 }, \ 1148 { 196, 0x17 }, \ 1149 { 195, 0x27 }, \ 1150 { 196, 0x06 }, \ 1151 { 195, 0x28 }, \ 1152 { 196, 0x09 }, \ 1153 { 195, 0x29 }, \ 1154 { 196, 0x05 }, \ 1155 { 195, 0x2a }, \ 1156 { 196, 0x09 }, \ 1157 { 195, 0x80 }, \ 1158 { 196, 0x8b }, \ 1159 { 195, 0x81 }, \ 1160 { 196, 0x12 }, \ 1161 { 195, 0x82 }, \ 1162 { 196, 0x09 }, \ 1163 { 195, 0x83 }, \ 1164 { 196, 0x17 }, \ 1165 { 195, 0x84 }, \ 1166 { 196, 0x11 }, \ 1167 { 195, 0x85 }, \ 1168 { 196, 0x00 }, \ 1169 { 195, 0x86 }, \ 1170 { 196, 0x00 }, \ 1171 { 195, 0x87 }, \ 1172 { 196, 0x18 }, \ 1173 { 195, 0x88 }, \ 1174 { 196, 0x60 }, \ 1175 { 195, 0x89 }, \ 1176 { 196, 0x44 }, \ 1177 { 195, 0x8a }, \ 1178 { 196, 0x8b }, \ 1179 { 195, 0x8b }, \ 1180 { 196, 0x8b }, \ 1181 { 195, 0x8c }, \ 1182 { 196, 0x8b }, \ 1183 { 195, 0x8d }, \ 1184 { 196, 0x8b }, \ 1185 { 195, 0x8e }, \ 1186 { 196, 0x09 }, \ 1187 { 195, 0x8f }, \ 1188 { 196, 0x09 }, \ 1189 { 195, 0x90 }, \ 1190 { 196, 0x09 }, \ 1191 { 195, 0x91 }, \ 1192 { 196, 0x09 }, \ 1193 { 195, 0x92 }, \ 1194 { 196, 0x11 }, \ 1195 { 195, 0x93 }, \ 1196 { 196, 0x11 }, \ 1197 { 195, 0x94 }, \ 1198 { 196, 0x11 }, \ 1199 { 195, 0x95 }, \ 1200 { 196, 0x11 }, \ 1201 { 47, 0x80 }, \ 1202 { 60, 0x80 }, \ 1203 { 150, 0xd2 }, \ 1204 { 151, 0x32 }, \ 1205 { 152, 0x23 }, \ 1206 { 153, 0x41 }, \ 1207 { 154, 0x00 }, \ 1208 { 155, 0x4f }, \ 1209 { 253, 0x7e }, \ 1210 { 195, 0x30 }, \ 1211 { 196, 0x32 }, \ 1212 { 195, 0x31 }, \ 1213 { 196, 0x23 }, \ 1214 { 195, 0x32 }, \ 1215 { 196, 0x45 }, \ 1216 { 195, 0x35 }, \ 1217 { 196, 0x4a }, \ 1218 { 195, 0x36 }, \ 1219 { 196, 0x5a }, \ 1220 { 195, 0x37 }, \ 1221 { 196, 0x5a } 1222 1223 /* 1224 * Default values for RF registers 1225 */ 1226 #define MT7601_BANK0_RF \ 1227 { 0, 0x02 }, \ 1228 { 1, 0x01 }, \ 1229 { 2, 0x11 }, \ 1230 { 3, 0xff }, \ 1231 { 4, 0x0a }, \ 1232 { 5, 0x20 }, \ 1233 { 6, 0x00 }, \ 1234 { 7, 0x00 }, \ 1235 { 8, 0x00 }, \ 1236 { 9, 0x00 }, \ 1237 { 10, 0x00 }, \ 1238 { 11, 0x21 }, \ 1239 { 13, 0x00 }, \ 1240 { 14, 0x7c }, \ 1241 { 15, 0x22 }, \ 1242 { 16, 0x80 }, \ 1243 { 17, 0x99 }, \ 1244 { 18, 0x99 }, \ 1245 { 19, 0x09 }, \ 1246 { 20, 0x50 }, \ 1247 { 21, 0xb0 }, \ 1248 { 22, 0x00 }, \ 1249 { 23, 0xc5 }, \ 1250 { 24, 0xfc }, \ 1251 { 25, 0x40 }, \ 1252 { 26, 0x4d }, \ 1253 { 27, 0x02 }, \ 1254 { 28, 0x72 }, \ 1255 { 29, 0x01 }, \ 1256 { 30, 0x00 }, \ 1257 { 31, 0x00 }, \ 1258 { 32, 0x00 }, \ 1259 { 33, 0x00 }, \ 1260 { 34, 0x23 }, \ 1261 { 35, 0x01 }, \ 1262 { 36, 0x00 }, \ 1263 { 37, 0x00 }, \ 1264 { 38, 0x00 }, \ 1265 { 39, 0x20 }, \ 1266 { 40, 0x00 }, \ 1267 { 41, 0xd0 }, \ 1268 { 42, 0x1b }, \ 1269 { 43, 0x02 }, \ 1270 { 44, 0x00 } 1271 1272 #define MT7601_BANK4_RF \ 1273 { 0, 0x01 }, \ 1274 { 1, 0x00 }, \ 1275 { 2, 0x00 }, \ 1276 { 3, 0x00 }, \ 1277 { 4, 0x00 }, \ 1278 { 5, 0x08 }, \ 1279 { 6, 0x00 }, \ 1280 { 7, 0x5b }, \ 1281 { 8, 0x52 }, \ 1282 { 9, 0xb6 }, \ 1283 { 10, 0x57 }, \ 1284 { 11, 0x33 }, \ 1285 { 12, 0x22 }, \ 1286 { 13, 0x3d }, \ 1287 { 14, 0x3e }, \ 1288 { 15, 0x13 }, \ 1289 { 16, 0x22 }, \ 1290 { 17, 0x23 }, \ 1291 { 18, 0x02 }, \ 1292 { 19, 0xa4 }, \ 1293 { 20, 0x01 }, \ 1294 { 21, 0x12 }, \ 1295 { 22, 0x80 }, \ 1296 { 23, 0xb3 }, \ 1297 { 24, 0x00 }, \ 1298 { 25, 0x00 }, \ 1299 { 26, 0x00 }, \ 1300 { 27, 0x00 }, \ 1301 { 28, 0x18 }, \ 1302 { 29, 0xee }, \ 1303 { 30, 0x6b }, \ 1304 { 31, 0x31 }, \ 1305 { 32, 0x5d }, \ 1306 { 33, 0x00 }, \ 1307 { 34, 0x96 }, \ 1308 { 35, 0x55 }, \ 1309 { 36, 0x08 }, \ 1310 { 37, 0xbb }, \ 1311 { 38, 0xb3 }, \ 1312 { 39, 0xb3 }, \ 1313 { 40, 0x03 }, \ 1314 { 41, 0x00 }, \ 1315 { 42, 0x00 }, \ 1316 { 43, 0xc5 }, \ 1317 { 44, 0xc5 }, \ 1318 { 45, 0xc5 }, \ 1319 { 46, 0x07 }, \ 1320 { 47, 0xa8 }, \ 1321 { 48, 0xef }, \ 1322 { 49, 0x1a }, \ 1323 { 54, 0x07 }, \ 1324 { 55, 0xa7 }, \ 1325 { 56, 0xcc }, \ 1326 { 57, 0x14 }, \ 1327 { 58, 0x07 }, \ 1328 { 59, 0xa8 }, \ 1329 { 60, 0xd7 }, \ 1330 { 61, 0x10 }, \ 1331 { 62, 0x1c }, \ 1332 { 63, 0x00 } 1333 1334 #define MT7601_BANK5_RF \ 1335 { 0, 0x47 }, \ 1336 { 1, 0x00 }, \ 1337 { 2, 0x00 }, \ 1338 { 3, 0x08 }, \ 1339 { 4, 0x04 }, \ 1340 { 5, 0x20 }, \ 1341 { 6, 0x3a }, \ 1342 { 7, 0x3a }, \ 1343 { 8, 0x00 }, \ 1344 { 9, 0x00 }, \ 1345 { 10, 0x10 }, \ 1346 { 11, 0x10 }, \ 1347 { 12, 0x10 }, \ 1348 { 13, 0x10 }, \ 1349 { 14, 0x10 }, \ 1350 { 15, 0x20 }, \ 1351 { 16, 0x22 }, \ 1352 { 17, 0x7c }, \ 1353 { 18, 0x00 }, \ 1354 { 19, 0x00 }, \ 1355 { 20, 0x00 }, \ 1356 { 21, 0xf1 }, \ 1357 { 22, 0x11 }, \ 1358 { 23, 0x02 }, \ 1359 { 24, 0x41 }, \ 1360 { 25, 0x20 }, \ 1361 { 26, 0x00 }, \ 1362 { 27, 0xd7 }, \ 1363 { 28, 0xa2 }, \ 1364 { 29, 0x20 }, \ 1365 { 30, 0x49 }, \ 1366 { 31, 0x20 }, \ 1367 { 32, 0x04 }, \ 1368 { 33, 0xf1 }, \ 1369 { 34, 0xa1 }, \ 1370 { 35, 0x01 }, \ 1371 { 41, 0x00 }, \ 1372 { 42, 0x00 }, \ 1373 { 43, 0x00 }, \ 1374 { 44, 0x00 }, \ 1375 { 45, 0x00 }, \ 1376 { 46, 0x00 }, \ 1377 { 47, 0x00 }, \ 1378 { 48, 0x00 }, \ 1379 { 49, 0x00 }, \ 1380 { 50, 0x00 }, \ 1381 { 51, 0x00 }, \ 1382 { 52, 0x00 }, \ 1383 { 53, 0x00 }, \ 1384 { 54, 0x00 }, \ 1385 { 55, 0x00 }, \ 1386 { 56, 0x00 }, \ 1387 { 57, 0x00 }, \ 1388 { 58, 0x31 }, \ 1389 { 59, 0x31 }, \ 1390 { 60, 0x0a }, \ 1391 { 61, 0x02 }, \ 1392 { 62, 0x00 }, \ 1393 { 63, 0x00 } 1394