1 /* $OpenBSD: if_mvnetareg.h,v 1.7 2022/06/03 03:17:36 dlg Exp $ */ 2 /* $NetBSD: mvnetareg.h,v 1.8 2013/12/23 02:23:25 kiyohara Exp $ */ 3 /* 4 * Copyright (c) 2007, 2013 KIYOHARA Takashi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #ifndef _MVNETAREG_H_ 29 #define _MVNETAREG_H_ 30 31 #define MVNETA_NWINDOW 6 32 #define MVNETA_NREMAP 4 33 34 #define MVNETA_PHY_TIMEOUT 10000 /* msec */ 35 36 /* 37 * Ethernet Unit Registers 38 */ 39 40 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 41 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 42 #define MVNETA_PRXF01(q) (0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */ 43 #define MVNETA_PRXF23(q) (0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */ 44 #define MVNETA_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 45 #define MVNETA_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 46 #define MVNETA_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 47 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 48 #define MVNETA_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 49 #define MVNETA_PPLBSZ(q) (0x1700 + ((q) << 2)) /* P Pool n Buffer Size */ 50 #define MVNETA_PRXFC 0x1710 /* Port RX Flow Control */ 51 #define MVNETA_PRXTXP 0x1714 /* Port RX_TX Pause */ 52 #define MVNETA_PRXFCG 0x1718 /* Port RX Flow Control Generation */ 53 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */ 54 #define MVNETA_RXCTRL 0x1d00 /* RX Control */ 55 #define MVNETA_RXHWFWD(n) (0x1d10 + (((n) & ~0x1) << 1)) 56 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */ 57 #define MVNETA_RXHWFWDPTR 0x1d30 /* RX Hardware Forwarding Pointer */ 58 #define MVNETA_RXHWFWDTH 0x1d40 /* RX Hardware Forwarding Threshold */ 59 #define MVNETA_RXHWFWDDQA 0x1d44 /* RX Hw Fwd Descriptors Queue Address*/ 60 #define MVNETA_RXHWFWDQS 0x1d48 /* RX Hw Fwd Descriptors Queue Size */ 61 #define MVNETA_RXHWFWDQENB 0x1d4c /* RX Hw Fwd Queue Enable */ 62 #define MVNETA_RXHWFWDACPT 0x1d50 /* RX Hw Forwarding Accepted Counter */ 63 #define MVNETA_RXHWFWDYDSCRD 0x1d54 /* RX Hw Fwd Yellow Discarded Counter */ 64 #define MVNETA_RXHWFWDGDSCRD 0x1d58 /* RX Hw Fwd Green Discarded Counter */ 65 #define MVNETA_RXHWFWDTHDSCRD 0x1d5c /*RX HwFwd Threshold Discarded Counter*/ 66 #define MVNETA_RXHWFWDTXGAP 0x1d6c /*RX Hardware Forwarding TX Access Gap*/ 67 68 /* Ethernet Unit Global Registers */ 69 #define MVNETA_PHYADDR 0x2000 70 #define MVNETA_SMI 0x2004 71 #define MVNETA_EUDA 0x2008 /* Ethernet Unit Default Address */ 72 #define MVNETA_EUDID 0x200c /* Ethernet Unit Default ID */ 73 #define MVNETA_ERETRY 0x2010 /* Ethernet Unit MBUS Retry */ 74 #define MVNETA_EU 0x2014 /* Ethernet Unit Reserved */ 75 #define MVNETA_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 76 #define MVNETA_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 77 #define MVNETA_EUEA 0x2094 /* Ethernet Unit Error Address */ 78 #define MVNETA_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 79 #define MVNETA_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */ 80 #define MVNETA_EUC 0x20b0 /* Ethernet Unit Control */ 81 82 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 83 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */ 84 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 85 #define MVNETA_BARE 0x2290 /* Base Address Enable */ 86 #define MVNETA_EPAP 0x2294 /* Ethernet Port Access Protect */ 87 88 /* Ethernet Unit Port Registers */ 89 #define MVNETA_PXC 0x2400 /* Port Configuration */ 90 #define MVNETA_PXCX 0x2404 /* Port Configuration Extend */ 91 #define MVNETA_MIISP 0x2408 /* MII Serial Parameters */ 92 #define MVNETA_GMIISP 0x240c /* GMII Serial Params */ 93 #define MVNETA_EVLANE 0x2410 /* VLAN EtherType */ 94 #define MVNETA_MACAL 0x2414 /* MAC Address Low */ 95 #define MVNETA_MACAH 0x2418 /* MAC Address High */ 96 #define MVNETA_SDC 0x241c /* SDMA Configuration */ 97 #define MVNETA_DSCP(n) (0x2420 + ((n) << 2)) 98 #define MVNETA_PSC 0x243c /* Port Serial Control0 */ 99 #define MVNETA_VPT2P 0x2440 /* VLAN Priority Tag to Priority */ 100 #define MVNETA_PS 0x2444 /* Ethernet Port Status */ 101 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */ 102 #define MVNETA_PSC1 0x244c /* Port Serial Control1 */ 103 #define MVNETA_MH 0x2454 /* Marvell Header */ 104 #define MVNETA_MTU 0x2458 /* Max Transmit Unit */ 105 #define MVNETA_IC 0x2460 /* Port Interrupt Cause */ 106 #define MVNETA_ICE 0x2464 /* Port Interrupt Cause Extend */ 107 #define MVNETA_PIM 0x2468 /* Port Interrupt Mask */ 108 #define MVNETA_PEIM 0x246c /* Port Extend Interrupt Mask */ 109 #define MVNETA_PRFUT 0x2470 /* Port Rx FIFO Urgent Threshold */ 110 #define MVNETA_PTFUT 0x2474 /* Port Tx FIFO Urgent Threshold */ 111 #define MVNETA_PXTFTT 0x2478 /* Port Tx FIFO Threshold */ 112 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */ 113 #define MVNETA_PXDFC 0x2484 /* Port Rx Discard Frame Counter */ 114 #define MVNETA_POFC 0x2488 /* Port Overrun Frame Counter */ 115 #define MVNETA_PIAE 0x2494 /* Port Internal Address Error */ 116 #define MVNETA_AIP0ADR 0x2498 /* Arp IP0 Address */ 117 #define MVNETA_AIP1ADR 0x249c /* Arp IP1 Address */ 118 #define MVNETA_SERDESCFG 0x24a0 /* Serdes Configuration */ 119 #define MVNETA_SERDESSTS 0x24a4 /* Serdes Status */ 120 #define MVNETA_ETP 0x24bc /* Ethernet Type Priority */ 121 #define MVNETA_TQFPC 0x24dc /* Transmit Queue Fixed Priority Cfg */ 122 #define MVNETA_TQC_1 0x24e4 123 #define MVNETA_OMSCD 0x24f4 /* One mS Clock Divider */ 124 #define MVNETA_PFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/ 125 #define MVNETA_PACC 0x2500 /* Port Acceleration Mode */ 126 #define MVNETA_PBMADDR 0x2504 /* Port BM Address */ 127 #define MVNETA_PV 0x25bc /* Port Version */ 128 #define MVNETA_CRDP(n) (0x260c + ((n) << 4)) 129 /* Ethernet Current Receive Descriptor Pointers */ 130 #define MVNETA_RQC 0x2680 /* Receive Queue Command */ 131 #define MVNETA_TCSDP 0x2684 /* Tx Current Served Desc Pointer */ 132 #define MVNETA_TCQDP 0x26c0 /* Tx Current Queue Desc Pointer */ 133 #define MVNETA_TQTBCOUNT(q) (0x2700 + ((q) << 4)) 134 /* Transmit Queue Token-Bucket Counter */ 135 #define MVNETA_TQTBCONFIG(q) (0x2704 + ((q) << 4)) 136 /* Transmit Queue Token-Bucket Configuration */ 137 #define MVNETA_TQAC(q) (0x2708 + ((q) << 4)) 138 /* Transmit Queue Arbiter Configuration */ 139 140 #define MVNETA_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) /* Port CPUn to Queue */ 141 #define MVNETA_PRXITTH(q) (0x2580 + ((q) << 2)) /* Port RX Intr Threshold*/ 142 #define MVNETA_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 143 #define MVNETA_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 144 #define MVNETA_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 145 #define MVNETA_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 146 #define MVNETA_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 147 #define MVNETA_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 148 #define MVNETA_PIE 0x25b8 /* Port Interrupt Enable */ 149 150 #define MVNETA_PMACC0 0x2c00 /* Port MAC Control 0 */ 151 #define MVNETA_PMACC1 0x2c04 /* Port MAC Control 1 */ 152 #define MVNETA_PMACC2 0x2c08 /* Port MAC Control 2 */ 153 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 154 #define MVNETA_PS0 0x2c10 /* Port Status 0 */ 155 #define MVNETA_PSPC 0x2c14 /* Port Serial Parameters Config */ 156 #define MVNETA_PIC_2 0x2c20 /* Port Interrupt Cause */ 157 #define MVNETA_PIM_2 0x2c24 /* Port Interrupt Mask */ 158 #define MVNETA_PPRBSS 0x2c38 /* Port PRBS Status */ 159 #define MVNETA_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 160 #define MVNETA_PMACC3 0x2c48 /* Port MAC Control 3 */ 161 #define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 162 #define MVNETA_PMACC4 0x2c90 /* Port MAC Control 4 */ 163 #define MVNETA_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 164 #define MVNETA_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 165 #define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */ 166 #define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */ 167 #define MVNETA_LPIS 0x2ccc /* LPI status */ 168 #define MVNETA_LPIC 0x2cd0 /* LPI counter */ 169 170 #define MVNETA_PPLLC 0x2e04 /* Power and PLL Control */ 171 #define MVNETA_DLE 0x2e8c /* Digital Loopback Enable */ 172 #define MVNETA_RCS 0x2f18 /* Reference Clock Select */ 173 174 /* MAC MIB Counters 0x3000 - 0x307c */ 175 176 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 177 178 #define MVNETA_NDFSMT 0x40 179 #define MVNETA_DFSMT 0x3400 180 /* Destination Address Filter Special Multicast Table */ 181 #define MVNETA_NDFOMT 0x40 182 #define MVNETA_DFOMT 0x3500 183 /* Destination Address Filter Other Multicast Table */ 184 #define MVNETA_NDFUT 0x4 185 #define MVNETA_DFUT 0x3600 186 /* Destination Address Filter Unicast Table */ 187 188 #define MVNETA_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 189 #define MVNETA_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 190 #define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 191 #define MVNETA_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 192 #define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 193 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 194 #define MVNETA_PTXINIT 0x3cf0 /* Port TX Initialization */ 195 #define MVNETA_PTXDOSD 0x3cf4 /* Port TX Disable Outstanding Reads */ 196 197 #define MVNETA_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 198 #define MVNETA_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 199 #define MVNETA_TXNB 0x3cfc /* Tx Number of New Bytes */ 200 #define MVNETA_TXGB 0x3d00 /* Tx Green Number of Bytes */ 201 #define MVNETA_TXYB 0x3d04 /* Tx Yellow Number of Bytes */ 202 203 /* Tx DMA Packet Modification Registers 0x3d00 - 0x3dff */ 204 205 /* Tx DMA Queue Arbiter Registers 0x3e00 - 0x3eff */ 206 #define MVNETA_TXMTU 0x3e0c /* Tx Max MTU */ 207 #define MVNETA_TXMTU_MAX 0x3ffff 208 #define MVNETA_TXTKSIZE 0x3e14 /* Tx Token Size */ 209 #define MVNETA_TXQTKSIZE(q) (0x3e40 + ((q) << 2)) /* Tx Token Size */ 210 211 212 /* PHY Address (MVNETA_PHYADDR) */ 213 #define MVNETA_PHYADDR_PHYAD_MASK 0x1f 214 #define MVNETA_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5)) 215 216 /* SMI register fields (MVNETA_SMI) */ 217 #define MVNETA_SMI_DATA_MASK 0x0000ffff 218 #define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 219 #define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 220 #define MVNETA_SMI_OPCODE_WRITE (0 << 26) 221 #define MVNETA_SMI_OPCODE_READ (1 << 26) 222 #define MVNETA_SMI_READVALID (1 << 27) 223 #define MVNETA_SMI_BUSY (1 << 28) 224 225 /* Ethernet Unit Default ID (MVNETA_EUDID) */ 226 #define MVNETA_EUDID_DIDR_MASK 0x0000000f 227 #define MVNETA_EUDID_DATTR_MASK 0x00000ff0 228 229 /* Ethernet Unit Reserved (MVNETA_EU) */ 230 #define MVNETA_EU_FASTMDC (1 << 0) 231 #define MVNETA_EU_ACCS (1 << 1) 232 233 /* Ethernet Unit Interrupt Cause (MVNETA_EUIC) */ 234 #define MVNETA_EUIC_ETHERINTSUM (1 << 0) 235 #define MVNETA_EUIC_PARITY (1 << 1) 236 #define MVNETA_EUIC_ADDRVIOL (1 << 2) 237 #define MVNETA_EUIC_ADDRVNOMATCH (1 << 3) 238 #define MVNETA_EUIC_SMIDONE (1 << 4) 239 #define MVNETA_EUIC_COUNTWA (1 << 5) 240 #define MVNETA_EUIC_INTADDRERR (1 << 7) 241 #define MVNETA_EUIC_PORT0DPERR (1 << 9) 242 #define MVNETA_EUIC_TOPDPERR (1 << 12) 243 244 /* Ethernet Unit Internal Addr Error (MVNETA_EUIAE) */ 245 #define MVNETA_EUIAE_INTADDR_MASK 0x000001ff 246 247 /* Ethernet Unit Port Pads Calibration (MVNETA_EUPCR) */ 248 #define MVNETA_EUPCR_DRVN_MASK 0x0000001f 249 #define MVNETA_EUPCR_TUNEEN (1 << 16) 250 #define MVNETA_EUPCR_LOCKN_MASK 0x003e0000 251 #define MVNETA_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */ 252 #define MVNETA_EUPCR_WREN (1U << 31) 253 254 /* Ethernet Unit Control (MVNETA_EUC) */ 255 #define MVNETA_EUC_PORT0DPPAR (1 << 0) 256 #define MVNETA_EUC_POLLING (1 << 1) 257 #define MVNETA_EUC_TOPDPPAR (1 << 3) 258 #define MVNETA_EUC_PORT0PW (1 << 16) 259 #define MVNETA_EUC_PORTRESET (1 << 24) 260 #define MVNETA_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 261 262 /* Base Address (MVNETA_BASEADDR) */ 263 #define MVNETA_BASEADDR_TARGET(target) ((target) & 0xf) 264 #define MVNETA_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 265 #define MVNETA_BASEADDR_BASE(base) ((base) & 0xffff0000) 266 267 /* Size (MVNETA_S) */ 268 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000) 269 270 /* Base Address Enable (MVNETA_BARE) */ 271 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1) 272 #define MVNETA_BARE_EN(win) ((1 << (win)) & MVNETA_BARE_EN_MASK) 273 274 /* Ethernet Port Access Protect (MVNETA_EPAP) */ 275 #define MVNETA_EPAP_AC_NAC 0x0 /* No access allowed */ 276 #define MVNETA_EPAP_AC_RO 0x1 /* Read Only */ 277 #define MVNETA_EPAP_AC_FA 0x3 /* Full access (r/w) */ 278 #define MVNETA_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 279 280 /* Port Configuration (MVNETA_PXC) */ 281 #define MVNETA_PXC_UPM (1 << 0) /* Uni Promisc mode */ 282 #define MVNETA_PXC_RXQ(q) ((q) << 1) 283 #define MVNETA_PXC_RXQ_MASK MVNETA_PXC_RXQ(7) 284 #define MVNETA_PXC_RXQARP(q) ((q) << 4) 285 #define MVNETA_PXC_RXQARP_MASK MVNETA_PXC_RXQARP(7) 286 #define MVNETA_PXC_RB (1 << 7) /* Rej mode of MAC */ 287 #define MVNETA_PXC_RBIP (1 << 8) 288 #define MVNETA_PXC_RBARP (1 << 9) 289 #define MVNETA_PXC_AMNOTXES (1 << 12) 290 #define MVNETA_PXC_RBARPF (1 << 13) 291 #define MVNETA_PXC_TCPCAPEN (1 << 14) 292 #define MVNETA_PXC_UDPCAPEN (1 << 15) 293 #define MVNETA_PXC_TCPQ(q) ((q) << 16) 294 #define MVNETA_PXC_TCPQ_MASK MVNETA_PXC_TCPQ(7) 295 #define MVNETA_PXC_UDPQ(q) ((q) << 19) 296 #define MVNETA_PXC_UDPQ_MASK MVNETA_PXC_UDPQ(7) 297 #define MVNETA_PXC_BPDUQ(q) ((q) << 22) 298 #define MVNETA_PXC_BPDUQ_MASK MVNETA_PXC_BPDUQ(7) 299 #define MVNETA_PXC_RXCS (1 << 25) 300 301 /* Port Configuration Extend (MVNETA_PXCX) */ 302 #define MVNETA_PXCX_SPAN (1 << 1) 303 #define MVNETA_PXCX_TXCRCDIS (1 << 3) 304 305 /* MII Serial Parameters (MVNETA_MIISP) */ 306 #define MVNETA_MIISP_JAMLENGTH_12KBIT 0x00000000 307 #define MVNETA_MIISP_JAMLENGTH_24KBIT 0x00000001 308 #define MVNETA_MIISP_JAMLENGTH_32KBIT 0x00000002 309 #define MVNETA_MIISP_JAMLENGTH_48KBIT 0x00000003 310 #define MVNETA_MIISP_JAMIPG(x) (((x) & 0x7c) << 0) 311 #define MVNETA_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5) 312 #define MVNETA_MIISP_IPGDATA(x) (((x) & 0x7c) << 10) 313 #define MVNETA_MIISP_DATABLIND(x) (((x) & 0x1f) << 17) 314 315 /* GMII Serial Parameters (MVNETA_GMIISP) */ 316 #define MVNETA_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7) 317 318 /* SDMA Configuration (MVNETA_SDC) */ 319 #define MVNETA_SDC_RIFB (1 << 0) 320 #define MVNETA_SDC_RXBSZ(x) ((x) << 1) 321 #define MVNETA_SDC_RXBSZ_MASK MVNETA_SDC_RXBSZ(7) 322 #define MVNETA_SDC_RXBSZ_1_64BITWORDS MVNETA_SDC_RXBSZ(0) 323 #define MVNETA_SDC_RXBSZ_2_64BITWORDS MVNETA_SDC_RXBSZ(1) 324 #define MVNETA_SDC_RXBSZ_4_64BITWORDS MVNETA_SDC_RXBSZ(2) 325 #define MVNETA_SDC_RXBSZ_8_64BITWORDS MVNETA_SDC_RXBSZ(3) 326 #define MVNETA_SDC_RXBSZ_16_64BITWORDS MVNETA_SDC_RXBSZ(4) 327 #define MVNETA_SDC_BLMR (1 << 4) 328 #define MVNETA_SDC_BLMT (1 << 5) 329 #define MVNETA_SDC_SWAPMODE (1 << 6) 330 #define MVNETA_SDC_IPGINTRX_V1_MASK __BITS(21, 8) 331 #define MVNETA_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7)) 332 #define MVNETA_SDC_IPGINTRX_V1(x) (((x) << 4) \ 333 & MVNETA_SDC_IPGINTRX_V1_MASK) 334 #define MVNETA_SDC_IPGINTRX_V2(x) ((((x) & 0x8000) << 10) \ 335 | (((x) & 0x7fff) << 7)) 336 #define MVNETA_SDC_IPGINTRX_V1_MAX 0x3fff 337 #define MVNETA_SDC_IPGINTRX_V2_MAX 0xffff 338 #define MVNETA_SDC_TXBSZ(x) ((x) << 22) 339 #define MVNETA_SDC_TXBSZ_MASK MVNETA_SDC_TXBSZ(7) 340 #define MVNETA_SDC_TXBSZ_1_64BITWORDS MVNETA_SDC_TXBSZ(0) 341 #define MVNETA_SDC_TXBSZ_2_64BITWORDS MVNETA_SDC_TXBSZ(1) 342 #define MVNETA_SDC_TXBSZ_4_64BITWORDS MVNETA_SDC_TXBSZ(2) 343 #define MVNETA_SDC_TXBSZ_8_64BITWORDS MVNETA_SDC_TXBSZ(3) 344 #define MVNETA_SDC_TXBSZ_16_64BITWORDS MVNETA_SDC_TXBSZ(4) 345 346 /* Port Serial Control (MVNETA_PSC) */ 347 #define MVNETA_PSC_PORTEN (1 << 0) 348 #define MVNETA_PSC_FLP (1 << 1) /* Force_Link_Pass */ 349 #define MVNETA_PSC_ANDUPLEX (1 << 2) /* auto nego */ 350 #define MVNETA_PSC_ANFC (1 << 3) 351 #define MVNETA_PSC_PAUSEADV (1 << 4) 352 #define MVNETA_PSC_FFCMODE (1 << 5) /* Force FC */ 353 #define MVNETA_PSC_FBPMODE (1 << 7) /* Back pressure */ 354 #define MVNETA_PSC_RESERVED (1 << 9) /* Must be set to 1 */ 355 #define MVNETA_PSC_FLFAIL (1 << 10) /* Force Link Fail */ 356 #define MVNETA_PSC_ANSPEED (1 << 13) 357 #define MVNETA_PSC_DTEADVERT (1 << 14) 358 #define MVNETA_PSC_MRU(x) ((x) << 17) 359 #define MVNETA_PSC_MRU_MASK MVNETA_PSC_MRU(7) 360 #define MVNETA_PSC_MRU_1518 0 361 #define MVNETA_PSC_MRU_1522 1 362 #define MVNETA_PSC_MRU_1552 2 363 #define MVNETA_PSC_MRU_9022 3 364 #define MVNETA_PSC_MRU_9192 4 365 #define MVNETA_PSC_MRU_9700 5 366 #define MVNETA_PSC_SETFULLDX (1 << 21) 367 #define MVNETA_PSC_SETFCEN (1 << 22) 368 #define MVNETA_PSC_SETGMIISPEED (1 << 23) 369 #define MVNETA_PSC_SETMIISPEED (1 << 24) 370 371 /* Ethernet Port Status (MVNETA_PS) */ 372 #define MVNETA_PS_LINKUP (1 << 1) 373 #define MVNETA_PS_FULLDX (1 << 2) 374 #define MVNETA_PS_ENFC (1 << 3) 375 #define MVNETA_PS_GMIISPEED (1 << 4) 376 #define MVNETA_PS_MIISPEED (1 << 5) 377 #define MVNETA_PS_TXINPROG (1 << 7) 378 #define MVNETA_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */ 379 #define MVNETA_PS_RXFIFOEMPTY (1 << 16) 380 /* Armada XP */ 381 #define MVNETA_PS_TXINPROG_MASK (0xff << 0) 382 #define MVNETA_PS_TXINPROG_(q) (1 << ((q) + 0)) 383 #define MVNETA_PS_TXFIFOEMP_MASK (0xff << 8) 384 #define MVNETA_PS_TXFIFOEMP_(q) (1 << ((q) + 8)) 385 386 /* Transmit Queue Command (MVNETA_TQC) */ 387 #define MVNETA_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 388 #define MVNETA_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 389 390 /* Port Serial Control 1 (MVNETA_PSC1) */ 391 #define MVNETA_PSC1_PCSLB (1 << 1) 392 #define MVNETA_PSC1_RGMIIEN (1 << 3) /* RGMII */ 393 #define MVNETA_PSC1_PRST (1 << 4) /* Port Reset */ 394 395 /* Port Interrupt Cause (MVNETA_IC) */ 396 #define MVNETA_IC_RXBUF (1 << 0) 397 #define MVNETA_IC_EXTEND (1 << 1) 398 #define MVNETA_IC_RXBUFQ_MASK (0xff << 2) 399 #define MVNETA_IC_RXBUFQ(q) (1 << ((q) + 2)) 400 #define MVNETA_IC_RXERROR (1 << 10) 401 #define MVNETA_IC_RXERRQ_MASK (0xff << 11) 402 #define MVNETA_IC_RXERRQ(q) (1 << ((q) + 11)) 403 #define MVNETA_IC_TXEND(q) (1 << ((q) + 19)) 404 #define MVNETA_IC_ETHERINTSUM (1U << 31) 405 406 /* Port Interrupt Cause Extend (MVNETA_ICE) */ 407 #define MVNETA_ICE_TXBUF_MASK (0xff << + 0) 408 #define MVNETA_ICE_TXBUF(q) (1 << ((q) + 0)) 409 #define MVNETA_ICE_TXERR_MASK (0xff << + 8) 410 #define MVNETA_ICE_TXERR(q) (1 << ((q) + 8)) 411 #define MVNETA_ICE_PHYSTC (1 << 16) 412 #define MVNETA_ICE_PTP (1 << 17) 413 #define MVNETA_ICE_RXOVR (1 << 18) 414 #define MVNETA_ICE_TXUDR (1 << 19) 415 #define MVNETA_ICE_LINKCHG (1 << 20) 416 #define MVNETA_ICE_SERDESREALIGN (1 << 21) 417 #define MVNETA_ICE_INTADDRERR (1 << 23) 418 #define MVNETA_ICE_SYNCCHANGED (1 << 24) 419 #define MVNETA_ICE_PRBSERROR (1 << 25) 420 #define MVNETA_ICE_ETHERINTSUM (1U << 31) 421 422 /* Port Tx FIFO Urgent Threshold (MVNETA_PTFUT) */ 423 #define MVNETA_PTFUT_IPGINTTX_V1_MASK __BITS(17, 4) 424 #define MVNETA_PTFUT_IPGINTTX_V2_MASK __BITS(19, 4) 425 #define MVNETA_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V1_MASK) 426 #define MVNETA_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V2_MASK) 427 #define MVNETA_PTFUT_IPGINTTX_V1_MAX 0x3fff 428 #define MVNETA_PTFUT_IPGINTTX_V2_MAX 0xffff 429 430 /* Port Rx Minimal Frame Size (MVNETA_PMFS) */ 431 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 432 /* RxMFS = 40,44,48,52,56,60,64 bytes */ 433 434 /* Transmit Queue Fixed Priority Configuration */ 435 #define MVNETA_TQFPC_EN(q) (1 << (q)) 436 437 /* Receive Queue Command (MVNETA_RQC) */ 438 #define MVNETA_RQC_ENQ_MASK (0xff << 0) /* Enable Q */ 439 #define MVNETA_RQC_ENQ(n) (1 << (0 + (n))) 440 #define MVNETA_RQC_DISQ_MASK (0xff << 8) /* Disable Q */ 441 #define MVNETA_RQC_DISQ(n) (1 << (8 + (n))) 442 #define MVNETA_RQC_DISQ_DISABLE(q) ((q) << 8) 443 444 /* Destination Address Filter Registers (MVNETA_DF{SM,OM,U}T) */ 445 #define MVNETA_DF(n, x) ((x) << (8 * (n))) 446 #define MVNETA_DF_PASS (1 << 0) 447 #define MVNETA_DF_QUEUE(q) ((q) << 1) 448 #define MVNETA_DF_QUEUE_MASK ((7) << 1) 449 450 /* One mS Clock Divider (MVNETA_OMSCD) */ 451 #define MVNETA_OMSCD_1MS_CLOCK_ENABLE (1U << 31) 452 453 /* Port Acceleration Mode (MVNETA_PACC) */ 454 #define MVGVE_PACC_ACCELERATIONMODE_MASK 0x7 455 #define MVGVE_PACC_ACCELERATIONMODE_BM 0x0 /* Basic Mode */ 456 #define MVGVE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 457 #define MVGVE_PACC_ACCELERATIONMODE_EDMBM 0x2 /* with BM */ 458 #define MVGVE_PACC_ACCELERATIONMODE_EDMPNC 0x3 /* with PnC */ 459 #define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC 0x4 /* with BM & PnC */ 460 461 /* Port BM Address (MVNETA_PBMADDR) */ 462 #define MVNETA_PBMADDR_BMADDRESS_MASK 0xfffff800 463 464 /* Port Serdes Config (MVNETA_SERDESCFG) */ 465 #define MVNETA_SERDESCFG_SGMII_PROTO 0x0cc7 466 #define MVNETA_SERDESCFG_QSGMII_PROTO 0x0667 467 #define MVNETA_SERDESCFG_HSGMII_PROTO 0x1107 468 469 /* Ether Type Priority (MVNETA_ETP) */ 470 #define MVNETA_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 471 #define MVNETA_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 472 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 473 #define MVNETA_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 474 #define MVNETA_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 475 476 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVNETA_RXHWFWD) */ 477 #define MVNETA_RXHWFWD_PORT_BASEADDRESS(p, x) xxxxx 478 479 /* RX Hardware Forwarding Pointer (MVNETA_RXHWFWDPTR) */ 480 #define MVNETA_RXHWFWDPTR_QUEUENO(q) ((q) << 8) /* Queue Number */ 481 #define MVNETA_RXHWFWDPTR_PORTNO(p) ((p) << 11) /* Port Number */ 482 483 /* RX Hardware Forwarding Threshold (MVNETA_RXHWFWDTH) */ 484 #define MVNETA_RXHWFWDTH_DROPRNDGENBITS(n) (((n) & 0x3ff) << 0) 485 #define MVNETA_RXHWFWDTH_DROPTHRESHOLD(n) (((n) & 0xf) << 16) 486 487 /* RX Control (MVNETA_RXCTRL) */ 488 #define MVNETA_RXCTRL_PACKETCOLORSRCSELECT(x) (1 << 0) 489 #define MVNETA_RXCTRL_GEMPORTIDSRCSEL(x) ((x) << 4) 490 #define MVNETA_RXCTRL_TXHWFRWMQSRC(x) (1 << 8) 491 #define MVNETA_RXCTRL_RX_MH_SELECT(x) ((x) << 12) 492 #define MVNETA_RXCTRL_RX_TX_SRC_SELECT (1 << 16) 493 #define MVNETA_RXCTRL_HWFRWDENB (1 << 17) 494 #define MVNETA_RXCTRL_HWFRWDSHORTPOOLID(id) (((id) & 0x3) << 20) 495 #define MVNETA_RXCTRL_HWFRWDLONGPOOLID(id) (((id) & 0x3) << 22) 496 497 /* Port RX queues Configuration (MVNETA_PRXC) */ 498 #define MVNETA_PRXC_POOLIDSHORT(i) (((i) & 0x3) << 4) 499 #define MVNETA_PRXC_POOLIDLONG(i) (((i) & 0x3) << 6) 500 #define MVNETA_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 501 #define MVNETA_PRXC_USERPREFETCHCMND0 (1 << 16) 502 503 /* Port RX queues Snoop (MVNETA_PRXSNP) */ 504 #define MVNETA_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 505 #define MVNETA_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 506 507 /* Port RX queues Snoop (MVNETA_PRXSNP) */ 508 #define MVNETA_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx 509 #define MVNETA_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx 510 511 /* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */ 512 #define MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0) 513 #define MVNETA_PRXDQS_BUFFERSIZE(s) (((s) & 0xfff80000) << 19) 514 515 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */ 516 /* Occupied Descriptors Threshold */ 517 #define MVNETA_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 518 /* Non Occupied Descriptors Threshold */ 519 #define MVNETA_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 520 521 /* Port RX queues Status (MVNETA_PRXS) */ 522 /* Occupied Descriptors Counter */ 523 #define MVNETA_PRXS_ODC(x) (((x) >> 0) & 0x3fff) 524 /* Non Occupied Descriptors Counter */ 525 #define MVNETA_PRXS_NODC(x) (((x) >> 16) & 0x3fff) 526 527 /* Port RX queues Status Update (MVNETA_PRXSU) */ 528 #define MVNETA_PRXSU_MAX 0xff /* works as a mask too */ 529 /* Number Of Processed Descriptors */ 530 #define MVNETA_PRXSU_NOPD(x) (((x) & MVNETA_PRXSU_MAX) << 0) 531 /* Number Of New Descriptors */ 532 #define MVNETA_PRXSU_NOND(x) (((x) & MVNETA_PRXSU_MAX) << 16) 533 534 /* Port RX Flow Control (MVNETA_PRXFC) */ 535 #define MVNETA_PRXFC_PERPRIOFCGENCONTROL (1 << 0) 536 #define MVNETA_PRXFC_TXPAUSECONTROL (1 << 1) 537 538 /* Port RX_TX Pause (MVNETA_PRXTXP) */ 539 #define MVNETA_PRXTXP_TXPAUSE(x) ((x) & 0xff) 540 541 /* Port RX Flow Control Generation (MVNETA_PRXFCG) */ 542 #define MVNETA_PRXFCG_PERPRIOFCGENDATA (1 << 0) 543 #define MVNETA_PRXFCG_PERPRIOFCGENQNO(x) (((x) & 0x7) << 4) 544 545 /* Port RX Initialization (MVNETA_PRXINIT) */ 546 #define MVNETA_PRXINIT_RXDMAINIT (1 << 0) 547 548 /* TX Number of New Bytes (MVNETA_TXNB) */ 549 #define MVNETA_TXNB_NOOFNEWBYTES(b) (((b) & 0xffff) << 0) 550 #define MVNETA_TXNB_PKTQNO(q) (((q) & 0x7) << 28) 551 #define MVNETA_TXNB_PKTCOLOR (1U << 31) 552 553 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */ 554 /* Descriptors Queue Size */ 555 #define MVNETA_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 556 /* Transmitted Buffer Threshold */ 557 #define MVNETA_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 558 559 /* Port TX queues Status (MVNETA_PTXS) */ 560 /* Pending Descriptors Counter */ 561 #define MVNETA_PTXDQS_PDC(x) (((x) >> 0) & 0x3fff) 562 /* Transmitted Buffer Counter */ 563 #define MVNETA_PTXS_TBC(x) (((x) >> 16) & 0x3fff) 564 565 /* Port TX queues Status Update (MVNETA_PTXSU) */ 566 #define MVNETA_PTXSU_MAX 0xff /* works as a mask too */ 567 /* Number Of Written Descriptors */ 568 #define MVNETA_PTXSU_NOWD(x) (((x) & MVNETA_PTXSU_MAX) << 0) 569 /* Number Of Released Buffers */ 570 #define MVNETA_PTXSU_NORB(x) (((x) & MVNETA_PTXSU_MAX) << 16) 571 572 /* TX Transmitted Buffers Counter (MVNETA_TXTBC) */ 573 /* Transmitted Buffers Counter */ 574 #define MVNETA_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 575 576 /* Port TX Initialization (MVNETA_PTXINIT) */ 577 #define MVNETA_PTXINIT_TXDMAINIT (1 << 0) 578 579 /* Marvell Header (MVNETA_MH) */ 580 #define MVNETA_MH_MHEN (1 << 0) 581 #define MVNETA_MH_DAPREFIX (0x3 << 1) 582 #define MVNETA_MH_SPID (0xf << 4) 583 #define MVNETA_MH_MHMASK (0x3 << 8) 584 #define MVNETA_MH_MHMASK_8QUEUES (0x0 << 8) 585 #define MVNETA_MH_MHMASK_4QUEUES (0x1 << 8) 586 #define MVNETA_MH_MHMASK_2QUEUES (0x3 << 8) 587 #define MVNETA_MH_DSAEN_MASK (0x3 << 10) 588 #define MVNETA_MH_DSAEN_DISABLE (0x0 << 10) 589 #define MVNETA_MH_DSAEN_NONEXTENDED (0x1 << 10) 590 #define MVNETA_MH_DSAEN_EXTENDED (0x2 << 10) 591 592 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */ 593 #define MVNETA_PANC_FORCELINKFAIL (1 << 0) 594 #define MVNETA_PANC_FORCELINKPASS (1 << 1) 595 #define MVNETA_PANC_INBANDANEN (1 << 2) 596 #define MVNETA_PANC_INBANDANBYPASSEN (1 << 3) 597 #define MVNETA_PANC_INBANDRESTARTAN (1 << 4) 598 #define MVNETA_PANC_SETMIISPEED (1 << 5) 599 #define MVNETA_PANC_SETGMIISPEED (1 << 6) 600 #define MVNETA_PANC_ANSPEEDEN (1 << 7) 601 #define MVNETA_PANC_SETFCEN (1 << 8) 602 #define MVNETA_PANC_PAUSEADV (1 << 9) 603 #define MVNETA_PANC_ANFCEN (1 << 11) 604 #define MVNETA_PANC_SETFULLDX (1 << 12) 605 #define MVNETA_PANC_ANDUPLEXEN (1 << 13) 606 #define MVNETA_PANC_RESERVED (1 << 15) 607 608 /* Port MAC Control 0 (MVNETA_PMACC0) */ 609 #define MVNETA_PMACC0_PORTEN (1 << 0) 610 #define MVNETA_PMACC0_PORTTYPE (1 << 1) 611 #define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2) 612 #define MVNETA_PMACC0_RESERVED (1 << 15) 613 614 /* Port MAC Control 1 (MVNETA_PMACC1) */ 615 #define MVNETA_PMACC1_PCSLB (1 << 6) 616 617 /* Port MAC Control 2 (MVNETA_PMACC2) */ 618 #define MVNETA_PMACC2_INBANDAN (1 << 0) 619 #define MVNETA_PMACC2_PCSEN (1 << 3) 620 #define MVNETA_PMACC2_RGMIIEN (1 << 4) 621 #define MVNETA_PMACC2_PADDINGDIS (1 << 5) 622 #define MVNETA_PMACC2_PORTMACRESET (1 << 6) 623 #define MVNETA_PMACC2_PRBSCHECKEN (1 << 10) 624 #define MVNETA_PMACC2_PRBSGENEN (1 << 11) 625 #define MVNETA_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 626 #define MVNETA_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 627 #define MVNETA_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 628 #define MVNETA_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 629 #define MVNETA_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 630 #define MVNETA_PMACC2_RESERVED (3 << 14) 631 632 /* Port MAC Control 3 (MVNETA_PMACC3) */ 633 #define MVNETA_PMACC3_IPG_MASK 0x7f80 634 635 /* Port MAC Control 4 (MVNETA_PMACC4) */ 636 #define MVNETA_PMACC4_SHORT_PREAMBLE (1 << 1) 637 638 /* Port Interrupt Cause/Mask (MVNETA_PIC_2/MVNETA_PIM_2) */ 639 #define MVNETA_PI_2_INTSUM (1 << 0) 640 #define MVNETA_PI_2_LSC (1 << 1) /* LinkStatus Change */ 641 #define MVNETA_PI_2_ACOP (1 << 2) /* AnCompleted OnPort */ 642 #define MVNETA_PI_2_AOOR (1 << 5) /* AddressOut Of Range */ 643 #define MVNETA_PI_2_SSC (1 << 6) /* SyncStatus Change */ 644 #define MVNETA_PI_2_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 645 #define MVNETA_PI_2_MIBCWA (1 << 15) /* MIB counter wrap around */ 646 #define MVNETA_PI_2_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 647 #define MVNETA_PI_2_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 648 #define MVNETA_PI_2_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 649 #define MVNETA_PI_2_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 650 #define MVNETA_PI_2_MIBCCD (1 << 14) /* MIB counters copy done */ 651 652 /* LPI Control 0 (MVNETA_LPIC0) */ 653 #define MVNETA_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 654 #define MVNETA_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 655 656 /* LPI Control 1 (MVNETA_LPIC1) */ 657 #define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 658 #define MVNETA_LPIC1_LPIRF (1 << 1) /* LPI request force */ 659 #define MVNETA_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 660 #define MVNETA_LPIC1_TWLIMIT (((x) & 0xfff) << 4) 661 662 /* LPI Status (MVNETA_LPIS) */ 663 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 664 #define MVNETA_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 665 #define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 666 #define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 667 #define MVNETA_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 668 669 /* Port PRBS Status (MVNETA_PPRBSS) */ 670 #define MVNETA_PPRBSS_PRBSCHECKLOCKED (1 << 0) 671 #define MVNETA_PPRBSS_PRBSCHECKRDY (1 << 1) 672 673 /* Port Status 0 (MVNETA_PS0) */ 674 #define MVNETA_PS0_LINKUP (1 << 0) 675 #define MVNETA_PS0_GMIISPEED (1 << 1) 676 #define MVNETA_PS0_MIISPEED (1 << 2) 677 #define MVNETA_PS0_FULLDX (1 << 3) 678 #define MVNETA_PS0_RXFCEN (1 << 4) 679 #define MVNETA_PS0_TXFCEN (1 << 5) 680 #define MVNETA_PS0_PRP (1 << 6) /* Port Rx Pause */ 681 #define MVNETA_PS0_PTP (1 << 7) /* Port Tx Pause */ 682 #define MVNETA_PS0_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 683 #define MVNETA_PS0_SYNCFAIL10MS (1 << 10) 684 #define MVNETA_PS0_ANDONE (1 << 11) 685 #define MVNETA_PS0_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 686 #define MVNETA_PS0_SYNCOK (1 << 14) 687 688 /* Port CPUn to Queue (MVNETA_PCP2Q) */ 689 #define MVNETA_PCP2Q_RXQAE_ALL (0xff << 0)/*QueueAccessEnable*/ 690 #define MVNETA_PCP2Q_TXQAE_ALL (0xff << 8)/*QueueAccessEnable*/ 691 692 /* Port RX_TX Threshold Interrupt Cause/Mask (MVNETA_PRXTXTIC/MVNETA_PRXTXTIM) */ 693 #define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 694 #define MVNETA_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 695 #define MVNETA_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 696 #define MVNETA_PRXTXTI_PRXTXICSUMMARY (1 << 29) 697 #define MVNETA_PRXTXTI_PTXERRORSUMMARY (1 << 30) 698 #define MVNETA_PRXTXTI_PMISCICSUMMARY (1U << 31) 699 700 /* Port RX_TX Interrupt Cause/Mask (MVNETA_PRXTXIC/MVNETA_PRXTXIM) */ 701 #define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 702 #define MVNETA_PRXTXI_RPQ(q) (1 << ((q) + 8)) 703 #define MVNETA_PRXTXI_RREQ(q) (1 << ((q) + 16)) 704 #define MVNETA_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 705 #define MVNETA_PRXTXI_PTXERRORSUMMARY (1 << 30) 706 #define MVNETA_PRXTXI_PMISCICSUMMARY (1U << 31) 707 708 /* Port Misc Interrupt Cause/Mask (MVNETA_PMIC/MVNETA_PMIM) */ 709 #define MVNETA_PMI_PHYSTATUSCHNG (1 << 0) 710 #define MVNETA_PMI_LINKCHANGE (1 << 1) 711 #define MVNETA_PMI_PTP (1 << 4) 712 #define MVNETA_PMI_PME (1 << 6) /* Packet Modification Error */ 713 #define MVNETA_PMI_IAE (1 << 7) /* Internal Address Error */ 714 #define MVNETA_PMI_RXOVERRUN (1 << 8) 715 #define MVNETA_PMI_RXCRCERROR (1 << 9) 716 #define MVNETA_PMI_RXLARGEPACKET (1 << 10) 717 #define MVNETA_PMI_TXUNDRN (1 << 11) 718 #define MVNETA_PMI_PRBSERROR (1 << 12) 719 #define MVNETA_PMI_PSCSYNCCHNG (1 << 13) 720 #define MVNETA_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 721 #define MVNETA_PMI_RNBTP(q) (1 << ((q) + 16)) /* RxNoBuffersToPool*/ 722 #define MVNETA_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 723 724 /* Port Interrupt Enable (MVNETA_PIE) */ 725 #define MVNETA_PIE_RXPKTINTRPTENB_ALL (0xff << 24) 726 #define MVNETA_PIE_TXPKTINTRPTENB_ALL (0xff << 8) 727 728 /* Power and PLL Control (MVNETA_PPLLC) */ 729 #define MVNETA_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 730 #define MVNETA_PPLLC_PHY_MODE_MASK (7 << 5) 731 #define MVNETA_PPLLC_PHY_MODE_SATA (0 << 5) 732 #define MVNETA_PPLLC_PHY_MODE_SAS (1 << 5) 733 #define MVNETA_PPLLC_PLL_LOCK (1 << 8) 734 #define MVNETA_PPLLC_PU_DFE (1 << 10) 735 #define MVNETA_PPLLC_PU_TX_INTP (1 << 11) 736 #define MVNETA_PPLLC_PU_TX (1 << 12) 737 #define MVNETA_PPLLC_PU_RX (1 << 13) 738 #define MVNETA_PPLLC_PU_PLL (1 << 14) 739 740 /* Digital Loopback Enable (MVNETA_DLE) */ 741 #define MVNETA_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 742 #define MVNETA_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 743 #define MVNETA_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 744 #define MVNETA_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 745 #define MVNETA_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 746 #define MVNETA_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 747 #define MVNETA_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 748 #define MVNETA_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 749 750 /* Reference Clock Select (MVNETA_RCS) */ 751 #define MVNETA_RCS_REFCLK_SEL (1 << 10) 752 753 754 /* 755 * Set the chip's packet size limit to 9022. 756 * (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) 757 */ 758 #define MVNETA_MRU 9022 759 760 #define MVNETA_RXBUF_ALIGN 32 /* Cache line size */ 761 #define MVNETA_RXBUF_MASK (MVNETA_RXBUF_ALIGN - 1) 762 #define MVNETA_HWHEADER_SIZE 2 763 764 765 /* 766 * DMA descriptors 767 * Despite the documentation saying these descriptors only need to be 768 * aligned to 16-byte boundaries, 32-byte alignment seems to be required 769 * by the hardware. We'll just pad them out to that to make it easier. 770 */ 771 struct mvneta_tx_desc { 772 #if BYTE_ORDER == BIG_ENDIAN 773 uint16_t bytecnt; /* Descriptor buffer byte count */ 774 uint16_t l4ichk; /* CPU provided TCP Checksum */ 775 uint32_t cmdsts; /* Descriptor command status */ 776 uint32_t nextdescptr; /* Next descriptor pointer */ 777 uint32_t bufptr; /* Descriptor buffer pointer */ 778 #else /* LITTLE_ENDIAN */ 779 uint32_t cmdsts; /* Descriptor command status */ 780 uint16_t l4ichk; /* CPU provided TCP Checksum */ 781 uint16_t bytecnt; /* Descriptor buffer byte count */ 782 uint32_t bufptr; /* Descriptor buffer pointer */ 783 uint32_t nextdescptr; /* Next descriptor pointer */ 784 #endif 785 uint32_t _padding[4]; 786 } __packed __aligned(32); 787 788 struct mvneta_rx_desc { 789 #if BYTE_ORDER == BIG_ENDIAN 790 uint16_t bytecnt; /* Descriptor buffer byte count */ 791 uint16_t bufsize; /* Buffer size */ 792 uint32_t cmdsts; /* Descriptor command status */ 793 uint32_t nextdescptr; /* Next descriptor pointer */ 794 uint32_t bufptr; /* Descriptor buffer pointer */ 795 #else /* LITTLE_ENDIAN */ 796 uint32_t cmdsts; /* Descriptor command status */ 797 uint16_t bufsize; /* Buffer size */ 798 uint16_t bytecnt; /* Descriptor buffer byte count */ 799 uint32_t bufptr; /* Descriptor buffer pointer */ 800 uint32_t nextdescptr; /* Next descriptor pointer */ 801 #endif 802 uint32_t _padding[4]; 803 } __packed __aligned(32); 804 805 #define MVNETA_ERROR_SUMMARY (1 << 0) 806 #define MVNETA_BUFFER_OWNED_MASK (1U << 31) 807 #define MVNETA_BUFFER_OWNED_BY_HOST (0U << 31) 808 #define MVNETA_BUFFER_OWNED_BY_DMA (1U << 31) 809 810 #define MVNETA_TX_ERROR_CODE_MASK (3 << 1) 811 #define MVNETA_TX_LATE_COLLISION_ERROR (0 << 1) 812 #define MVNETA_TX_UNDERRUN_ERROR (1 << 1) 813 #define MVNETA_TX_EXCESSIVE_COLLISION_ERRO (2 << 1) 814 #define MVNETA_TX_LLC_SNAP_FORMAT (1 << 9) 815 #define MVNETA_TX_IP_NO_FRAG (1 << 10) 816 #define MVNETA_TX_IP_HEADER_LEN(len) ((len) << 11) 817 #define MVNETA_TX_VLAN_TAGGED_FRAME (1 << 15) 818 #define MVNETA_TX_L4_TYPE_TCP (0 << 16) 819 #define MVNETA_TX_L4_TYPE_UDP (1 << 16) 820 #define MVNETA_TX_GENERATE_L4_CHKSUM (1 << 17) 821 #define MVNETA_TX_GENERATE_IP_CHKSUM (1 << 18) 822 #define MVNETA_TX_ZERO_PADDING (1 << 19) 823 #define MVNETA_TX_LAST_DESC (1 << 20) 824 #define MVNETA_TX_FIRST_DESC (1 << 21) 825 #define MVNETA_TX_GENERATE_CRC (1 << 22) 826 #define MVNETA_TX_ENABLE_INTERRUPT (1 << 23) 827 #define MVNETA_TX_L4_CSUM_FULL (1 << 30) 828 #define MVNETA_TX_L4_CSUM_NOT (1U << 31) 829 830 #define MVNETA_RX_ERROR_CODE_MASK (3 << 1) 831 #define MVNETA_RX_CRC_ERROR (0 << 1) 832 #define MVNETA_RX_OVERRUN_ERROR (1 << 1) 833 #define MVNETA_RX_MAX_FRAME_LEN_ERROR (2 << 1) 834 #define MVNETA_RX_RESOURCE_ERROR (3 << 1) 835 #define MVNETA_RX_L4_CHECKSUM_MASK (0xffff << 3) 836 #define MVNETA_RX_VLAN_TAGGED_FRAME (1 << 19) 837 #define MVNETA_RX_BPDU_FRAME (1 << 20) 838 #define MVNETA_RX_L4_TYPE_MASK (3 << 21) 839 #define MVNETA_RX_L4_TYPE_TCP (0 << 21) 840 #define MVNETA_RX_L4_TYPE_UDP (1 << 21) 841 #define MVNETA_RX_L4_TYPE_OTHER (2 << 21) 842 #define MVNETA_RX_NOT_LLC_SNAP_FORMAT (1 << 23) 843 #define MVNETA_RX_IP_FRAME_TYPE (1 << 24) 844 #define MVNETA_RX_IP_HEADER_OK (1 << 25) 845 #define MVNETA_RX_LAST_DESC (1 << 26) 846 #define MVNETA_RX_FIRST_DESC (1 << 27) 847 #define MVNETA_RX_UNKNOWN_DA (1 << 28) 848 #define MVNETA_RX_ENABLE_INTERRUPT (1 << 29) 849 #define MVNETA_RX_L4_CHECKSUM_OK (1 << 30) 850 851 #define MVNETA_RX_IP_FRAGMENT (1 << 2) 852 853 #endif /* _MVGEREG_H_ */ 854