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Searched refs:MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7938 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 macro
H A Ddce_8_0_sh_mask.h10474 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 macro
H A Ddce_10_0_sh_mask.h10172 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 macro
H A Ddce_11_0_sh_mask.h9866 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 macro
H A Ddce_11_2_sh_mask.h11140 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 macro