| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.h | 41 MachineRegisterInfo &MRI,
46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
64 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
75 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
84 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
130 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AMDGPURegisterBankInfo.h | 53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
67 MachineRegisterInfo &MRI,
70 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI) const;
80 MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI, int RSrcIdx) const;
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
151 unsigned getMappingType(const MachineRegisterInfo &MRI,
186 MachineRegisterInfo &MRI,
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| H A D | GCNRegPressure.h | 26 class MachineRegisterInfo; variable
71 const MachineRegisterInfo &MRI);
93 static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
117 mutable const MachineRegisterInfo *MRI = nullptr;
197 const MachineRegisterInfo &MRI);
201 const MachineRegisterInfo &MRI);
260 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, in getRegPressure()
274 const MachineRegisterInfo &MRI);
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| H A D | SIRegisterInfo.h | 195 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
272 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
277 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
280 getRegClassForOperandReg(const MachineRegisterInfo &MRI,
283 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
284 bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
285 bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { in isVectorRegister()
324 const MachineRegisterInfo &MRI) const override;
349 MachineRegisterInfo &MRI,
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| H A D | SIInstrInfo.h | 34 class MachineRegisterInfo; variable
69 MachineRegisterInfo &MRI,
123 MachineRegisterInfo &MRI,
796 const MachineRegisterInfo &MRI = MF.getRegInfo(); in isVGPRCopy()
802 const MachineRegisterInfo &MRI = MF.getRegInfo(); in hasVGPRUses()
888 bool usesConstantBus(const MachineRegisterInfo &MRI,
901 const MachineRegisterInfo &MRI) const;
964 bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
970 bool isLegalRegOperand(const MachineRegisterInfo &MRI,
1199 MachineRegisterInfo &MRI) { in isOfRegClass()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 40 class MachineRegisterInfo; variable
89 Register constrainRegToClass(MachineRegisterInfo &MRI,
104 MachineRegisterInfo &MRI,
123 MachineRegisterInfo &MRI,
193 Register VReg, const MachineRegisterInfo &MRI,
215 const MachineRegisterInfo &MRI);
251 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef()
415 const MachineRegisterInfo &MRI,
421 const MachineRegisterInfo &MRI,
445 const MachineRegisterInfo &MRI,
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| H A D | MIPatternMatch.h | 41 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
55 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
84 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
119 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
145 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
159 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
398 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
422 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
558 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
652 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
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| H A D | LoadStoreOpt.h | 33 class MachineRegisterInfo; variable
44 BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI);
50 bool &IsAlias, MachineRegisterInfo &MRI);
57 MachineRegisterInfo &MRI, AliasAnalysis *AA);
71 MachineRegisterInfo *MRI;
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 41 void MachineRegisterInfo::Delegate::anchor() {} in anchor()
43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) in MachineRegisterInfo() function in MachineRegisterInfo
62 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
68 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
91 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
121 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
179 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType()
198 void MachineRegisterInfo::clearVirtRegs() { in clearVirtRegs()
255 void MachineRegisterInfo::verifyUseLists() const { in verifyUseLists()
333 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, in moveOperands()
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| H A D | MIRVRegNamerUtils.h | 29 class MachineRegisterInfo; variable
48 MachineRegisterInfo &MRI;
85 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} in VRegRenamer()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.h | 37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeCTPOP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeAtomicCmpxchg128(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AArch64PostLegalizerLowering.cpp | 222 static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV()
251 static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN()
272 static bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP()
288 static bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip()
345 MachineRegisterInfo &MRI, in matchDupFromBuildVector()
563 const MachineRegisterInfo &MRI) { in tryAdjustICmpImmAndPred()
659 MachineInstr &MI, const MachineRegisterInfo &MRI, in matchAdjustICmpImmAndPred()
676 MachineRegisterInfo &MRI = *MIB.getMRI(); in applyAdjustICmpImmAndPred()
686 bool matchDupLane(MachineInstr &MI, MachineRegisterInfo &MRI, in matchDupLane()
738 bool applyDupLane(MachineInstr &MI, MachineRegisterInfo &MRI, in applyDupLane()
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| H A D | AArch64PostLegalizerCombiner.cpp | 54 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd()
97 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd()
113 static bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended()
119 static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended()
125 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine()
238 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyAArch64MulConstCombine()
248 bool matchFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFoldMergeToZext()
256 void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI, in applyFoldMergeToZext()
286 static void applyMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI, in applyMutateAnyExtToZExt()
296 static bool matchSplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchSplitStoreZero128()
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| H A D | AArch64GlobalISelUtils.h | 35 getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
41 const MachineRegisterInfo &MRI);
46 const MachineRegisterInfo &MRI);
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 43 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
55 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
107 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
160 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands()
199 MachineRegisterInfo &MRI) { in canReplaceReg()
213 const MachineRegisterInfo &MRI) { in isTriviallyDead()
735 MachineRegisterInfo &MRI = MF.getRegInfo(); in getFunctionLiveInPhysReg()
1102 const MachineRegisterInfo &MRI) { in getIConstantSplatVal()
1156 const MachineRegisterInfo &MRI, in isConstantScalar()
1258 const MachineRegisterInfo &MRI, Register Reg, in matchUnaryPredicate()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 28 class MachineRegisterInfo; variable
133 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
136 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
139 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
142 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
157 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| H A D | RDFDeadCode.h | 31 class MachineRegisterInfo; variable
35 DeadCodeElimination(DataFlowGraph &dfg, MachineRegisterInfo &mri) in DeadCodeElimination()
53 MachineRegisterInfo &MRI;
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 52 MachineRegisterInfo &MRI) { in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
78 bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSSReg()
86 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock()
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| /openbsd/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 64 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
70 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
72 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
74 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
102 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
154 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
168 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
203 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
240 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 87 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
89 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
91 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
93 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
95 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
103 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
105 bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
117 bool selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
350 MachineRegisterInfo &MRI = MF.getRegInfo(); in select()
513 const MachineRegisterInfo &MRI, in X86SelectAddress()
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| H A D | X86DomainReassignment.cpp | 104 MachineRegisterInfo *MRI) const = 0;
108 MachineRegisterInfo *MRI) const = 0;
119 MachineRegisterInfo *MRI) const override { in convertInstr()
125 MachineRegisterInfo *MRI) const override { in getExtraCost()
153 MachineRegisterInfo *MRI) const override { in convertInstr()
165 MachineRegisterInfo *MRI) const override { in getExtraCost()
181 MachineRegisterInfo *MRI) const override { in convertInstr()
201 MachineRegisterInfo *MRI) const override { in getExtraCost()
236 MachineRegisterInfo *MRI) const override { in getExtraCost()
267 MachineRegisterInfo *MRI) const override { in convertInstr()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 66 MachineRegisterInfo *MRI;
105 const MachineRegisterInfo *MRI) { in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy()
209 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
222 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
241 for (MachineRegisterInfo::use_instr_nodbg_iterator in isProfitableToTransform()
302 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
321 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 31 class MachineRegisterInfo; variable
289 MachineRegisterInfo &MRI;
323 MachineRegisterInfo &MRI);
334 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI()
547 const MachineRegisterInfo &MRI) const;
584 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
647 MachineRegisterInfo &MRI);
731 unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.h | 80 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
85 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
89 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.h | 49 MachineRegisterInfo &MRI) in M68kIncomingValueHandler()
67 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in FormalArgHandler()
72 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
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