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Searched refs:MaskLo (Results 1 – 5 of 5) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1195 SDValue MaskLo, MaskHi; in SplitMask() local
1222 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp() local
1256 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp() local
1894 SDValue MaskLo, MaskHi; in SplitVecRes_VP_LOAD() local
2049 SDValue MaskLo, MaskHi; in SplitVecRes_MLOAD() local
2140 SDValue MaskLo, MaskHi; in SplitVecRes_Gather() local
2276 SDValue MaskLo, MaskHi; in SplitVecRes_UnaryOp() local
3018 SDValue MaskLo, MaskHi; in SplitVecOp_VP_REDUCE() local
3274 SDValue MaskLo, MaskHi; in SplitVecOp_VP_STORE() local
3426 SDValue MaskLo, MaskHi; in SplitVecOp_MSTORE() local
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H A DLegalizeIntegerTypes.cpp1382 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1383 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1386 EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo); in PromoteIntRes_TRUNCATE()
H A DTargetLowering.cpp2219 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2224 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) in SimplifyDemandedBits()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2861 Register MaskLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2864 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo) in selectG_PTRMASK()
2868 .addReg(MaskLo); in selectG_PTRMASK()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25098 static const int MaskLo[] = { 0, 0, 2, 2 }; in LowerVSETCC() local
25100 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()