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Searched refs:MatchInfo (Results 1 – 13 of 13) sorted by relevance

/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h309 ShiftOfShiftedLogic &MatchInfo);
515 BuildFnTy &MatchInfo);
598 void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
617 BuildFnTy &MatchInfo);
635 BuildFnTy &MatchInfo);
646 bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
684 bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo);
688 bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
692 bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
708 bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo);
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.cpp187 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
197 if (fnegFoldsIntoMI(*MatchInfo) && in matchFoldableFneg()
203 switch (MatchInfo->getOpcode()) { in matchFoldableFneg()
217 return mayIgnoreSignedZero(*MatchInfo); in matchFoldableFneg()
287 Builder.setInstrAndDebugLoc(*MatchInfo); in applyFoldableFneg()
291 switch (MatchInfo->getOpcode()) { in applyFoldableFneg()
294 NegateOperand(MatchInfo->getOperand(1)); in applyFoldableFneg()
298 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2)); in applyFoldableFneg()
314 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2)); in applyFoldableFneg()
338 NegateEitherOperand(MatchInfo->getOperand(2), MatchInfo->getOperand(3)); in applyFoldableFneg()
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H A DAMDGPUPreLegalizerCombiner.cpp54 ClampI64ToI16MatchInfo &MatchInfo);
62 ClampI64ToI16MatchInfo &MatchInfo) { in matchClampI64ToI16() argument
76 auto IsApplicableForCombine = [&MatchInfo]() -> bool { in matchClampI64ToI16()
77 const auto Cmp1 = MatchInfo.Cmp1; in matchClampI64ToI16()
78 const auto Cmp2 = MatchInfo.Cmp2; in matchClampI64ToI16()
96 m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16()
98 m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
106 m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
124 Register Src = MatchInfo.Origin; in applyClampI64ToI16()
140 auto MinBoundary = std::min(MatchInfo.Cmp1, MatchInfo.Cmp2); in applyClampI64ToI16()
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H A DAMDGPUPostLegalizerCombiner.cpp63 std::function<void(MachineIRBuilder &)> &MatchInfo);
72 bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
74 const CvtF32UByteMatchInfo &MatchInfo);
228 MatchInfo = [SqrtSrcMI, &MI](MachineIRBuilder &B) { in matchRcpSqrtToRsq()
238 MatchInfo = [RcpSrcMI, &MI](MachineIRBuilder &B) { in matchRcpSqrtToRsq()
250 MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) { in matchCvtF32UByteN() argument
268 MatchInfo.CvtVal = Src0; in matchCvtF32UByteN()
269 MatchInfo.ShiftOffset = ShiftOffset; in matchCvtF32UByteN()
278 MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) { in applyCvtF32UByteN() argument
283 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN()
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H A DAMDGPURegBankCombiner.cpp70 bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
71 bool matchFPMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
74 void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
151 MachineInstr &MI, Med3MatchInfo &MatchInfo) { in matchIntMinMaxToMed3() argument
174 MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg}; in matchIntMinMaxToMed3()
197 MachineInstr &MI, Med3MatchInfo &MatchInfo) { in matchFPMinMaxToMed3() argument
228 MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg}; in matchFPMinMaxToMed3()
322 Med3MatchInfo &MatchInfo) { in applyMed3() argument
324 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)}, in applyMed3()
325 {getAsVgpr(MatchInfo.Val0), getAsVgpr(MatchInfo.Val1), in applyMed3()
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H A DAMDGPUCombinerHelper.h24 bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
25 void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp223 ShuffleVectorPseudo &MatchInfo) { in matchREV() argument
252 ShuffleVectorPseudo &MatchInfo) { in matchTRN() argument
355 MatchInfo = in matchDupFromBuildVector()
441 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
454 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
455 {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst}); in applyEXT()
665 MatchInfo = *MaybeNewImmAndPred; in matchAdjustICmpImmAndPred()
678 MatchInfo.first); in applyAdjustICmpImmAndPred()
681 MI.getOperand(1).setPredicate(MatchInfo.second); in applyAdjustICmpImmAndPred()
733 MatchInfo.first = Opc; in matchDupLane()
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H A DAArch64PostLegalizerCombiner.cpp55 std::tuple<unsigned, LLT, Register> &MatchInfo) { in matchExtractVecEltPairwiseAdd() argument
88 std::get<0>(MatchInfo) = TargetOpcode::G_FADD; in matchExtractVecEltPairwiseAdd()
89 std::get<1>(MatchInfo) = DstTy; in matchExtractVecEltPairwiseAdd()
90 std::get<2>(MatchInfo) = Other->getOperand(0).getReg(); in matchExtractVecEltPairwiseAdd()
98 std::tuple<unsigned, LLT, Register> &MatchInfo) { in applyExtractVecEltPairwiseAdd() argument
99 unsigned Opc = std::get<0>(MatchInfo); in applyExtractVecEltPairwiseAdd()
102 LLT Ty = std::get<1>(MatchInfo); in applyExtractVecEltPairwiseAdd()
103 Register Src = std::get<2>(MatchInfo); in applyExtractVecEltPairwiseAdd()
H A DAArch64PreLegalizerCombiner.cpp66 GISelKnownBits *KB, Register &MatchInfo) { in matchICmpRedundantTrunc() argument
90 MatchInfo = WideReg; in matchICmpRedundantTrunc()
118 std::pair<uint64_t, uint64_t> &MatchInfo) { in matchFoldGlobalOffset() argument
180 MatchInfo = std::make_pair(NewOffset, MinOffset); in matchFoldGlobalOffset()
187 std::pair<uint64_t, uint64_t> &MatchInfo) { in applyFoldGlobalOffset() argument
209 std::tie(Offset, MinOffset) = MatchInfo; in applyFoldGlobalOffset()
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1059 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()
1062 !findPostIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()
1407 MatchInfo.Base = Base; in matchPtrAddImmedChain()
1457 MatchInfo.Imm = in matchShiftImmedChain()
1459 MatchInfo.Reg = Base; in matchShiftImmedChain()
2698 if (!MatchInfo[I]) in applyCombineInsertVecElts()
4093 MatchInfo(Builder); in applyBuildFn()
4100 MatchInfo(Builder); in applyBuildFnNoErase()
4254 MatchInfo = in matchICmpToTrueFalseKnownBits()
5979 MatchInfo = Lo; in matchBuildVectorIdentityFold()
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/openbsd/gnu/llvm/llvm/lib/DebugInfo/LogicalView/Core/
H A DLVOptions.cpp506 bool LVPatterns::matchPattern(StringRef Input, const LVMatchInfo &MatchInfo) { in matchPattern() argument
512 for (const LVMatch &Match : MatchInfo) { in matchPattern()
/openbsd/gnu/llvm/llvm/lib/FileCheck/
H A DFileCheck.cpp1294 SmallVector<StringRef, 4> MatchInfo; in match() local
1298 if (!Regex(RegExToMatch, Flags).match(Buffer, &MatchInfo)) in match()
1302 assert(!MatchInfo.empty() && "Didn't get any match"); in match()
1303 StringRef FullMatch = MatchInfo[0]; in match()
1307 assert(VariableDef.second < MatchInfo.size() && "Internal paren error"); in match()
1309 MatchInfo[VariableDef.second]; in match()
1325 assert(CaptureParenGroup < MatchInfo.size() && "Internal paren error"); in match()
1329 StringRef MatchedValue = MatchInfo[CaptureParenGroup]; in match()
/openbsd/gnu/llvm/llvm/include/llvm/DebugInfo/LogicalView/Core/
H A DLVOptions.h595 bool matchPattern(StringRef Input, const LVMatchInfo &MatchInfo);