Home
last modified time | relevance | path

Searched refs:MinClock (Results 1 – 25 of 31) sorted by relevance

12

/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h25 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
H A Ddcn30_clk_mgr.c341 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
H A Dsmu9_driver_if.h330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
386 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
392 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
H A Ddcn316_smu.h41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_v13_0_4.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
435 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges()
H A Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn315_clk_mgr.c395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
424 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
430 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
464 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
470 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
H A Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
479 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
485 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c728 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
749 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
H A Dsmu_helper.h36 uint16_t MinClock; member
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c416 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
430 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c672 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
686 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c507 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
521 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h574 uint16_t MinClock; member
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1057 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1073 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()

12