1 /* $OpenBSD: if_ngereg.h,v 1.10 2014/08/20 00:59:56 dlg Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_ngereg.h,v 1.7 2002/08/08 18:33:28 ambrisko Exp $ 35 */ 36 37 #define NGE_CSR 0x00 38 #define NGE_CFG 0x04 39 #define NGE_MEAR 0x08 40 #define NGE_PCITST 0x0C 41 #define NGE_ISR 0x10 42 #define NGE_IMR 0x14 43 #define NGE_IER 0x18 44 #define NGE_IHR 0x1C 45 #define NGE_TX_LISTPTR_LO 0x20 46 #define NGE_TX_LISTPTR_HI 0x24 47 #define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO 48 #define NGE_TX_CFG 0x28 49 #define NGE_GPIO 0x2C 50 #define NGE_RX_LISTPTR_LO 0x30 51 #define NGE_RX_LISTPTR_HI 0x34 52 #define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO 53 #define NGE_RX_CFG 0x38 54 #define NGE_PRIOQCTL 0x3C 55 #define NGE_WOLCSR 0x40 56 #define NGE_PAUSECSR 0x44 57 #define NGE_RXFILT_CTL 0x48 58 #define NGE_RXFILT_DATA 0x4C 59 #define NGE_BOOTROM_ADDR 0x50 60 #define NGE_BOOTROM_DATA 0x54 61 #define NGE_SILICONREV 0x58 62 #define NGE_MIBCTL 0x5C 63 #define NGE_MIB_RXERRPKT 0x60 64 #define NGE_MIB_RXERRFCS 0x64 65 #define NGE_MIB_RXERRMISSEDPKT 0x68 66 #define NGE_MIB_RXERRALIGN 0x6C 67 #define NGE_MIB_RXERRSYM 0x70 68 #define NGE_MIB_RXERRGIANT 0x74 69 #define NGE_MIB_RXERRRANGLEN 0x78 70 #define NGE_MIB_RXBADOPCODE 0x7C 71 #define NGE_MIB_RXPAUSEPKTS 0x80 72 #define NGE_MIB_TXPAUSEPKTS 0x84 73 #define NGE_MIB_TXERRSQE 0x88 74 #define NGE_TXPRIOQ_PTR1 0xA0 75 #define NGE_TXPRIOQ_PTR2 0xA4 76 #define NGE_TXPRIOQ_PTR3 0xA8 77 #define NGE_RXPRIOQ_PTR1 0xB0 78 #define NGE_RXPRIOQ_PTR2 0xB4 79 #define NGE_RXPRIOQ_PTR3 0xB8 80 #define NGE_VLAN_IP_RXCTL 0xBC 81 #define NGE_VLAN_IP_TXCTL 0xC0 82 #define NGE_VLAN_DATA 0xC4 83 #define NGE_CLKRUN 0xCC 84 #define NGE_TBI_BMCR 0xE0 85 #define NGE_TBI_BMSR 0xE4 86 #define NGE_TBI_ANAR 0xE8 87 #define NGE_TBI_ANLPAR 0xEC 88 #define NGE_TBI_ANER 0xF0 89 #define NGE_TBI_ESR 0xF4 90 91 /* Control/status register */ 92 #define NGE_CSR_TX_ENABLE 0x00000001 93 #define NGE_CSR_TX_DISABLE 0x00000002 94 #define NGE_CSR_RX_ENABLE 0x00000004 95 #define NGE_CSR_RX_DISABLE 0x00000008 96 #define NGE_CSR_TX_RESET 0x00000010 97 #define NGE_CSR_RX_RESET 0x00000020 98 #define NGE_CSR_SOFTINTR 0x00000080 99 #define NGE_CSR_RESET 0x00000100 100 #define NGE_CSR_TX_PRIOQ_ENB0 0x00000200 101 #define NGE_CSR_TX_PRIOQ_ENB1 0x00000400 102 #define NGE_CSR_TX_PRIOQ_ENB2 0x00000800 103 #define NGE_CSR_TX_PRIOQ_ENB3 0x00001000 104 #define NGE_CSR_RX_PRIOQ_ENB0 0x00002000 105 #define NGE_CSR_RX_PRIOQ_ENB1 0x00004000 106 #define NGE_CSR_RX_PRIOQ_ENB2 0x00008000 107 #define NGE_CSR_RX_PRIOQ_ENB3 0x00010000 108 109 /* Configuration register */ 110 #define NGE_CFG_BIGENDIAN 0x00000001 111 #define NGE_CFG_EXT_125MHZ 0x00000002 112 #define NGE_CFG_BOOTROM_DIS 0x00000004 113 #define NGE_CFG_PERR_DETECT 0x00000008 114 #define NGE_CFG_DEFER_DISABLE 0x00000010 115 #define NGE_CFG_OUTOFWIN_TIMER 0x00000020 116 #define NGE_CFG_SINGLE_BACKOFF 0x00000040 117 #define NGE_CFG_PCIREQ_ALG 0x00000080 118 #define NGE_CFG_EXTSTS_ENB 0x00000100 119 #define NGE_CFG_PHY_DIS 0x00000200 120 #define NGE_CFG_PHY_RST 0x00000400 121 #define NGE_CFG_64BIT_ADDR_ENB 0x00000800 122 #define NGE_CFG_64BIT_DATA_ENB 0x00001000 123 #define NGE_CFG_64BIT_PCI_DET 0x00002000 124 #define NGE_CFG_64BIT_TARG 0x00004000 125 #define NGE_CFG_MWI_DIS 0x00008000 126 #define NGE_CFG_MRM_DIS 0x00010000 127 #define NGE_CFG_TMRTST 0x00020000 128 #define NGE_CFG_PHYINTR_SPD 0x00040000 129 #define NGE_CFG_PHYINTR_LNK 0x00080000 130 #define NGE_CFG_PHYINTR_DUP 0x00100000 131 #define NGE_CFG_MODE_1000 0x00400000 132 #define NGE_CFG_TBI_EN 0x01000000 133 #define NGE_CFG_DUPLEX_STS 0x10000000 134 #define NGE_CFG_SPEED_STS 0x60000000 135 #define NGE_CFG_LINK_STS 0x80000000 136 137 /* MII/EEPROM control register */ 138 #define NGE_MEAR_EE_DIN 0x00000001 139 #define NGE_MEAR_EE_DOUT 0x00000002 140 #define NGE_MEAR_EE_CLK 0x00000004 141 #define NGE_MEAR_EE_CSEL 0x00000008 142 #define NGE_MEAR_MII_DATA 0x00000010 143 #define NGE_MEAR_MII_DIR 0x00000020 144 #define NGE_MEAR_MII_CLK 0x00000040 145 146 #define NGE_EECMD_WRITE 0x140 147 #define NGE_EECMD_READ 0x180 148 #define NGE_EECMD_ERASE 0x1c0 149 150 #define NGE_EE_NODEADDR 0xA 151 #define NGE_EE_GPIOR 0x4 152 153 /* PCI control register */ 154 #define NGE_PCICTL_SRAMADDR 0x0000001F 155 #define NGE_PCICTL_RAMTSTENB 0x00000020 156 #define NGE_PCICTL_TXTSTENB 0x00000040 157 #define NGE_PCICTL_RXTSTENB 0x00000080 158 #define NGE_PCICTL_BMTSTENB 0x00000200 159 #define NGE_PCICTL_RAMADDR 0x001F0000 160 #define NGE_PCICTL_ROMTIME 0x0F000000 161 #define NGE_PCICTL_DISCTEST 0x40000000 162 163 /* Interrupt/status register */ 164 #define NGE_ISR_RX_OK 0x00000001 165 #define NGE_ISR_RX_DESC_OK 0x00000002 166 #define NGE_ISR_RX_ERR 0x00000004 167 #define NGE_ISR_RX_EARLY 0x00000008 168 #define NGE_ISR_RX_IDLE 0x00000010 169 #define NGE_ISR_RX_OFLOW 0x00000020 170 #define NGE_ISR_TX_OK 0x00000040 171 #define NGE_ISR_TX_DESC_OK 0x00000080 172 #define NGE_ISR_TX_ERR 0x00000100 173 #define NGE_ISR_TX_IDLE 0x00000200 174 #define NGE_ISR_TX_UFLOW 0x00000400 175 #define NGE_ISR_MIB_SERVICE 0x00000800 176 #define NGE_ISR_SOFTINTR 0x00001000 177 #define NGE_ISR_PME_EVENT 0x00002000 178 #define NGE_ISR_PHY_INTR 0x00004000 179 #define NGE_ISR_HIBITS 0x00008000 180 #define NGE_ISR_RX_FIFO_OFLOW 0x00010000 181 #define NGE_ISR_TGT_ABRT 0x00020000 182 #define NGE_ISR_BM_ABRT 0x00040000 183 #define NGE_ISR_SYSERR 0x00080000 184 #define NGE_ISR_PARITY_ERR 0x00100000 185 #define NGE_ISR_RX_RESET_DONE 0x00200000 186 #define NGE_ISR_TX_RESET_DONE 0x00400000 187 #define NGE_ISR_RX_PRIOQ_DESC0 0x00800000 188 #define NGE_ISR_RX_PRIOQ_DESC1 0x01000000 189 #define NGE_ISR_RX_PRIOQ_DESC2 0x02000000 190 #define NGE_ISR_RX_PRIOQ_DESC3 0x04000000 191 #define NGE_ISR_TX_PRIOQ_DESC0 0x08000000 192 #define NGE_ISR_TX_PRIOQ_DESC1 0x10000000 193 #define NGE_ISR_TX_PRIOQ_DESC2 0x20000000 194 #define NGE_ISR_TX_PRIOQ_DESC3 0x40000000 195 196 /* Interrupt mask register */ 197 #define NGE_IMR_RX_OK 0x00000001 198 #define NGE_IMR_RX_DESC_OK 0x00000002 199 #define NGE_IMR_RX_ERR 0x00000004 200 #define NGE_IMR_RX_EARLY 0x00000008 201 #define NGE_IMR_RX_IDLE 0x00000010 202 #define NGE_IMR_RX_OFLOW 0x00000020 203 #define NGE_IMR_TX_OK 0x00000040 204 #define NGE_IMR_TX_DESC_OK 0x00000080 205 #define NGE_IMR_TX_ERR 0x00000100 206 #define NGE_IMR_TX_IDLE 0x00000200 207 #define NGE_IMR_TX_UFLOW 0x00000400 208 #define NGE_IMR_MIB_SERVICE 0x00000800 209 #define NGE_IMR_SOFTINTR 0x00001000 210 #define NGE_IMR_PME_EVENT 0x00002000 211 #define NGE_IMR_PHY_INTR 0x00004000 212 #define NGE_IMR_HIBITS 0x00008000 213 #define NGE_IMR_RX_FIFO_OFLOW 0x00010000 214 #define NGE_IMR_TGT_ABRT 0x00020000 215 #define NGE_IMR_BM_ABRT 0x00040000 216 #define NGE_IMR_SYSERR 0x00080000 217 #define NGE_IMR_PARITY_ERR 0x00100000 218 #define NGE_IMR_RX_RESET_DONE 0x00200000 219 #define NGE_IMR_TX_RESET_DONE 0x00400000 220 #define NGE_IMR_RX_PRIOQ_DESC0 0x00800000 221 #define NGE_IMR_RX_PRIOQ_DESC1 0x01000000 222 #define NGE_IMR_RX_PRIOQ_DESC2 0x02000000 223 #define NGE_IMR_RX_PRIOQ_DESC3 0x04000000 224 #define NGE_IMR_TX_PRIOQ_DESC0 0x08000000 225 #define NGE_IMR_TX_PRIOQ_DESC1 0x10000000 226 #define NGE_IMR_TX_PRIOQ_DESC2 0x20000000 227 #define NGE_IMR_TX_PRIOQ_DESC3 0x40000000 228 229 #define NGE_INTRS \ 230 (NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\ 231 NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\ 232 NGE_IMR_SYSERR|NGE_IMR_PHY_INTR|\ 233 NGE_IMR_RX_DESC_OK|NGE_IMR_TX_DESC_OK|\ 234 NGE_IMR_RX_IDLE|NGE_IMR_RX_FIFO_OFLOW) 235 236 /* Interrupt enable register */ 237 #define NGE_IER_INTRENB 0x00000001 238 239 /* Interrupt moderation timer register */ 240 #define NGE_IHR_HOLDOFF 0x000000FF 241 #define NGE_IHR_HOLDCTL 0x00000100 242 243 /* Transmit configuration register */ 244 #define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */ 245 #define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */ 246 #define NGE_1000MB_BURST_DIS 0x00080000 247 #define NGE_TXCFG_DMABURST 0x00700000 248 #define NGE_TXCFG_ECRETRY 0x00800000 249 #define NGE_TXCFG_AUTOPAD 0x10000000 250 #define NGE_TXCFG_LOOPBK 0x20000000 251 #define NGE_TXCFG_IGN_HBEAT 0x40000000 252 #define NGE_TXCFG_IGN_CARR 0x80000000 253 254 #define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH) 255 #define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH) 256 257 #define NGE_TXDMA_1024BYTES 0x00000000 258 #define NGE_TXDMA_8BYTES 0x00100000 259 #define NGE_TXDMA_16BYTES 0x00200000 260 #define NGE_TXDMA_32BYTES 0x00300000 261 #define NGE_TXDMA_64BYTES 0x00400000 262 #define NGE_TXDMA_128BYTES 0x00500000 263 #define NGE_TXDMA_256BYTES 0x00600000 264 #define NGE_TXDMA_512BYTES 0x00700000 265 266 #define NGE_TXCFG \ 267 (NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\ 268 NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400)) 269 270 /* GPIO register */ 271 #define NGE_GPIO_GP1_OUT 0x00000001 272 #define NGE_GPIO_GP2_OUT 0x00000002 273 #define NGE_GPIO_GP3_OUT 0x00000004 274 #define NGE_GPIO_GP4_OUT 0x00000008 275 #define NGE_GPIO_GP5_OUT 0x00000010 276 #define NGE_GPIO_GP1_OUTENB 0x00000020 277 #define NGE_GPIO_GP2_OUTENB 0x00000040 278 #define NGE_GPIO_GP3_OUTENB 0x00000080 279 #define NGE_GPIO_GP4_OUTENB 0x00000100 280 #define NGE_GPIO_GP5_OUTENB 0x00000200 281 #define NGE_GPIO_GP1_IN 0x00000400 282 #define NGE_GPIO_GP2_IN 0x00000800 283 #define NGE_GPIO_GP3_IN 0x00001000 284 #define NGE_GPIO_GP4_IN 0x00002000 285 #define NGE_GPIO_GP5_IN 0x00004000 286 287 /* Receive configuration register */ 288 #define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 289 #define NGE_RXCFG_DMABURST 0x00700000 290 #define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */ 291 #define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */ 292 #define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */ 293 #define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */ 294 #define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */ 295 #define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */ 296 297 #define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH) 298 299 #define NGE_RXDMA_1024BYTES 0x00000000 300 #define NGE_RXDMA_8BYTES 0x00100000 301 #define NGE_RXDMA_16BYTES 0x00200000 302 #define NGE_RXDMA_32YTES 0x00300000 303 #define NGE_RXDMA_64BYTES 0x00400000 304 #define NGE_RXDMA_128BYTES 0x00500000 305 #define NGE_RXDMA_256BYTES 0x00600000 306 #define NGE_RXDMA_512BYTES 0x00700000 307 308 #define NGE_RXCFG \ 309 (NGE_RXCFG_DRAIN(64)|NGE_RXDMA_256BYTES|\ 310 NGE_RXCFG_RX_GIANTS|NGE_RXCFG_RX_NOCRC) 311 312 /* Priority queue control */ 313 #define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001 314 #define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002 315 #define NGE_PRIOQCTL_RXPRIO 0x0000000C 316 317 #define NGE_RXPRIOQ_DISABLED 0x00000000 318 #define NGE_RXPRIOQ_TWOQS 0x00000004 319 #define NGE_RXPRIOQ_THREEQS 0x00000008 320 #define NGE_RXPRIOQ_FOURQS 0x0000000C 321 322 /* Wake On LAN command/status register */ 323 #define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001 324 #define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002 325 #define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004 326 #define NGR_WOLCSR_WAKE_ON_BROADCAST 0x00000008 327 #define NGE_WOLCSR_WAKE_ON_ARP 0x00000010 328 #define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020 329 #define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040 330 #define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080 331 #define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100 332 #define NGE_WOLCSR_SECUREON_ENB 0x00000200 333 #define NGE_WOLCSR_SECUREON_HACK 0x00200000 334 #define NGE_WOLCSR_PHYINTR 0x00400000 335 #define NGE_WOLCSR_UNICAST 0x00800000 336 #define NGE_WOLCSR_MULTICAST 0x01000000 337 #define NGE_WOLCSR_BROADCAST 0x02000000 338 #define NGE_WOLCSR_ARP_RCVD 0x04000000 339 #define NGE_WOLCSR_PAT0_MATCH 0x08000000 340 #define NGE_WOLCSR_PAT1_MATCH 0x10000000 341 #define NGE_WOLCSR_PAT2_MATCH 0x20000000 342 #define NGE_WOLCSR_PAT3_MATCH 0x40000000 343 #define NGE_WOLCSR_MAGICPKT 0x80000000 344 345 /* Pause control/status register */ 346 #define NGE_PAUSECSR_CNT 0x0000FFFF 347 #define NGE_PAUSECSR_PFRAME_SENT 0x00020000 348 #define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000 349 #define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000 350 #define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000 351 #define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000 352 #define NGE_PAUSECSR_PFRAME_RCVD 0x08000000 353 #define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000 354 #define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */ 355 #define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */ 356 #define NGE_PAUSECSR_PAUSE_ENB 0x80000000 357 358 /* Receive filter/match control message */ 359 #define MGE_RXFILTCTL_ADDR 0x000003FF 360 #define NGE_RXFILTCTL_ULMASK 0x00080000 361 #define NGE_RXFILTCTL_UCHASH 0x00100000 362 #define NGE_RXFILTCTL_MCHASH 0x00200000 363 #define NGE_RXFILTCTL_ARP 0x00400000 364 #define NGE_RXFILTCTL_PMATCH0 0x00800000 365 #define NGE_RXFILTCTL_PMATCH1 0x01000000 366 #define NGE_RXFILTCTL_PMATCH2 0x02000000 367 #define NGE_RXFILTCTL_PMATCH3 0x04000000 368 #define NGE_RXFILTCTL_PERFECT 0x08000000 369 #define NGE_RXFILTCTL_ALLPHYS 0x10000000 370 #define NGE_RXFILTCTL_ALLMULTI 0x20000000 371 #define NGE_RXFILTCTL_BROAD 0x40000000 372 #define NGE_RXFILTCTL_ENABLE 0x80000000 373 374 375 #define NGE_FILTADDR_PAR0 0x00000000 376 #define NGE_FILTADDR_PAR1 0x00000002 377 #define NGE_FILTADDR_PAR2 0x00000004 378 #define NGE_FILTADDR_PMATCH0 0x00000006 379 #define NGE_FILTADDR_PMATCH1 0x00000008 380 #define NGE_FILTADDR_SOPASS0 0x0000000A 381 #define NGE_FILTADDR_SOPASS1 0x0000000C 382 #define NGE_FILTADDR_SOPASS2 0x0000000E 383 #define NGE_FILTADDR_FMEM_LO 0x00000100 384 #define NGE_FILTADDR_FMEM_HI 0x000003FE 385 #define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */ 386 #define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */ 387 #define NGE_MCAST_FILTER_LEN 256 /* bytes */ 388 #define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */ 389 #define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */ 390 #define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */ 391 #define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */ 392 393 /* MIB control register */ 394 #define NGE_MIBCTL_WARNTEST 0x00000001 395 #define NGE_MIBCTL_FREEZE_CNT 0x00000002 396 #define NGE_MIBCTL_CLEAR_CNT 0x00000004 397 #define NGE_MIBCTL_STROBE_CNT 0x00000008 398 399 /* VLAN/IP RX control register */ 400 #define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001 401 #define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002 402 #define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004 403 #define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008 404 #define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010 405 #define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020 406 #define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040 407 #define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080 408 409 /* VLAN/IP TX control register */ 410 #define NGE_VIPTXCTL_TAG_ALL 0x00000001 411 #define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002 412 #define NGE_VIPTXCTL_CSUM_ALL 0x00000004 413 #define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008 414 415 /* VLAN data register */ 416 #define NGE_VLANDATA_VTYPE 0x0000FFFF 417 #define NGE_VLANDATA_VTCI 0xFFFF0000 418 419 /* Clockrun register */ 420 #define NGE_CLKRUN_PMESTS 0x00008000 421 #define NGE_CLKRUN_PMEENB 0x00000100 422 #define NGE_CLNRUN_CLKRUN_ENB 0x00000001 423 424 425 /* TBI BMCR */ 426 #define NGE_TBIBMCR_RESTART_ANEG 0x00000200 427 #define NGE_TBIBMCR_ENABLE_ANEG 0x00001000 428 #define NGE_TBIBMCR_LOOPBACK 0x00004000 429 430 /* TBI BMSR */ 431 #define NGE_TBIBMSR_ANEG_DONE 0x00000004 432 #define NGE_TBIBMSR_LINKSTAT 0x00000020 433 434 /* TBI ANAR */ 435 #define NGE_TBIANAR_HDX 0x00000020 436 #define NGE_TBIANAR_FDX 0x00000040 437 #define NGE_TBIANAR_PS1 0x00000080 438 #define NGE_TBIANAR_PS2 0x00000100 439 #define NGE_TBIANAR_PCAP 0x00000180 440 #define NGE_TBIANAR_REMFAULT 0x00003000 441 #define NGE_TBIANAR_NEXTPAGE 0x00008000 442 443 /* TBI ANLPAR */ 444 #define NGE_TBIANLPAR_HDX 0x00000020 445 #define NGE_TBIANLPAR_FDX 0x00000040 446 #define NGE_TBIANLPAR_PS1 0x00000080 447 #define NGE_TBIANLPAR_PS2 0x00000100 448 #define NGE_TBIANLPAR_PCAP 0x00000180 449 #define NGE_TBIANLPAR_REMFAULT 0x00003000 450 #define NGE_TBIANLPAR_NEXTPAGE 0x00008000 451 452 /* TBI ANER */ 453 #define NGE_TBIANER_PAGERCVD 0x00000002 454 #define NGE_TBIANER_NEXTPGABLE 0x00000004 455 456 /* TBI EXTSTS */ 457 #define NGE_TBIEXTSTS_HXD 0x00004000 458 #define NGE_TBIEXTSTS_FXD 0x00008000 459 460 /* 461 * DMA descriptor structures. The RX and TX descriptor formats are 462 * deliberately designed to be similar to facilitate passing them between 463 * RX and TX queues on multiple controllers, in the case where you have 464 * multiple MACs in a switching configuration. With the 83820, the pointer 465 * values can be either 64 bits or 32 bits depending on how the chip is 466 * configured. For the 83821, the fields are always 32-bits. There is 467 * also an optional extended status field for VLAN and TCP/IP checksum 468 * functions. We use the checksum feature so we enable the use of this 469 * field. Descriptors must be 64-bit aligned. 470 * After this, we include some additional structure members for 471 * use by the driver. Note that for this structure will be a different 472 * size on the alpha, but that's okay as long as it's a multiple of 4 473 * bytes in size. 474 * 475 */ 476 struct nge_desc_64 { 477 /* Hardware descriptor section */ 478 u_int32_t nge_next_lo; 479 u_int32_t nge_next_hi; 480 u_int32_t nge_ptr_lo; 481 u_int32_t nge_ptr_hi; 482 u_int32_t nge_cmdsts; 483 #define nge_rxstat nge_cmdsts 484 #define nge_txstat nge_cmdsts 485 #define nge_ctl nge_cmdsts 486 u_int32_t nge_extsts; 487 /* Driver software section */ 488 union { 489 struct mbuf *nge_mbuf; 490 u_int64_t nge_dummy; 491 } nge_mb_u; 492 union { 493 struct nge_desc_64 *nge_nextdesc; 494 u_int64_t nge_dummy; 495 } nge_nd_u; 496 }; 497 498 struct nge_desc_32 { 499 /* Hardware descriptor section */ 500 u_int32_t nge_next; 501 u_int32_t nge_ptr; 502 u_int32_t nge_cmdsts; 503 #define nge_rxstat nge_cmdsts 504 #define nge_txstat nge_cmdsts 505 #define nge_ctl nge_cmdsts 506 u_int32_t nge_extsts; 507 /* Driver software section */ 508 union { 509 struct mbuf *nge_mbuf; 510 u_int64_t nge_dummy; 511 } nge_mb_u; 512 union { 513 struct nge_desc_32 *nge_nextdesc; 514 u_int64_t nge_dummy; 515 } nge_nd_u; 516 }; 517 518 #define nge_desc nge_desc_32 519 #define nge_mbuf nge_mb_u.nge_mbuf 520 #define nge_nextdesc nge_nd_u.nge_nextdesc 521 522 #define NGE_CMDSTS_BUFLEN 0x0000FFFF 523 #define NGE_CMDSTS_PKT_OK 0x08000000 524 #define NGE_CMDSTS_CRC 0x10000000 525 #define NGE_CMDSTS_INTR 0x20000000 526 #define NGE_CMDSTS_MORE 0x40000000 527 #define NGE_CMDSTS_OWN 0x80000000 528 529 #define NGE_LASTDESC(x) (!((x)->nge_ctl & NGE_CMDSTS_MORE))) 530 #define NGE_OWNDESC(x) ((x)->nge_ctl & NGE_CMDSTS_OWN) 531 #define NGE_INC(x, y) (x) = (x + 1) % y 532 #define NGE_RXBYTES(x) ((x)->nge_ctl & NGE_CMDSTS_BUFLEN) 533 534 #define NGE_RXSTAT_RANGELENERR 0x00010000 535 #define NGE_RXSTAT_LOOPBK 0x00020000 536 #define NGE_RXSTAT_ALIGNERR 0x00040000 537 #define NGE_RXSTAT_CRCERR 0x00080000 538 #define NGE_RXSTAT_SYMBOLERR 0x00100000 539 #define NGE_RXSTAT_RUNT 0x00200000 540 #define NGE_RXSTAT_GIANT 0x00400000 541 #define NGE_RXSTAT_DSTCLASS 0x01800000 542 #define NGE_RXSTAT_OVERRUN 0x02000000 543 #define NGE_RXSTAT_RX_ABORT 0x04000000 544 545 #define NGE_DSTCLASS_REJECT 0x00000000 546 #define NGE_DSTCLASS_UNICAST 0x00800000 547 #define NGE_DSTCLASS_MULTICAST 0x01000000 548 #define NGE_DSTCLASS_BROADCAST 0x02000000 549 550 #define NGE_TXSTAT_COLLCNT 0x000F0000 551 #define NGE_TXSTAT_EXCESSCOLLS 0x00100000 552 #define NGE_TXSTAT_OUTOFWINCOLL 0x00200000 553 #define NGE_TXSTAT_EXCESS_DEFER 0x00400000 554 #define NGE_TXSTAT_DEFERED 0x00800000 555 #define NGE_TXSTAT_CARR_LOST 0x01000000 556 #define NGE_TXSTAT_UNDERRUN 0x02000000 557 #define NGE_TXSTAT_TX_ABORT 0x04000000 558 559 #define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF 560 #define NGE_TXEXTSTS_VLANPKT 0x00010000 561 #define NGE_TXEXTSTS_IPCSUM 0x00020000 562 #define NGE_TXEXTSTS_TCPCSUM 0x00080000 563 #define NGE_TXEXTSTS_UDPCSUM 0x00200000 564 565 #define NGE_RXEXTSTS_VTCI 0x0000FFFF 566 #define NGE_RXEXTSTS_VLANPKT 0x00010000 567 #define NGE_RXEXTSTS_IPPKT 0x00020000 568 #define NGE_RXEXTSTS_IPCSUMERR 0x00040000 569 #define NGE_RXEXTSTS_TCPPKT 0x00080000 570 #define NGE_RXEXTSTS_TCPCSUMERR 0x00100000 571 #define NGE_RXEXTSTS_UDPPKT 0x00200000 572 #define NGE_RXEXTSTS_UDPCSUMERR 0x00400000 573 574 #define NGE_RX_LIST_CNT 128 575 #define NGE_TX_LIST_CNT 128 576 577 struct nge_list_data { 578 struct nge_desc nge_rx_list[NGE_RX_LIST_CNT]; 579 struct nge_desc nge_tx_list[NGE_TX_LIST_CNT]; 580 }; 581 582 583 /* 584 * NatSemi PCI vendor ID. 585 */ 586 #define NGE_VENDORID 0x100B 587 588 /* 589 * 83820/83821 PCI device IDs 590 */ 591 #define NGE_DEVICEID 0x0022 592 593 struct nge_type { 594 u_int16_t nge_vid; 595 u_int16_t nge_did; 596 char *nge_name; 597 }; 598 599 struct nge_mii_frame { 600 u_int8_t mii_stdelim; 601 u_int8_t mii_opcode; 602 u_int8_t mii_phyaddr; 603 u_int8_t mii_regaddr; 604 u_int8_t mii_turnaround; 605 u_int16_t mii_data; 606 }; 607 608 /* 609 * MII constants 610 */ 611 #define NGE_MII_STARTDELIM 0x01 612 #define NGE_MII_READOP 0x02 613 #define NGE_MII_WRITEOP 0x01 614 #define NGE_MII_TURNAROUND 0x02 615 616 #define NGE_JUMBO_FRAMELEN 9018 617 #define NGE_JUMBO_MTU (NGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 618 #define NGE_JSLOTS 384 619 620 #define NGE_JRAWLEN (NGE_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 621 #define NGE_JLEN (NGE_JRAWLEN + (sizeof(u_int64_t) - \ 622 (NGE_JRAWLEN % sizeof(u_int64_t)))) 623 #define NGE_MCLBYTES (NGE_JLEN - sizeof(u_int64_t)) 624 #define NGE_JPAGESZ PAGE_SIZE 625 #define NGE_RESID (NGE_JPAGESZ - (NGE_JLEN * NGE_JSLOTS) % NGE_JPAGESZ) 626 #define NGE_JMEM ((NGE_JLEN * NGE_JSLOTS) + NGE_RESID) 627 628 struct nge_ring_data { 629 int nge_rx_prod; 630 int nge_tx_prod; 631 int nge_tx_cons; 632 int nge_tx_cnt; 633 }; 634 635 struct nge_softc { 636 struct device sc_dv; 637 struct arpcom arpcom; /* interface info */ 638 bus_space_handle_t nge_bhandle; 639 bus_space_tag_t nge_btag; 640 void *nge_intrhand; 641 struct mii_data nge_mii; 642 int nge_if_flags; 643 u_int8_t nge_type; 644 u_int8_t nge_link; 645 u_int8_t nge_width; 646 bus_dma_tag_t sc_dmatag; 647 #define NGE_WIDTH_32BITS 0 648 #define NGE_WIDTH_64BITS 1 649 struct nge_list_data *nge_ldata; 650 struct nge_ring_data nge_cdata; 651 struct timeout nge_timeout; 652 u_int8_t nge_tbi; 653 struct ifmedia nge_ifmedia; 654 }; 655 656 /* 657 * register space access macros 658 */ 659 #define CSR_WRITE_4(sc, reg, val) \ 660 bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val) 661 662 #define CSR_READ_4(sc, reg) \ 663 bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg) 664 665 #define NGE_TIMEOUT 1000 666 #define NGE_MIN_FRAMELEN 60 667 668 /* 669 * PCI low memory base and low I/O base register, and 670 * other PCI registers. 671 */ 672 673 #define NGE_PCI_VENDOR_ID 0x00 674 #define NGE_PCI_DEVICE_ID 0x02 675 #define NGE_PCI_COMMAND 0x04 676 #define NGE_PCI_STATUS 0x06 677 #define NGE_PCI_REVID 0x08 678 #define NGE_PCI_CLASSCODE 0x09 679 #define NGE_PCI_CACHELEN 0x0C 680 #define NGE_PCI_LATENCY_TIMER 0x0D 681 #define NGE_PCI_HEADER_TYPE 0x0E 682 #define NGE_PCI_LOIO 0x10 683 #define NGE_PCI_LOMEM 0x14 684 #define NGE_PCI_BIOSROM 0x30 685 #define NGE_PCI_INTLINE 0x3C 686 #define NGE_PCI_INTPIN 0x3D 687 #define NGE_PCI_MINGNT 0x3E 688 #define NGE_PCI_MINLAT 0x0F 689 #define NGE_PCI_RESETOPT 0x48 690 #define NGE_PCI_EEPROM_DATA 0x4C 691 692 /* power management registers */ 693 #define NGE_PCI_CAPID 0x50 /* 8 bits */ 694 #define NGE_PCI_NEXTPTR 0x51 /* 8 bits */ 695 #define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 696 #define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 697 698 #define NGE_PME_EN 0x0010 699 #define NGE_PME_STATUS 0x8000 700 701 #ifdef __alpha__ 702 #undef vtophys 703 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)va) 704 #endif 705