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Searched refs:NUM_DCEFCLK_DPM_LEVELS (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h101 #define NUM_DCEFCLK_DPM_LEVELS 4 macro
111 DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
H A Dsmu9_driver_if.h43 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
H A Dsmu11_driver_if.h44 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
427 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h42 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
55 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
314 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_navi10.h41 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
590 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
H A Dsmu11_driver_if_sienna_cichlid.h40 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
686 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
1046 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_processpptables.c340 for (i = 0; i < NUM_DCEFCLK_DPM_LEVELS; i++)
H A Dsmu10_hwmgr.c510 NUM_DCEFCLK_DPM_LEVELS, in smu10_populate_clock_table()