| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 89 unsigned Opc1, Opc2; in processBlock() local
94 Opc1 = PPC::ADDItlsgdL; in processBlock()
98 Opc1 = PPC::ADDItlsldL; in processBlock()
102 Opc1 = PPC::ADDItlsgdL32; in processBlock()
106 Opc1 = PPC::ADDItlsldL32; in processBlock()
121 Opc1 = PPC::PADDI8pc; in processBlock()
149 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); in processBlock()
153 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); in processBlock()
|
| H A D | PPCISelDAGToDAG.cpp | 6025 unsigned Opc1, Opc2, Opc3; in Select() local
6029 Opc1 = PPC::VSPLTISB; in Select()
6034 Opc1 = PPC::VSPLTISH; in Select()
6040 Opc1 = PPC::VSPLTISW; in Select()
6054 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
6066 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
6068 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
6080 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
6082 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
|
| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
|
| H A D | Mips16ISelLowering.cpp | 571 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, in emitSelT16() argument
609 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
636 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
675 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
|
| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | GCNCreateVOPD.cpp | 64 unsigned Opc1 = FirstMI->getOpcode(); in doReplace() local
66 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1), in doReplace()
|
| H A D | GCNHazardRecognizer.cpp | 2209 unsigned Opc1 = MI1->getOpcode(); in checkMAIHazards90A() local
2212 if (!isDGEMM(Opc) && (!ST.hasGFX940Insts() && isDGEMM(Opc1))) { in checkMAIHazards90A()
2217 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || in checkMAIHazards90A()
2218 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64)) in checkMAIHazards90A()
2224 switch (Opc1) { in checkMAIHazards90A()
2278 switch (Opc1) { in checkMAIHazards90A()
|
| H A D | SIInstrInfo.cpp | 85 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
88 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
179 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
182 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
185 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
208 Offset1Idx -= get(Opc1).NumDefs; in areLoadsFromSameBasePtr()
214 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
217 !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase)) in areLoadsFromSameBasePtr()
247 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
256 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
[all …]
|
| /openbsd/gnu/llvm/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ContainerModeling.cpp | 126 BinaryOperator::Opcode Opc1,
960 BinaryOperator::Opcode Opc1, in invalidateIteratorPositions() argument
964 return compare(State, Pos.getOffset(), Offset1, Opc1) && in invalidateIteratorPositions()
|
| /openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 2244 BinaryOperator::BinaryOps Opc1 = B1->getOpcode(); in foldSelectShuffle() local
2246 if (ConstantsAreOp1 && Opc0 != Opc1) { in foldSelectShuffle()
2250 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) in foldSelectShuffle()
2258 Opc1 = AltB1.Opcode; in foldSelectShuffle()
2263 if (Opc0 != Opc1 || !C0 || !C1) in foldSelectShuffle()
|
| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 7194 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
7196 switch (Opc1) { in areLoadsFromSameBasePtr()
7395 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
7397 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
7400 switch (Opc1) { in shouldScheduleLoadsNear()
|
| H A D | X86ISelLowering.cpp | 26992 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27026 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27108 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27186 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27199 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
27219 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
27222 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27241 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27259 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
27484 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
[all …]
|
| H A D | X86IntrinsicsInfo.h | 48 uint16_t Opc1; member
|
| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 409 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc1), TmpReg) in materializeFP()
|
| /openbsd/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 7815 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
7824 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
7842 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
7844 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
|