1 /* $OpenBSD: p9000.h,v 1.4 2007/05/22 04:14:03 jsg Exp $ */ 2 /* 3 * Copyright (c) 2003, Miodrag Vallat. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Weitek Power9000 and Power9100 definitions. 29 * 30 * Although the datasheet is not available anymore, a good source of 31 * documentation is several code examples in XFree86 3.x (vga256/p9x00) and the 32 * {Net,Open}BSD source trees. 33 */ 34 35 /* 36 * Frame buffer control registers 37 * 38 * Offsets below are relative to the following locations: 39 * P9000 at 0x00100000, P9100 at 0x000000 40 */ 41 42 /* 43 * System control registers 44 */ 45 46 /* System configuration register */ 47 #define P9000_SYSTEM_CONFIG 0x00000004 48 49 #define SCR_PIXEL_MASK 0x1c000000 50 #define SCR_PIXEL_8BPP 0x08000000 51 #define SCR_PIXEL_16BPP 0x0c000000 52 #define SCR_PIXEL_24BPP 0x1c000000 53 #define SCR_PIXEL_32BPP 0x14000000 54 #define SCR_SWAP_WORDS 0x00002000 55 #define SCR_SWAP_BYTES 0x00001000 56 #define SCR_SWAP_BITS 0x00000800 57 #define SCR_READ_BUFFER_MASK 0x00000400 58 #define SCR_WRITE_BUFFER_MASK 0x00000200 59 #define SCR_ID_MASK 0x00000007 60 #define SCR_SC(sc0, sc1, sc2, sc3) \ 61 (((sc0) << 14) | ((sc1) << 17) | ((sc2) << 20) | ((sc3) << 29)) 62 63 /* Interrupt status register */ 64 #define P9000_INTERRUPT 0x00000008 65 66 /* Interrupt enable register */ 67 #define P9000_INTERRUPT_ENABLE 0x0000000c 68 69 #define IER_MASTER_ENABLE 0x00000080 70 #define IER_MASTER_INTERRUPT 0x00000040 71 #define IER_VBLANK_ENABLE 0x00000020 72 #define IER_VBLANK_INTERRUPT 0x00000010 73 #define IER_PICK_ENABLE 0x00000008 74 #define IER_PICK_INTERRUPT 0x00000004 75 #define IER_IDLE_ENABLE 0x00000002 76 #define IER_IDLE_INTERRUPT 0x00000001 77 78 /* Alternate read bank register (bits 16-22) */ 79 #define P9000_ALTBANK_READ 0x00000010 80 81 /* Alternate write bank register (bits 16-22) */ 82 #define P9000_ALTBANK_WRITE 0x00000014 83 84 /* 85 * Video control registers 86 */ 87 88 /* Horizontal counter */ 89 #define P9000_HCR 0x00000104 90 /* Horizontal total */ 91 #define P9000_HTR 0x00000108 92 /* Horizontal sync rising edge */ 93 #define P9000_HSRE 0x0000010c 94 /* Horizontal blank rising edge */ 95 #define P9000_HBRE 0x00000110 96 /* Horizontal blank falling edge */ 97 #define P9000_HBFE 0x00000114 98 /* Horizontal counter preload */ 99 #define P9000_HCP 0x00000118 100 101 /* Vertical counter */ 102 #define P9000_VCR 0x0000011c 103 /* Vertical length */ 104 #define P9000_VL 0x00000120 105 /* Vertical sync rising edge */ 106 #define P9000_VSRE 0x00000124 107 /* Vertical blank rising edge */ 108 #define P9000_VBRE 0x00000128 109 /* Vertical blank falling edge */ 110 #define P9000_VBFE 0x0000012c 111 /* Vertical counter preload */ 112 #define P9000_VCP 0x00000130 113 114 /* Screen repaint address */ 115 #define P9000_SRA 0x00000134 116 /* Screen repaint timing control #1 */ 117 #define P9000_SRTC1 0x00000138 118 119 #define SRTC1_VSYNC_INTERNAL 0x00000100 120 #define SRTC1_HSYNC_INTERNAL 0x00000080 121 #define SRTC1_VIDEN 0x00000020 122 #define SRTC1_RESTRICTED 0x00000010 123 #define SRTC1_BUFFER1 0x00000008 124 125 /* QSF counter. Film at 11 */ 126 #define P9000_QSF 0x0000013c 127 /* Screen repaint timing control #2 */ 128 #define P9000_SRTC2 0x00000140 129 130 /* 131 * VRAM control registers 132 */ 133 134 /* Memory configuration */ 135 #define P9000_MCR 0x00000184 136 /* Refresh period */ 137 #define P9000_REFRESH_PERIOD 0x00000188 138 /* Refresh count */ 139 #define P9000_REFRESH_COUNT 0x0000018c 140 /* RAS low maximum */ 141 #define P9000_RASLOW_MAXIMUM 0x00000190 142 /* RAS low current */ 143 #define P9000_RASLOW_CURRENT 0x00000194 144 /* RAMDAC free FIFO (P9100 only, bits 12-15) and power-up configuration */ 145 #define P9000_POWERUP_CONFIG 0x00000198 146 #define P9100_FREE_FIFO 0x00000198 147 148 /* 149 * RAMDAC registers (P9100 only) 150 */ 151 152 #define P9100_RAMDAC_REGISTER(index) (0x00000200 + ((index) << 2)) 153 154 155 /* 156 * Accelerated features 157 * 158 * Offsets below are relative to the following locations: 159 * P9000 at 0x00180000, P9100 at 0x002000 160 */ 161 162 /* 163 * Parameter engine 164 */ 165 166 /* Status register */ 167 #define P9000_PE_STATUS 0x00000000 168 #define STATUS_QUAD_BUSY 0x80000000 169 #define STATUS_BLIT_BUSY 0x40000000 170 #define STATUS_PICK_DETECTED 0x00000080 171 #define STATUS_PIXEL_ERROR 0x00000040 172 #define STATUS_BLIT_ERROR 0x00000020 173 #define STATUS_QUAD_ERROR 0x00000010 174 #define STATUS_QUAD_CONCAVE 0x00000008 175 #define STATUS_QUAD_OUTSIDE 0x00000004 176 #define STATUS_QUAD_INSIDE 0x00000002 177 #define STATUS_QUAD_STRADDLE 0x00000001 178 179 /* Engine arguments / operation triggers */ 180 #define P9000_PE_BLIT 0x00000004 181 #define P9000_PE_QUAD 0x00000008 182 #define P9000_PE_PIXEL8 0x0000000c 183 #define P9000_PE_NEXTPIXELS 0x00000014 184 #define P9000_PE_PIXEL1(index) (0x00000080 + ((index) << 2)) 185 186 /* Control and conditions registers */ 187 188 /* Out of range */ 189 #define P9000_PE_OOR 0x00000184 190 /* Index register (0-3, for meta coordinates) */ 191 #define P9000_PE_INDEX 0x0000018c 192 /* Window offset (16x16)*/ 193 #define P9000_PE_WINOFFSET 0x00000190 194 /* Clipping window */ 195 #define P9000_PE_WINMIN 0x00000194 196 #define P9000_PE_WINMAX 0x00000198 197 /* X Clip register */ 198 #define P9000_X_CLIPPING 0x000001a0 199 /* Y Clip register */ 200 #define P9000_Y_CLIPPING 0x000001a4 201 /* X Edge Less Than register */ 202 #define P9000_X_EDGE_LESS 0x000001a8 203 /* X Edge Greater Than register */ 204 #define P9000_X_EDGE_GREATER 0x000001ac 205 /* Y Edge Less Than register */ 206 #define P9000_Y_EDGE_LESS 0x000001b0 207 /* Y Edge Greater Than register */ 208 #define P9000_Y_EDGE_GREATER 0x000001b4 209 210 /* 211 * Drawing engine 212 */ 213 214 /* Colors - 8 bit for P9000, 32 bit for P9100 */ 215 #define P9000_DE_FG_COLOR 0x00000200 216 #define P9000_DE_BG_COLOR 0x00000204 217 #define P9100_DE_COLOR0 0x00000200 218 #define P9100_DE_COLOR1 0x00000204 219 #define P9100_DE_COLOR2 0x00000238 220 #define P9100_DE_COLOR3 0x0000023c 221 222 /* How to encode a colors in 8 and 16 bit mode, for the P9100 */ 223 #define P9100_COLOR8(c) ((c) | ((c) << 8) | ((c) << 16) | ((c) << 24)) 224 #define P9100_COLOR16(c) ((c) | ((c) << 16)) 225 226 /* Plane mask (8 bits on P9000, 32 bits on P9100) */ 227 #define P9000_DE_PLANEMASK 0x00000208 228 229 /* Drawing mode */ 230 #define P9000_DE_DRAWMODE 0x0000020c 231 #define DM_PICK_CONTROL 0x00000008 232 #define DM_PICK_ENABLE 0x00000004 233 #define DM_BUFFER_CONTROL 0x00000002 234 #define DM_BUFFER_ENABLE0 0x00000000 235 #define DM_BUFFER_ENABLE1 0x00000001 236 237 /* Pattern Origin (4 bit x 4 bit offset) */ 238 #define P9000_DE_PATTERN_ORIGIN_X 0x00000210 239 #define P9000_DE_PATTERN_ORIGIN_Y 0x00000214 240 241 /* Raster operation */ 242 #define P9000_DE_RASTER 0x00000218 243 #define P9100_RASTER_NO_SOLID 0x00002000 244 #define P9100_RASTER_PATTERN_4COLOR 0x00004000 245 #define P9100_RASTER_PIXEL1_TRANSPARENT 0x00008000 246 #define P9000_RASTER_QUAD_OVERSIZE 0x00010000 247 #define P9000_RASTER_QUAD_PATTERN 0x00020000 248 249 /* Raster minterms */ 250 #define P9000_RASTER_SRC 0xcccc 251 #define P9000_RASTER_DST 0xaaaa 252 #define P9000_RASTER_PATTERN 0xff00 253 #define P9000_RASTER_MASK 0xffff 254 #define P9100_RASTER_SRC 0x00cc 255 #define P9100_RASTER_DST 0x00aa 256 #define P9100_RASTER_PATTERN 0x00f0 257 #define P9100_RASTER_MASK 0x00ff 258 259 /* Pixel8 excess storage */ 260 #define P9000_DE_PIXEL8 0x0000021c 261 262 /* Clipping window - same as in PE */ 263 #define P9000_DE_WINMIN 0x00000220 264 #define P9000_DE_WINMAX 0x00000224 265 266 /* Quad pattern - up to 4 items on P9000, 8 on P9100 */ 267 #define P9000_DE_PATTERN(index) (0x00000280 + ((index) << 2)) 268 269 /* User pattern - up to 4 items */ 270 #define P9000_DE_USER(index) (0x00000290 + ((index) << 2)) 271 272 /* Byte clipping window */ 273 #define P9100_DE_B_WINMIN 0x000002a0 274 #define P9100_DE_B_WINMAX 0x000002a4 275 276 /* 277 * Coordinates 278 */ 279 280 /* 32 bit X value */ 281 #define P9000_COORD_X 0x00000008 282 /* 32 bit Y value */ 283 #define P9000_COORD_Y 0x00000010 284 /* 16 bit X, 16 bit Y values packed */ 285 #define P9000_COORD_XY 0x00000018 286 287 /* Absolute (screen) coordinates */ 288 #define P9000_COORD_ABS 0x00000000 289 /* Relative (in-window) coordinates */ 290 #define P9000_COORD_REL 0x00000020 291 292 /* How to pack a x16y16 value - note that they are in fact 12 bit values */ 293 #define P9000_COORDS(x,y) ((((x) & 0x0fff) << 16) | ((y) & 0x0fff)) 294 295 /* Device coordinates - 4 edges */ 296 #define P9000_DC_COORD(index) (0x00001000 + ((index) * 0x40)) 297 298 /* Load coordinates */ 299 #define P9000_LC_POINT 0x00001200 300 #define P9000_LC_LINE 0x00001240 301 #define P9000_LC_TRI 0x00001280 302 #define P9000_LC_QUAD 0x000012c0 303 #define P9000_LC_RECT 0x00001300 304