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Searched refs:PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v6_0.c1762 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); in gfx_v6_0_constants_init()
H A Dgfx_v7_0.c2002 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); in gfx_v7_0_constants_init()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5617 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 macro
H A Dgfx_7_2_sh_mask.h5670 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
H A Dgfx_8_0_sh_mask.h6458 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
H A Dgfx_8_1_sh_mask.h6992 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1630 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_9_1_sh_mask.h1493 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1456 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h1560 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h14988 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h6900 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h7150 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h7750 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h7460 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro