1 /* $OpenBSD: pccbbreg.h,v 1.12 2012/10/18 21:40:49 deraadt Exp $ */ 2 /* $NetBSD: pccbbreg.h,v 1.5 2000/06/07 09:02:47 haya Exp $ */ 3 /* 4 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef _DEV_PCI_PCCBBREG_H_ 28 #define _DEV_PCI_PCCBBREG_H_ 29 30 #define PCI_SOCKBASE 0x10 /* Socket Base Address Register */ 31 #define PCI_BUSNUM 0x18 /* Latency timer, Subordinate bus number */ 32 #define PCI_BCR_INTR 0x3C /* Intr line, intr pin, bridge control regs */ 33 #define PCI_LEGACY 0x44 /* Legacy IO register address (32 bits) */ 34 #define PCI_SYSCTRL 0x80 /* System control */ 35 #define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */ 36 37 #define PCI_CLASS_INTERFACE_MASK 0xFFFFFF00 38 #define PCI_CLASS_INTERFACE_YENTA 0x06070000 39 40 /* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */ 41 #define PCI_CB_LSCP_REG 0x18 42 43 /* CardBus memory and io windows */ 44 #define PCI_CB_MEMBASE0 0x1C 45 #define PCI_CB_MEMLIMIT0 0x20 46 #define PCI_CB_MEMBASE1 0x24 47 #define PCI_CB_MEMLIMIT1 0x28 48 #define PCI_CB_IOBASE0 0x2C 49 #define PCI_CB_IOLIMIT0 0x30 50 #define PCI_CB_IOBASE1 0x34 51 #define PCI_CB_IOLIMIT1 0x38 52 53 /* PCI_CB_LSCP_REG */ 54 #define PCI_CB_LATENCY_SHIFT 24 55 #define PCI_CB_LATENCY_MASK 0xFF 56 #define PCI_CB_LATENCY(x)( \ 57 ((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK) 58 59 /* 60 * Cardbus socket registers 61 */ 62 #define CB_SOCKET_EVENT 0x00 /* Event */ 63 #define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */ 64 #define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */ 65 #define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */ 66 #define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */ 67 #define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */ 68 69 #define CB_SOCKET_MASK 0x04 /* Mask */ 70 #define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */ 71 #define CB_SOCKET_MASK_CD 0x06 /* CD event mask */ 72 #define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */ 73 74 #define CB_SOCKET_STAT 0x08 /* Present-state */ 75 #define CB_SOCKET_STAT_CARDSTS 0x00000001 /* Card status change bit */ 76 #define CB_SOCKET_STAT_CD1 0x00000002 /* Card detect 1 */ 77 #define CB_SOCKET_STAT_CD2 0x00000004 /* Card detect 2 */ 78 #define CB_SOCKET_STAT_CD 0x00000006 /* Card detect 1 and 2 */ 79 #define CB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power cycle */ 80 #define CB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit card */ 81 #define CB_SOCKET_STAT_CB 0x00000020 /* Cardbus card */ 82 #define CB_SOCKET_STAT_IREQ 0x00000040 /* READY(~IREQ)//(~CINT) */ 83 /* bit */ 84 #define CB_SOCKET_STAT_NOTCARD 0x00000080 /* Inserted card is */ 85 /* unrecognisable */ 86 #define CB_SOCKET_STAT_DATALOST 0x00000100 /* Data lost */ 87 #define CB_SOCKET_STAT_BADVCC 0x00000200 /* Bad Vcc Request */ 88 #define CB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 89 #define CB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 90 #define CB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 91 #define CB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 92 #define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 93 #define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 94 #define CB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 95 #define CB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 96 97 #define CB_SOCKET_FORCE 0x0C /* Force event */ 98 #define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 99 100 #define CB_SOCKET_CTRL 0x10 /* Control */ 101 #define CB_SOCKET_CTRL_VPPMASK 0x007 102 #define CB_SOCKET_CTRL_VPP_OFF 0x000 103 #define CB_SOCKET_CTRL_VPP_12V 0x001 104 #define CB_SOCKET_CTRL_VPP_5V 0x002 105 #define CB_SOCKET_CTRL_VPP_3V 0x003 106 #define CB_SOCKET_CTRL_VPP_XV 0x004 107 #define CB_SOCKET_CTRL_VPP_YV 0x005 108 109 #define CB_SOCKET_CTRL_VCCMASK 0x070 110 #define CB_SOCKET_CTRL_VCC_OFF 0x000 111 #define CB_SOCKET_CTRL_VCC_5V 0x020 112 #define CB_SOCKET_CTRL_VCC_3V 0x030 113 #define CB_SOCKET_CTRL_VCC_XV 0x040 114 #define CB_SOCKET_CTRL_VCC_YV 0x050 115 116 #define CB_SOCKET_CTRL_STOPCLK 0x080 117 118 #define PCCBB_SOCKEVENT_BITS "\020\001CSTS\002CD1\003CD2\004PWR" 119 #define PCCBB_SOCKSTATE_BITS \ 120 "\020\001CSTS\002CD1\003CD3\004PWR\00516BIT\006CB\007CINT\010NOTA" \ 121 "\011DLOST\012BADVCC\0135v\0143v\015Xv\016Yv\0355vS\0363vS\037XvS\040YvS" 122 123 /* PCI_BCR_INTR bits for generic PCI-CardBus bridge */ 124 #define CB_BCR_RESET_ENABLE 0x00400000 125 #define CB_BCR_INTR_IREQ_ENABLE 0x00800000 126 #define CB_BCR_PREFETCH_MEMWIN0 0x01000000 127 #define CB_BCR_PREFETCH_MEMWIN1 0x02000000 128 #define CB_BCR_WRITE_POST_ENABLE 0x04000000 129 130 /* TI [14][245]xx */ 131 #define PCI12XX_MMCTRL 0x84 132 133 /* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */ 134 #define PCI12XX_MFUNC 0x8c 135 #define PCI12XX_MFUNC_PIN0 0x0000000F 136 #define PCI12XX_MFUNC_PIN0_INTA 0x02 137 #define PCI12XX_MFUNC_PIN1 0x000000F0 138 #define PCI12XX_MFUNC_PIN1_INTB 0x20 139 #define PCI12XX_MFUNC_PIN2 0x00000F00 140 #define PCI12XX_MFUNC_PIN3 0x0000F000 141 #define PCI12XX_MFUNC_PIN3_INTSER 0x00001000 142 #define PCI12XX_MFUNC_PIN4 0x000F0000 143 #define PCI12XX_MFUNC_PIN5 0x00F00000 144 #define PCI12XX_MFUNC_PIN6 0x0F000000 145 #define PCI12XX_MFUNC_DEFAULT PCI12XX_MFUNC_PIN3_INTSER 146 147 /* PCI_CBCTRL bits for TI PCI113X */ 148 #define PCI113X_CBCTRL_INT_SERIAL 0x040000 149 #define PCI113X_CBCTRL_INT_ISA 0x020000 150 #define PCI113X_CBCTRL_INT_MASK 0x060000 151 #define PCI113X_CBCTRL_RIENB 0x008000 /* Ring indicate output */ 152 /* enable */ 153 #define PCI113X_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */ 154 #define PCI113X_CBCTRL_PCI_IRQ_ENA 0x002000 /* PCI intr enable */ 155 /* (funct and CSC) */ 156 #define PCI113X_CBCTRL_PCI_INTR 0x001000 /* PCI functional intr req */ 157 #define PCI113X_CBCTRL_PCI_CSC 0x000800 /* CSC intr route to PCI */ 158 #define PCI113X_CBCTRL_PCI_CSC_D 0x000400 /* Unknown */ 159 #define PCI113X_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */ 160 #define PCI113X_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */ 161 /* detect */ 162 163 /* PCI_CBCTRL bits for TI PCI12XX */ 164 #define PCI12XX_SYSCTRL_INTRTIE 0x20000000u 165 #define PCI12XX_SYSCTRL_VCCPROT 0x200000 166 #define PCI12XX_SYSCTRL_PWRSAVE 0x000040 167 #define PCI12XX_SYSCTRL_SUBSYSRW 0x000020 168 #define PCI12XX_SYSCTRL_CB_DPAR 0x000010 169 #define PCI12XX_SYSCTRL_CDMA_EN 0x000008 170 #define PCI12XX_SYSCTRL_KEEPCLK 0x000002 171 #define PCI12XX_SYSCTRL_RIMUX 0x000001 172 #define PCI12XX_CBCTRL_CSC 0x20000000u 173 #define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u 174 #define PCI12XX_CBCTRL_INT_SERIAL 0x060000 175 #define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000 176 #define PCI12XX_CBCTRL_INT_ISA 0x020000 177 #define PCI12XX_CBCTRL_INT_PCI 0x000000 178 #define PCI12XX_CBCTRL_INT_MASK 0x060000 179 #define PCI12XX_CBCTRL_RIENB 0x008000 /* Ring indicate output */ 180 /* enable */ 181 #define PCI12XX_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */ 182 #define PCI12XX_CBCTRL_AUD2MUX 0x000400 /* Unknown */ 183 #define PCI12XX_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */ 184 #define PCI12XX_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */ 185 /* detect */ 186 187 188 /* PCI_BCR_INTR additional bit for Rx5C46[567] */ 189 #define CB_BCRI_RL_3E0_ENA 0x08000000 190 #define CB_BCRI_RL_3E2_ENA 0x10000000 191 192 /* 193 * Special register definition for Toshiba ToPIC95/97 194 * These values are borrowed from pcmcia-cs/Linux. 195 */ 196 #define TOPIC_SOCKET_CTRL 0x90 197 #define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 198 199 #define TOPIC_SLOT_CTRL 0xA0 200 #define TOPIC_SLOT_CTRL_SLOTON 0x00000080 201 #define TOPIC_SLOT_CTRL_SLOTEN 0x00000040 202 #define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020 203 #define TOPIC_SLOT_CTRL_ID_WP 0x00000010 204 #define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000C 205 #define TOPIC_SLOT_CTRL_PORT_SHIFT 2 206 #define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003 207 #define TOPIC_SLOT_CTRL_OSF_SHIFT 0 208 209 #define TOPIC_SLOT_CTRL_INTB 0x00002000 210 #define TOPIC_SLOT_CTRL_INTA 0x00001000 211 #define TOPIC_SLOT_CTRL_INT_MASK 0x00003000 212 #define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000C00 213 #define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */ 214 #define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */ 215 #define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* No clock */ 216 #define TOPIC97_SLOT_CTRL_STSIRQP 0x00000400 /* Status change intr */ 217 /* pulse */ 218 #define TOPIC97_SLOT_CTRL_IRQP 0x00000200 /* Function intr pulse */ 219 #define TOPIC97_SLOT_CTRL_PCIINT 0x00000100 /* Intr routing to PCI INT */ 220 221 #define TOPIC_SLOT_CTRL_CARDBUS 0x80000000 222 #define TOPIC_SLOT_CTRL_VS1 0x04000000 223 #define TOPIC_SLOT_CTRL_VS2 0x02000000 224 #define TOPIC_SLOT_CTRL_SWDETECT 0x01000000 225 226 #define TOPIC_REG_CTRL 0x00A4 227 #define TOPIC_REG_CTRL_RESUME_RESET 0x80000000 228 #define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000 229 #define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000 230 #define TOPIC97_REG_CTRL_TESTMODE 0x10000000 231 #define TOPIC97_REG_CTRL_IOPLUP 0x08000000 232 #define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000 233 #define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000 234 #define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000F800 235 #define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11 236 #define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004 237 #define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002 238 #define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001 239 240 /* 241 * Additional O2Micro registers 242 * 243 * 'reserved' register at 0x94/D4. allows setting read prefetch and write 244 * bursting. read prefetching for example makes the RME Hammerfall DSP 245 * working. for some bridges it is at 0x94, for others at 0xD4. it's 246 * ok to write to both registers on all O2 bridges. 247 * from Eric Still, 02Micro. 248 */ 249 #define O2MICRO_RESERVED1 0x94 250 #define O2MICRO_RESERVED2 0xD4 251 #define O2MICRO_RES_READ_PREFETCH 0x02 252 #define O2MICRO_RES_WRITE_BURST 0x08 253 254 #endif /* _DEV_PCI_PCCBBREG_H_ */ 255