1 /* $OpenBSD: nsphyterreg.h,v 1.2 2008/06/26 05:42:16 ray Exp $ */ 2 /* $NetBSD: nsphyterreg.h,v 1.1 1999/12/07 19:36:37 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_MII_NSPHYTERREG_H_ 35 #define _DEV_MII_NSPHYTERREG_H_ 36 37 /* 38 * DP83843 registers. 39 */ 40 41 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */ 42 #define PHYSTS_REL 0x8000 /* receive error latch */ 43 #define PHYSTS_CIML 0x4000 /* CIM latch */ 44 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */ 45 #define PHYSTS_DEVRDY 0x0800 /* device ready */ 46 #define PHYSTS_PGRX 0x0400 /* page received */ 47 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */ 48 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */ 49 #define PHYSTS_REMFAULT 0x0080 /* remote fault */ 50 #define PHYSTS_JABBER 0x0040 /* jabber detect */ 51 #define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */ 52 #define PHYSTS_RESETSTAT 0x0010 /* reset status */ 53 #define PHYSTS_LOOPBACK 0x0008 /* loopback status */ 54 #define PHYSTS_DUPLEX 0x0004 /* full duplex */ 55 #define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */ 56 #define PHYSTS_LINK 0x0001 /* link up */ 57 58 59 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific 60 control */ 61 62 #define MIPSCR_INTEN 0x0002 /* interrupt enable */ 63 #define MIPSCR_TINT 0x0001 /* test interrupt */ 64 65 66 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic 67 status */ 68 #define MIPGSR_MINT 0x8000 /* MII interrupt pending */ 69 70 #define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */ 71 72 #define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */ 73 74 #define MII_NSPHYTER_RECR 0x15 /* Receive error counter */ 75 76 77 #define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */ 78 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */ 79 #define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */ 80 #define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */ 81 #define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */ 82 #define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */ 83 #define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */ 84 #define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */ 85 #define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */ 86 #define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */ 87 #define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */ 88 #define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */ 89 #define PCSR_CODE_ERR 0x0008 /* code errors */ 90 #define PCSR_PME_ERR 0x0004 /* premature end errors */ 91 #define PCSR_LINK_ERR 0x0002 /* link errors */ 92 #define PCSR_PKT_ERR 0x0001 /* packet errors */ 93 94 95 #define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */ 96 #define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */ 97 #define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */ 98 #define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */ 99 #define LBR_BP_RX 0x0800 /* bypass receive function */ 100 #define LBR_BP_TX 0x0400 /* bypass transmit function */ 101 #define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */ 102 #define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */ 103 #define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */ 104 105 106 #define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */ 107 #define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */ 108 #define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */ 109 #define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */ 110 #define BTSCR_POL_DS 0x0400 /* polarity detection and correction 111 disable */ 112 #define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */ 113 #define BTSCR_LP_DS 0x0100 /* link pulse disable */ 114 #define BTSCR_HB_DS 0x0080 /* heartbeat disabled */ 115 #define BTSCR_LS_SEL 0x0040 /* low squelch select */ 116 #define BTSCR_AUI_SEL 0x0020 /* AUI select */ 117 #define BTSCR_JAB_DS 0x0010 /* jabber disable */ 118 #define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */ 119 #define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */ 120 121 122 #define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */ 123 #define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */ 124 #define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */ 125 #define PHYCTRL_REPEATER 0x0200 /* repeater mode */ 126 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */ 127 #define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */ 128 #define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */ 129 #define PHYCTRL_PHYADDR 0x001f /* PHY address */ 130 131 #endif /* _DEV_MII_NSPHYTERREG_H_ */ 132