1 /* $OpenBSD: pciide_piix_reg.h,v 1.13 2022/01/09 05:42:58 jsg Exp $ */ 2 /* $NetBSD: pciide_piix_reg.h,v 1.5 2001/01/05 15:29:40 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_PCI_PCIIDE_PIIX_REG_H_ 30 #define _DEV_PCI_PCIIDE_PIIX_REG_H_ 31 32 /* 33 * Registers definitions for Intel's PIIX series PCI IDE controllers. 34 * See Intel's 35 * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" 36 * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and 37 * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub" 38 * available from http://developer.intel.com/ 39 */ 40 41 /* 42 * Bus master interface base address register 43 */ 44 #define PIIX_BMIBA 0x20 45 #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0) 46 #define PIIX_BMIBA_RTE(x) (x & 0x000000001) 47 #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */ 48 49 /* 50 * IDE timing register 51 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel 52 */ 53 #define PIIX_IDETIM 0x40 54 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF) 55 #define PIIX_IDETIM_SET(x, bytes, channel) \ 56 ((x) | ((bytes) << (16 * (channel)))) 57 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \ 58 ((x) & ~((bytes) << (16 * (channel)))) 59 60 #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */ 61 #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers 62 enabled (PIIX3/4 only) */ 63 #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */ 64 #define PIIX_IDETIM_ISP_SHIFT 12 65 #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT) 66 #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */ 67 #define PIIX_IDETIM_RTC_SHIFT 8 68 #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT) 69 #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */ 70 #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */ 71 #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */ 72 #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */ 73 /* 74 * Slave IDE timing register (PIIX3/4 only) 75 * This register must be enabled via the PIIX_IDETIM_SITRE bit 76 */ 77 #define PIIX_SIDETIM 0x44 78 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4)) 79 #define PIIX_SIDETIM_ISP_SHIFT 2 80 #define PIIX_SIDETIM_ISP_SET(x, channel) \ 81 (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4))) 82 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4)) 83 #define PIIX_SIDETIM_RTC_SHIFT 0 84 #define PIIX_SIDETIM_RTC_SET(x, channel) \ 85 (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4))) 86 87 /* 88 * Ultra DMA/33 register (PIIX4 only) 89 */ 90 #define PIIX_UDMAREG 0x48 91 /* Control register */ 92 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive))) 93 /* Ultra DMA/33 timing register (PIIX4 only) */ 94 #define PIIX_UDMATIM_SHIFT 16 95 #define PIIX_UDMATIM_SET(x, channel, drive) \ 96 (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT) 97 98 /* 99 * IDE config register (ICH/ICH0/ICH2 only) 100 */ 101 #define PIIX_CONFIG 0x54 102 #define PIIX_CONFIG_PINGPONG 0x0400 103 /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */ 104 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive))) 105 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive))) 106 /* The following are only for the 82801BA (ICH2) */ 107 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive))) 108 109 /* 110 * these tables define the different values to upload to the 111 * ISP and RTC registers for the various PIO and DMA mode 112 * (from the PIIX4 doc). 113 */ 114 static int8_t piix_isp_pio[] = {0x00, 0x00, 0x01, 0x02, 0x02}; 115 static int8_t piix_rtc_pio[] = {0x00, 0x00, 0x00, 0x01, 0x03}; 116 static int8_t piix_isp_dma[] = {0x00, 0x02, 0x02}; 117 static int8_t piix_rtc_dma[] = {0x00, 0x02, 0x03}; 118 static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02, 0x01, 0x02, 0x01}; 119 120 /* 121 * ICH5/ICH5R SATA registers definitions 122 */ 123 #define ICH5_SATA_MAP 0x90 /* Address Map Register */ 124 #define ICH5_SATA_MAP_MV_MASK 0x07 /* Map Value mask */ 125 #define ICH5_SATA_MAP_COMBINED 0x04 /* Combined mode */ 126 127 #define ICH5_SATA_PI 0x09 /* Program Interface register */ 128 #define ICH5_SATA_PI_PRI_NATIVE 0x01 /* Put Pri IDE channel in native mode */ 129 #define ICH5_SATA_PI_SEC_NATIVE 0x04 /* Put Sec IDE channel in native mode */ 130 131 #define ICH_SATA_PCS 0x92 /* Port Control and Status Register */ 132 #define ICH_SATA_PCS_P0E 0x01 /* Port 0 enabled */ 133 #define ICH_SATA_PCS_P1E 0x02 /* Port 1 enabled */ 134 #define ICH_SATA_PCS_P0P 0x10 /* Port 0 present */ 135 #define ICH_SATA_PCS_P1P 0x20 /* Port 1 present */ 136 137 /* 138 * ICH6/ICH7 SATA registers definitions 139 */ 140 #define ICH6_SATA_MAP_CMB_MASK 0x03 /* Combined mode bits */ 141 #define ICH6_SATA_MAP_CMB_PRI 0x01 /* Combined mode, IDE Primary */ 142 #define ICH6_SATA_MAP_CMB_SEC 0x02 /* Combined mode, IDE Secondary */ 143 #define ICH7_SATA_MAP_SMS_MASK 0xc0 /* SATA Mode Select */ 144 #define ICH7_SATA_MAP_SMS_IDE 0x00 145 #define ICH7_SATA_MAP_SMS_AHCI 0x40 146 #define ICH7_SATA_MAP_SMS_RAID 0x80 147 148 149 #endif /* !_DEV_PCI_PCIIDE_PIIX_REG_H_ */ 150