1 /* $OpenBSD: ppbreg.h,v 1.6 2020/05/23 07:58:24 patrick Exp $ */ 2 /* $NetBSD: ppbreg.h,v 1.3 2001/07/06 18:07:16 mcr Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI-PCI Bridge chip register definitions and macros. 36 * Derived from information found in the ``PCI to PCI Bridge 37 * Architecture Specification, Revision 1.0, April 5, 1994.'' 38 * 39 * XXX much is missing. 40 */ 41 42 /* 43 * PCI Programming Interface register. 44 */ 45 #define PPB_INTERFACE_SUBTRACTIVE 0x01 46 47 /* 48 * Register offsets 49 */ 50 #define PPB_REG_BASE0 0x10 /* Base Addr Reg. 0 */ 51 #define PPB_REG_BASE1 0x14 /* Base Addr Reg. 1 */ 52 #define PPB_REG_BUSINFO 0x18 /* Bus information */ 53 #define PPB_REG_IOSTATUS 0x1c /* I/O base+lim & sec stat */ 54 #define PPB_REG_MEM 0x20 /* Memory base/limit */ 55 #define PPB_REG_PREFMEM 0x24 /* Pref Mem base/limit */ 56 #define PPB_REG_PREFBASE_HI32 0x28 /* Pref Mem base high bits */ 57 #define PPB_REG_PREFLIM_HI32 0x2c /* Pref Mem lim high bits */ 58 #define PPB_REG_IO_HI 0x30 /* I/O base+lim high bits */ 59 #define PPB_REG_BRIDGECONTROL 0x3c /* bridge control register */ 60 61 /* 62 * Macros to extract the contents of the "Bus Info" register. 63 */ 64 #define PPB_BUSINFO_PRIMARY(bir) \ 65 ((bir >> 0) & 0xff) 66 #define PPB_BUSINFO_SECONDARY(bir) \ 67 ((bir >> 8) & 0xff) 68 #define PPB_BUSINFO_SUBORDINATE(bir) \ 69 ((bir >> 16) & 0xff) 70 #define PPB_BUSINFO_SECLAT(bir) \ 71 ((bir >> 24) & 0xff) 72 73 /* 74 * Routine to translate between secondary bus interrupt pin/device number and 75 * primary bus interrupt pin number. 76 */ 77 #define PPB_INTERRUPT_SWIZZLE(pin, device) \ 78 ((((pin) + (device) - 1) % 4) + 1) 79 80 /* 81 * secondary bus I/O base and limits 82 */ 83 #define PPB_IOBASE_SHIFT 0 84 #define PPB_IOLIMIT_SHIFT 8 85 #define PPB_IO_MASK 0xf000 86 #define PPB_IO_32BIT 0x0001 87 #define PPB_IO_SHIFT 8 88 #define PPB_IO_MIN 4096 89 90 /* 91 * secondary bus memory base and limits 92 */ 93 #define PPB_MEMBASE_SHIFT 0 94 #define PPB_MEMLIMIT_SHIFT 16 95 #define PPB_MEM_MASK 0xfff00000 96 #define PPB_MEM_SHIFT 16 97 #define PPB_MEM_MIN 0x00100000 98 99 /* 100 * bridge control register (see table 3.9 of ppb rev. 1.1) 101 * 102 * Note these are in the *upper* 16 bits of the Bridge Control 103 * Register (the bottom 16 are Interrupt Line and Interrupt Pin). 104 */ 105 #define PPB_BC_BITBASE 16 106 107 #define PPB_BC_PARITYERRORRESPONSE_ENABLE (1U << (0 + PPB_BC_BITBASE)) 108 #define PPB_BC_SERR_ENABLE (1U << (1 + PPB_BC_BITBASE)) 109 #define PPB_BC_ISA_ENABLE (1U << (2 + PPB_BC_BITBASE)) 110 #define PPB_BC_VGA_ENABLE (1U << (3 + PPB_BC_BITBASE)) 111 #define PPB_BC_MASTER_ABORT_MODE (1U << (5 + PPB_BC_BITBASE)) 112 #define PPB_BC_SECONDARY_RESET (1U << (6 + PPB_BC_BITBASE)) 113 #define PPB_BC_FAST_B2B_ENABLE (1U << (7 + PPB_BC_BITBASE)) 114 /* PCI 2.2 */ 115 #define PPB_BC_PRIMARY_DISCARD_TIMEOUT (1U << (8 + PPB_BC_BITBASE)) 116 #define PPB_BC_SECONDARY_DISCARD_TIMEOUT (1U << (9 + PPB_BC_BITBASE)) 117 #define PPB_BC_DISCARD_TIMER_STATUS (1U << (10 + PPB_BC_BITBASE)) 118 #define PPB_BC_DISCARD_TIMER_SERR_ENABLE (1U << (11 + PPB_BC_BITBASE)) 119