xref: /openbsd/sys/arch/powerpc/include/pte.h (revision 9bd4dd0f)
1 /*	$OpenBSD: pte.h,v 1.11 2023/01/31 01:27:58 gkoehler Exp $	*/
2 /*	$NetBSD: pte.h,v 1.1 1996/09/30 16:34:32 ws Exp $	*/
3 
4 /*-
5  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6  * Copyright (C) 1995, 1996 TooLs GmbH.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed by TooLs GmbH.
20  * 4. The name of TooLs GmbH may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef	_POWERPC_PTE_H_
36 #define	_POWERPC_PTE_H_
37 
38 /*
39  * Page Table Entries
40  */
41 #ifndef	_LOCORE
42 struct pte_32 {
43 	u_int32_t pte_hi;
44 	u_int32_t pte_lo;
45 };
46 struct pte_64 {
47 	u_int64_t pte_hi;
48 	u_int64_t pte_lo;
49 };
50 #endif	/* _LOCORE */
51 
52 /* 32 bit */
53 /* High word: */
54 #define	PTE_VALID_32	0x80000000
55 #define	PTE_VSID_SHIFT_32	7
56 #define	PTE_HID_32	0x00000040
57 #define	PTE_API_32	0x0000003f
58  /* Low word: */
59 #define	PTE_RPGN_32	0xfffff000
60 #define	PTE_REF_32	0x00000100
61 #define	PTE_CHG_32	0x00000080
62 #define	PTE_WIM_32	0x00000078
63 #define	PTE_W_32	0x00000040
64 #define	PTE_EXE_32	0x00000040 /* only used in pmap_attr, same as PTE_W */
65 #define	PTE_I_32	0x00000020
66 #define	PTE_M_32	0x00000010
67 #define	PTE_G_32	0x00000008
68 #define	PTE_PP_32	0x00000003
69 #define	PTE_RO_32	0x00000003
70 #define	PTE_RW_32	0x00000002
71 
72 
73 /* 64 bit */
74 /* High doubleword: */
75 #define	PTE_VALID_64		0x0000000000000001ULL
76 #define	PTE_AVPN_SHIFT_64	7
77 #define PTE_AVPN_64		0xffffffffffffff80ULL
78 #define PTE_API_SHIFT_64	7
79 #define PTE_API_64		0x0000000000000f80ULL
80 #define PTE_VSID_SHIFT_64  12
81 #define PTE_VSID_64		0xfffffffffffff000ULL
82 #define	PTE_HID_64		0x0000000000000002ULL
83 /* Low word: */
84 #define	PTE_RPGN_64		0x3ffffffffffff000ULL
85 #define	PTE_AC_64		0x0000000000000200ULL
86 #define	PTE_REF_64		0x0000000000000100ULL
87 #define	PTE_CHG_64		0x0000000000000080ULL
88 #define	PTE_WIMG_64		0x0000000000000078ULL
89 #define	PTE_W_64		0x0000000000000040ULL
90 #define PTE_EXE_64		PTE_W
91 #define	PTE_I_64		0x0000000000000020ULL
92 #define	PTE_M_64		0x0000000000000010ULL
93 #define	PTE_G_64		0x0000000000000008ULL
94 #define PTE_N_64		0x0000000000000004ULL
95 #define	PTE_PP_64		0x0000000000000003ULL
96 #define	PTE_RO_64		0x0000000000000003ULL
97 #define	PTE_RW_64		0x0000000000000002ULL
98 
99 /*
100  * Extract bits from address
101  */
102 #define	ADDR_SR_SHIFT		28
103 #define	ADDR_PIDX		0x0ffff000
104 #define	ADDR_PIDX_SHIFT		12
105 #define	ADDR_API_SHIFT_32	22
106 #define	ADDR_API_SHIFT_64	16
107 #define	ADDR_POFF		0x00000fff
108 
109 /*
110  * Bits in DSISR:
111  */
112 #define	DSISR_DIRECT	0x80000000
113 #define	DSISR_NOTFOUND	0x40000000
114 #define	DSISR_PROTECT	0x08000000
115 #define	DSISR_INVRX	0x04000000
116 #define	DSISR_STORE	0x02000000
117 #define	DSISR_DABR	0x00400000
118 #define	DSISR_SEGMENT	0x00200000
119 #define	DSISR_EAR	0x00100000
120 
121 /*
122  * Bits in SRR1 on ISI:
123  */
124 #define	ISSRR1_NOTFOUND	0x40000000
125 #define	ISSRR1_DIRECT	0x10000000
126 #define	ISSRR1_PROTECT	0x08000000
127 #define	ISSRR1_SEGMENT	0x00200000
128 
129 #endif	/* _POWERPC_PTE_H_ */
130