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Searched refs:PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_sh_mask.h55159 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddpcs_4_2_0_sh_mask.h374 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddpcs_4_2_2_sh_mask.h363 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddpcs_4_2_3_sh_mask.h380 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_sh_mask.h46558 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddcn_3_1_5_sh_mask.h44837 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddcn_3_1_4_sh_mask.h48863 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro
H A Ddcn_3_1_6_sh_mask.h48183 #define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK … macro